Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8571818	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9149232

1

T1

8

T2

7

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	17088841	1			T1	7		T2	7		T3	3
values[0x0]	315219	1			T1	4		T2	6		T3	2
values[0x1]	316990	1			T1	3		T2	5		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6810687	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

10910363

1

T1

9

T2

12

T3

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	64541	1			T63	6		T33	6		T18	4
valid_sources[0x01]	78749	1			T30	1		T40	1		T86	1
valid_sources[0x02]	85910	1			T29	1		T63	1		T33	8
valid_sources[0x03]	53030	1			T63	1		T33	4		T19	8
valid_sources[0x04]	52762	1			T30	2		T63	3		T33	14
valid_sources[0x05]	73652	1			T63	3		T33	25		T7	2
valid_sources[0x06]	60867	1			T33	2		T19	4		T23	69
valid_sources[0x07]	83219	1			T63	4		T33	29		T7	1
valid_sources[0x08]	54564	1			T28	2		T33	2		T7	1
valid_sources[0x09]	53751	1			T33	3		T7	2		T19	10
valid_sources[0x0a]	94642	1			T2	11		T33	4		T7	1
valid_sources[0x0b]	80240	1			T63	5		T33	17		T7	2
valid_sources[0x0c]	52690	1			T29	2		T63	8		T35	15
valid_sources[0x0d]	52561	1			T39	2		T63	3		T86	1
valid_sources[0x0e]	53613	1			T39	1		T63	4		T33	8
valid_sources[0x0f]	69331	1			T33	14		T19	3		T23	89
valid_sources[0x10]	53141	1			T63	10		T86	2		T33	3
valid_sources[0x11]	53272	1			T33	10		T48	1		T37	1
valid_sources[0x12]	54103	1			T63	5		T33	16		T19	1
valid_sources[0x13]	63274	1			T33	23		T7	1		T19	18
valid_sources[0x14]	53931	1			T1	2		T29	1		T63	2
valid_sources[0x15]	54227	1			T30	1		T33	10		T19	3
valid_sources[0x16]	54476	1			T30	4		T33	4		T7	1
valid_sources[0x17]	52935	1			T40	1		T41	1		T42	51
valid_sources[0x18]	69484	1			T63	4		T33	16		T36	1
valid_sources[0x19]	53590	1			T29	1		T33	29		T7	1
valid_sources[0x1a]	53344	1			T63	5		T33	11		T7	1
valid_sources[0x1b]	105110	1			T63	4		T86	1		T33	14
valid_sources[0x1c]	60863	1			T33	3		T7	1		T19	10
valid_sources[0x1d]	54641	1			T63	5		T33	20		T7	1
valid_sources[0x1e]	52552	1			T29	1		T30	2		T63	5
valid_sources[0x1f]	52766	1			T33	25		T7	1		T19	10
valid_sources[0x20]	149611	1			T30	3		T33	14		T7	2
valid_sources[0x21]	72341	1			T29	1		T63	5		T7	1
valid_sources[0x22]	52913	1			T33	14		T48	1		T7	4
valid_sources[0x23]	52930	1			T2	6		T30	2		T63	10
valid_sources[0x24]	53655	1			T39	1		T33	20		T7	2
valid_sources[0x25]	52176	1			T63	6		T33	50		T7	1
valid_sources[0x26]	101510	1			T33	12		T36	1		T19	9
valid_sources[0x27]	58618	1			T33	17		T7	1		T19	6
valid_sources[0x28]	67942	1			T86	1		T33	6		T7	3
valid_sources[0x29]	53011	1			T63	2		T86	1		T33	2
valid_sources[0x2a]	75728	1			T29	1		T63	2		T33	7
valid_sources[0x2b]	53174	1			T30	6		T63	11		T86	1
valid_sources[0x2c]	51468	1			T33	15		T19	6		T23	86
valid_sources[0x2d]	52878	1			T33	12		T19	5		T23	49
valid_sources[0x2e]	62003	1			T30	2		T33	11		T37	1
valid_sources[0x2f]	52643	1			T30	2		T33	24		T19	5
valid_sources[0x30]	66821	1			T29	1		T30	3		T63	8
valid_sources[0x31]	53833	1			T63	2		T33	5		T37	3
valid_sources[0x32]	88018	1			T28	1		T63	9		T86	1
valid_sources[0x33]	53456	1			T1	3		T86	1		T33	22
valid_sources[0x34]	52456	1			T30	1		T33	4		T19	10
valid_sources[0x35]	54233	1			T33	20		T7	2		T19	11
valid_sources[0x36]	67039	1			T30	1		T33	3		T19	8
valid_sources[0x37]	53865	1			T29	1		T30	1		T86	1
valid_sources[0x38]	52941	1			T30	1		T86	1		T33	2
valid_sources[0x39]	53021	1			T29	1		T63	1		T86	2
valid_sources[0x3a]	53844	1			T30	2		T63	1		T33	6
valid_sources[0x3b]	53854	1			T40	3		T63	4		T7	1
valid_sources[0x3c]	54499	1			T63	1		T33	6		T7	1
valid_sources[0x3d]	96899	1			T63	1		T33	11		T7	1
valid_sources[0x3e]	53043	1			T63	4		T86	1		T33	17
valid_sources[0x3f]	52976	1			T63	2		T86	1		T33	9
valid_sources[0x40]	52906	1			T28	1		T30	4		T33	3
valid_sources[0x41]	54489	1			T29	1		T63	4		T48	1
valid_sources[0x42]	95758	1			T30	5		T63	2		T33	13
valid_sources[0x43]	70737	1			T30	3		T63	6		T33	26
valid_sources[0x44]	56125	1			T33	19		T19	4		T23	81
valid_sources[0x45]	68835	1			T63	10		T33	42		T7	2
valid_sources[0x46]	54062	1			T29	1		T86	2		T33	3
valid_sources[0x47]	52939	1			T30	2		T7	2		T19	10
valid_sources[0x48]	53966	1			T33	5		T7	2		T19	8
valid_sources[0x49]	117837	1			T29	1		T30	3		T86	1
valid_sources[0x4a]	118018	1			T29	1		T33	3		T7	1
valid_sources[0x4b]	53130	1			T30	1		T33	2		T7	1
valid_sources[0x4c]	54573	1			T33	29		T19	3		T22	2
valid_sources[0x4d]	53519	1			T30	3		T63	1		T33	24
valid_sources[0x4e]	53568	1			T29	1		T30	2		T33	29
valid_sources[0x4f]	61188	1			T2	1		T29	1		T30	3
valid_sources[0x50]	118314	1			T30	2		T33	1		T34	2
valid_sources[0x51]	53223	1			T63	8		T33	4		T36	1
valid_sources[0x52]	53586	1			T30	6		T33	14		T7	1
valid_sources[0x53]	90336	1			T41	2		T33	8		T37	1
valid_sources[0x54]	54360	1			T28	1		T30	3		T63	1
valid_sources[0x55]	53366	1			T63	1		T33	29		T7	1
valid_sources[0x56]	53313	1			T29	1		T33	2		T36	3
valid_sources[0x57]	53942	1			T30	2		T33	2		T7	3
valid_sources[0x58]	93678	1			T30	1		T63	1		T33	14
valid_sources[0x59]	122318	1			T39	1		T63	2		T86	1
valid_sources[0x5a]	66990	1			T7	3		T19	3		T23	84
valid_sources[0x5b]	53078	1			T3	12		T29	1		T63	2
valid_sources[0x5c]	76334	1			T28	1		T63	1		T33	9
valid_sources[0x5d]	134371	1			T86	1		T33	16		T7	2
valid_sources[0x5e]	52986	1			T63	11		T33	7		T7	1
valid_sources[0x5f]	53337	1			T33	6		T37	1		T19	2
valid_sources[0x60]	69554	1			T30	1		T63	7		T33	6
valid_sources[0x61]	54029	1			T63	2		T33	19		T7	2
valid_sources[0x62]	53662	1			T30	3		T63	7		T33	28
valid_sources[0x63]	53933	1			T29	1		T30	3		T63	5
valid_sources[0x64]	89875	1			T29	1		T63	11		T86	1
valid_sources[0x65]	54369	1			T30	1		T63	12		T33	5
valid_sources[0x66]	53845	1			T28	1		T29	1		T63	2
valid_sources[0x67]	53493	1			T30	6		T63	2		T33	10
valid_sources[0x68]	77897	1			T30	1		T33	1		T36	1
valid_sources[0x69]	53298	1			T63	1		T33	8		T7	1
valid_sources[0x6a]	52594	1			T28	1		T33	24		T7	1
valid_sources[0x6b]	124546	1			T33	6		T19	6		T21	2
valid_sources[0x6c]	53036	1			T33	20		T17	1		T19	2
valid_sources[0x6d]	79755	1			T33	9		T19	3		T20	3
valid_sources[0x6e]	54498	1			T86	1		T33	1		T7	1
valid_sources[0x6f]	106323	1			T28	1		T29	1		T30	1
valid_sources[0x70]	53331	1			T30	4		T63	6		T33	5
valid_sources[0x71]	125709	1			T30	3		T86	1		T33	13
valid_sources[0x72]	104869	1			T30	1		T33	11		T19	13
valid_sources[0x73]	152052	1			T1	2		T30	5		T63	1
valid_sources[0x74]	119599	1			T30	1		T63	6		T33	33
valid_sources[0x75]	53708	1			T30	2		T33	33		T19	5
valid_sources[0x76]	79756	1			T1	1		T33	2		T19	2
valid_sources[0x77]	165623	1			T29	1		T33	5		T7	1
valid_sources[0x78]	63506	1			T29	1		T40	1		T63	5
valid_sources[0x79]	54297	1			T30	2		T63	3		T33	16
valid_sources[0x7a]	53997	1			T86	1		T33	8		T7	1
valid_sources[0x7b]	72115	1			T29	1		T7	3		T19	4
valid_sources[0x7c]	61723	1			T63	1		T86	1		T33	16
valid_sources[0x7d]	53339	1			T30	2		T63	4		T33	3
valid_sources[0x7e]	75798	1			T29	1		T33	8		T19	4
valid_sources[0x7f]	53537	1			T63	2		T33	5		T7	1
valid_sources[0x80]	52466	1			T30	1		T33	1		T7	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8637467

1

T1

6

T2

2

T3

1

values[0x0]

all_enables

biggest_size

263990

1

T1

1

T2

4

T3

2

values[0x1]

all_enables

biggest_size

247775

1

T1

1

T2

1

T3

3