Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

8586518

1

T1

6

T2

11

T3

6

full_word

9150329

1

T1

8

T2

7

T3

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	17736527	1			T1	14		T2	18		T3	12
auto[TlIntgErrCmd]	88	1			T269	4		T276	7		T277	2
auto[TlIntgErrData]	126	1			T269	3		T276	6		T277	3
auto[TlIntgErrBoth]	106	1			T269	3		T276	7		T277	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17090859

1

T1

7

T2

7

T3

3

auto[1]

645988

1

T1

7

T2

11

T3

9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8453070	1			T1	1		T2	5		T3	2
auto[TlIntgErrNone]	partial	auto[1]	133155	1			T1	5		T2	6		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	8637659	1			T1	6		T2	2		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	512643	1			T1	2		T2	5		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	28	1			T269	1		T276	1		T277	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T269	3		T276	6		T277	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T511	2		T512	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T505	1		T509	1		-	-
auto[TlIntgErrData]	partial	auto[0]	53	1			T269	1		T276	2		T277	2
auto[TlIntgErrData]	partial	auto[1]	61	1			T269	1		T276	3		T277	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T276	1		T513	1		T514	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T269	1		T291	1		T511	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T276	2		T277	1		T291	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T269	2		T276	4		T277	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T269	1		T277	1		T511	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T276	1		T291	1		T507	1