Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	577496061	12285	0	0
ep_in_enable_rd_A	577496061	1928	0	0
ep_out_enable_rd_A	577496061	1879	0	0
in_iso_rd_A	577496061	1652	0	0
intr_enable_rd_A	577496061	2828	0	0
out_iso_rd_A	577496061	2151	0	0
phy_config_rd_A	577496061	1143	0	0
phy_pins_drive_rd_A	577496061	1603	0	0
rxenable_setup_rd_A	577496061	1999	0	0
set_nak_out_rd_A	577496061	2038	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577496061	12285	0	0
T249	5406	1003	0	0
T250	4282	10	0	0
T251	5188	228	0	0
T268	3881	502	0	0
T276	45171	6	0	0
T277	41931	3	0	0
T278	13632	859	0	0
T284	3667	11	0	0
T285	9795	28	0	0
T289	4469	23	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577496061	1928	0	0
T263	4993	13	0	0
T272	9555	43	0	0
T278	13632	2	0	0
T285	9795	6	0	0
T291	39391	537	0	0
T306	3022	44	0	0
T312	4585	10	0	0
T313	9216	60	0	0
T322	47980	218	0	0
T323	9891	56	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577496061	1879	0	0
T263	4993	12	0	0
T272	9555	66	0	0
T285	9795	102	0	0
T291	39391	417	0	0
T306	3022	43	0	0
T312	4585	30	0	0
T313	9216	24	0	0
T322	47980	209	0	0
T323	9891	38	0	0
T324	3547	5	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577496061	1652	0	0
T263	4993	6	0	0
T272	9555	43	0	0
T285	9795	16	0	0
T291	39391	506	0	0
T306	3022	41	0	0
T313	9216	31	0	0
T322	47980	196	0	0
T323	9891	40	0	0
T325	11914	97	0	0
T326	3394	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577496061	2828	0	0
T258	3104	5	0	0
T263	4993	8	0	0
T272	9555	51	0	0
T285	9795	157	0	0
T291	39391	770	0	0
T312	4585	7	0	0
T313	9216	28	0	0
T322	47980	230	0	0
T323	9891	20	0	0
T327	2110	7	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577496061	2151	0	0
T263	4993	13	0	0
T272	9555	57	0	0
T285	9795	88	0	0
T291	39391	603	0	0
T306	3022	49	0	0
T312	4585	18	0	0
T313	9216	25	0	0
T322	47980	239	0	0
T323	9891	91	0	0
T325	11914	40	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577496061	1143	0	0
T263	4993	8	0	0
T272	9555	62	0	0
T285	9795	42	0	0
T291	39391	272	0	0
T306	3022	11	0	0
T312	4585	6	0	0
T313	9216	47	0	0
T322	47980	172	0	0
T323	9891	10	0	0
T325	11914	31	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577496061	1603	0	0
T272	9555	31	0	0
T285	9795	72	0	0
T291	39391	358	0	0
T306	3022	30	0	0
T312	4585	23	0	0
T313	9216	66	0	0
T322	47980	204	0	0
T323	9891	25	0	0
T324	3547	3	0	0
T325	11914	20	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577496061	1999	0	0
T263	4993	9	0	0
T272	9555	39	0	0
T285	9795	118	0	0
T291	39391	417	0	0
T306	3022	3	0	0
T312	4585	36	0	0
T313	9216	44	0	0
T322	47980	221	0	0
T323	9891	54	0	0
T324	3547	2	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577496061	2038	0	0
T263	4993	1	0	0
T272	9555	56	0	0
T285	9795	65	0	0
T291	39391	598	0	0
T313	9216	20	0	0
T322	47980	199	0	0
T323	9891	82	0	0
T325	11914	86	0	0
T326	3394	30	0	0
T328	14236	28	0	0