Line Coverage for Module :
usb_fs_rx
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 204 | 204 | 100.00 |
| CONT_ASSIGN | 73 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 75 | 1 | 1 | 100.00 |
| ALWAYS | 125 | 5 | 5 | 100.00 |
| ALWAYS | 135 | 11 | 11 | 100.00 |
| ALWAYS | 154 | 5 | 5 | 100.00 |
| ALWAYS | 172 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 224 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 225 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 245 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 246 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
| ALWAYS | 252 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 290 | 1 | 1 | 100.00 |
| ALWAYS | 294 | 3 | 3 | 100.00 |
| ALWAYS | 302 | 9 | 9 | 100.00 |
| CONT_ASSIGN | 325 | 1 | 1 | 100.00 |
| ALWAYS | 329 | 8 | 8 | 100.00 |
| CONT_ASSIGN | 346 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 347 | 1 | 1 | 100.00 |
| ALWAYS | 350 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 358 | 1 | 1 | 100.00 |
| ALWAYS | 373 | 12 | 12 | 100.00 |
| ALWAYS | 399 | 5 | 5 | 100.00 |
| ALWAYS | 409 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 421 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 427 | 1 | 1 | 100.00 |
| ALWAYS | 431 | 5 | 5 | 100.00 |
| ALWAYS | 440 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 447 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 460 | 1 | 1 | 100.00 |
| ALWAYS | 463 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 477 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 478 | 1 | 1 | 100.00 |
| ALWAYS | 481 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 499 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 500 | 1 | 1 | 100.00 |
| ALWAYS | 503 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 521 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 522 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 523 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 525 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 528 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 530 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 536 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 540 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 545 | 1 | 1 | 100.00 |
| ALWAYS | 552 | 5 | 5 | 100.00 |
| ALWAYS | 565 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 576 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 577 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 578 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 579 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 581 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 582 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 591 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 592 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 593 | 1 | 1 | 100.00 |
| ALWAYS | 596 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 613 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 614 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 615 | 1 | 1 | 100.00 |
| ALWAYS | 618 | 8 | 8 | 100.00 |
| ALWAYS | 635 | 32 | 32 | 100.00 |
72 logic usb_dp_flipped, usb_dn_flipped, usb_d_flipped;
73 1/1 assign usb_dp_flipped = cfg_pinflip_i ? usb_dn_i : usb_dp_i;
Tests: T1 T2 T3
74 1/1 assign usb_dn_flipped = cfg_pinflip_i ? usb_dp_i : usb_dn_i;
Tests: T1 T2 T3
75 1/1 assign usb_d_flipped = usb_d_i ^ cfg_pinflip_i;
Tests: T1 T2 T3
76
77 ///////////////////////////////////////
78 // line state recovery state machine //
79 ///////////////////////////////////////
80
81 // If the receive path is set NOT to use an external differential receiver:
82 // This block samples data purely from the usb_dp_i/usb_dn_i pair.
83 // There is a chance that one of the signals in the pair will appear to have
84 // changed to the new state while the other is still in the old state. The
85 // following state machine detects transitions and waits an extra sampling clock
86 // before decoding the state on the dp/dn pair. This transition period will
87 // only ever last for one clock as long as there is no noise on the line.
88 // If there is enough noise on the line then the data may be corrupted and the
89 // packet will fail the data integrity checks.
90
91 // If the receive path uses an external differential receiver:
92 // This block uses the usb_d_i input to detect K and J symbols.
93 // The individual signals of the differential pair must still be connected
94 // to this block to detect SE0.
95 // Note that the spec warns in section 7.1.4.1:
96 // Both D+ and D- may temporarily be less than VIH (min) during differential
97 // signal transitions. This period can be up to 14 ns (TFST) for full-speed
98 // transitions and up to 210 ns (TLST) for low-speed transitions. Logic in the
99 // receiver must ensure that this is not interpreted as an SE0.
100 // Since the 48MHz sample clock is 20.833ns period we will either miss this or
101 // sample it only once, so it will be covered by line_state=DT and the next
102 // sample will not be SE0 unless this was a real SE0 transition
103 // Note: if it is a real SE0 the usb_d_i input could be doing anything.
104
105 logic [2:0] line_state_qq, line_state_q, line_state_d;
106 logic [2:0] diff_state_q, diff_state_d;
107 logic [2:0] line_state_rx;
108 logic use_se;
109
110 localparam logic [2:0] DT = 3'b100; // transition state
111 localparam logic [2:0] DJ = 3'b010; // J - idle line state
112 localparam logic [2:0] DK = 3'b001; // K - inverse of J
113 localparam logic [2:0] SE0 = 3'b000; // single-ended 0 - end of packet or detached
114 // localparam logic [2:0] SE1 = 3'b011; // single-ended 1 - illegal
115
116 // Mute the input if we're transmitting
117 // dpair is the usb_dp_i/usb_dn_i pair, used in both modes. With
118 // an external differential receiver, it is only used for detecting SE0 and
119 // transitions. Without an external differential receiver driving the
120 // usb_d_i input, it is used for all symbols.
121 // ddiff is the decoded data input from an external differential receiver,
122 // if available, and it is only for K and J symbols, plus transition detection.
123 logic [1:0] dpair, ddiff;
124 always_comb begin : proc_dpair_mute
125 1/1 if (tx_en_i) begin
Tests: T1 T2 T3
126 1/1 dpair = DJ[1:0]; // J
Tests: T1 T28 T29
127 1/1 ddiff = DJ[1:0]; // J
Tests: T1 T28 T29
128 end else begin
129 1/1 dpair = {usb_dp_flipped, usb_dn_flipped};
Tests: T1 T2 T3
130 1/1 ddiff = usb_d_flipped ? DJ[1:0] : DK[1:0]; // equiv to {usb_d_i, ~usb_d_i}
Tests: T1 T2 T3
131 end
132 end
133
134 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_line_state_q
135 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
136 1/1 line_state_q <= SE0;
Tests: T1 T2 T3
137 1/1 line_state_qq <= SE0;
Tests: T1 T2 T3
138 1/1 diff_state_q <= SE0;
Tests: T1 T2 T3
139 end else begin
140 1/1 if (link_reset_i) begin
Tests: T1 T2 T3
141 1/1 line_state_q <= SE0;
Tests: T1 T2 T3
142 1/1 line_state_qq <= SE0;
Tests: T1 T2 T3
143 1/1 diff_state_q <= SE0;
Tests: T1 T2 T3
144 end else begin
145 1/1 line_state_q <= line_state_d;
Tests: T1 T2 T3
146 1/1 line_state_qq <= line_state_q;
Tests: T1 T2 T3
147 1/1 diff_state_q <= diff_state_d;
Tests: T1 T2 T3
148 end
149 end
150 end
151
152 always_comb begin : proc_line_state_d
153 // Default assignment
154 1/1 line_state_d = line_state_q;
Tests: T1 T2 T3
155
156 1/1 if (line_state_q == DT) begin
Tests: T1 T2 T3
157 // if we are in a transition state, then we can sample the pair and
158 // move to the next corresponding line state
159 1/1 line_state_d = {1'b0, dpair};
Tests: T1 T2 T3
160
161 end else begin
162 // if we are in a valid line state and the value of the pair changes,
163 // then we need to move to the transition state
164 1/1 if (dpair != line_state_q[1:0]) begin
Tests: T1 T2 T3
165 1/1 line_state_d = DT;
Tests: T1 T2 T3
166 end
MISSING_ELSE
167 end
168 end
169
170 always_comb begin : proc_diff_state_d
171 // Default assignment
172 1/1 diff_state_d = diff_state_q;
Tests: T1 T2 T3
173
174 1/1 if (diff_state_q == DT) begin
Tests: T1 T2 T3
175 // if we are in a transition state, then we can sample the diff input and
176 // move to the next corresponding line state
177 1/1 diff_state_d = {1'b0, ddiff};
Tests: T1 T2 T3
178
179 end else begin
180 // if we are in a valid line state and the value of the diff input changes,
181 // then we need to move to the transition state
182 1/1 if (ddiff != diff_state_q[1:0]) begin
Tests: T1 T2 T3
183 1/1 diff_state_d = DT;
Tests: T1 T2 T3
184 end
MISSING_ELSE
185 end
186 end
187
188 // The received line state depends on how the receiver is configured:
189 // NOT using a differential receiver: it is just the line_state_q that was captured
190 //
191 // Using a differential receiver: recovered from the differential receiver (diff_state_q)
192 // unless the diff pair indicate SE0 when the differential
193 // receiver could produce any value
194 //
195 // Transition where the dp/dn pair happen to see SE0 will look like (driven by diff DT)
196 // line_state D? DT D?...
197 // diff_state Dx DT Dy (expect Dy to be inverse of Dx since diff changed)
198 //
199 // Transition to SE0 when usb_d_i changes will look like:
200 // line_state DT D? D? D? DT SE0 SE0... (DT is the first sample at SE0)
201 // diff_state DT Dx Dx Dx DT ?? ??... (diff saw transition as line went SE0)
202 // --> out DT Dx Dx Dx DT SE0 SE0 (if no transition then DT would be Dx and n=3)
203 // bit_phase n 0 1 2 3 0 1 (n=3 unless there was a clock resync)
204 //
205 // Transition to SE0 when usb_d_i does not change will look like:
206 // line_state DT D? D? D? DT SE0 SE0... (DT is the first sample at SE0)
207 // diff_state DT Dx Dx Dx Dx ?? ??... (diff no transition as line went SE0)
208 // --> out DT Dx Dx Dx Dx SE0 SE0 (if no transition then DT would be Dx and n=3)
209 // bit_phase n 0 1 2 3 0 1 (n=3 unless there was a clock resync)
210 //
211 // Transition to SE0 when usb_d_i does not change and clock resync earlier:
212 // line_state DT D? D? DT SE0 SE0 SE0... (DT is the first sample at SE0, should resync clock)
213 // diff_state DT Dx Dx Dx Dx ?? ??... (diff no transition as line went SE0)
214 // --> out DT Dx Dx Dx SE0 SE0 SE0 (if no transition then DT would be Dx and n=3)
215 // bit_phase n 0 1 2 3 0 1 (n=3 unless there was a clock resync)
216 //
217 // On transition back from SE0 want to generate a DT to resync the clock
218 // since SE0 could have gone on a while no idea what bit_phase is
219 // line_state SE0 SE0 DT D? D? D?
220 // diff_state ?? ?? ?? Dx Dx Dx
221 // --> out SE0 SE0 DT Dx Dx Dx
222 // bit_phase ? ? ? 0 1 2
223
224 1/1 assign use_se = (line_state_q == SE0) || ((line_state_q == DT) && (line_state_qq == SE0));
Tests: T1 T2 T3
225 1/1 assign line_state_rx = cfg_use_diff_rcvr_i ? (use_se ? line_state_q : diff_state_q) :
Tests: T1 T2 T3
226 line_state_q;
227
228 ////////////////////
229 // clock recovery //
230 ////////////////////
231
232 // the DT state from the line state recovery state machine is used to align to
233 // transmit clock. the line state is sampled in the middle of the bit time.
234
235 // example of signal relationships
236 // -------------------------------
237 // line_state DT DJ DJ DJ DT DK DK DK DK DK DK DT DJ DJ DJ
238 // line_state_valid ________----____________----____________----________----____
239 // bit_phase 0 0 1 2 3 0 1 2 3 0 1 2 0 1 2
240
241
242 logic [1:0] bit_phase_q, bit_phase_d;
243 logic line_state_valid;
244
245 1/1 assign line_state_valid = (bit_phase_q == 2'd1);
Tests: T1 T2 T3
246 1/1 assign bit_strobe_o = (bit_phase_q == 2'd2);
Tests: T1 T2 T3
247
248 // keep track of phase within each bit
249 1/1 assign bit_phase_d = (line_state_rx == DT) ? 0 : bit_phase_q + 1;
Tests: T1 T2 T3
250
251 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_bit_phase_q
252 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
253 1/1 bit_phase_q <= 0;
Tests: T1 T2 T3
254 end else begin
255 1/1 if (link_reset_i) begin
Tests: T1 T2 T3
256 1/1 bit_phase_q <= 0;
Tests: T1 T2 T3
257 end else begin
258 1/1 bit_phase_q <= bit_phase_d;
Tests: T1 T2 T3
259 end
260 end
261 end
262
263
264 //////////////////////
265 // packet detection //
266 //////////////////////
267
268 // usb uses a sync to denote the beginning of a packet's PID and two
269 // single-ended-0 to denote the end of a packet. this state machine
270 // recognizes the beginning and end of packets for subsequent layers to
271 // process.
272
273 logic [11:0] line_history_q, line_history_d;
274 logic packet_valid_q, packet_valid_d;
275 logic see_sop, see_eop, see_preamble, packet_start, packet_end;
276 logic in_packet_d, in_packet_q;
277
278 // A bit of a misnomer: packet_start pulses when the PID begins, not SOP.
279 1/1 assign packet_start = packet_valid_d & ~packet_valid_q;
Tests: T1 T2 T3
280 1/1 assign packet_end = ~packet_valid_d & packet_valid_q;
Tests: T1 T2 T3
281
282 // EOP detection is configurable for 1/2 bit periods of SE0.
283 // The standard (Table 7-7) mandates min = 82 ns = 1 bit period.
284 // We also trigger an EOP on seeing a bitstuff error or a PRE PID.
285 1/1 assign see_eop = (cfg_eop_single_bit_i && line_history_q[1:0] == 2'b00)
Tests: T1 T2 T3
286 || (line_history_q[3:0] == 4'b0000) || bitstuff_error_q || see_preamble;
287
288 // SOP is the transition from idle (J) to K
289 1/1 assign see_sop = (line_history_q[3:0] == 4'b1001) & ~tx_en_i & ~in_packet_q;
Tests: T1 T2 T3
290 1/1 assign in_packet_d = see_eop ? 1'b0 :
Tests: T1 T2 T3
291 see_sop ? 1'b1 : in_packet_q;
292
293 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_reg_in_packet
294 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
295 1/1 in_packet_q <= 1'b0;
Tests: T1 T2 T3
296 end else begin
297 1/1 in_packet_q <= in_packet_d;
Tests: T1 T2 T3
298 end
299 end
300
301 always_comb begin : proc_packet_valid_d
302 1/1 if (line_state_valid) begin
Tests: T1 T2 T3
303 // If the differential K and J symbols are not valid, reject the
304 // containing packet as invalid.
305 1/1 if (~diff_rx_ok_i) begin
Tests: T1 T2 T3
306 1/1 packet_valid_d = 0;
Tests: T7 T22 T8
307 // check for packet start: KJKJKK, we use the last 6 bits
308 1/1 end else if (!packet_valid_q && line_history_q[11:0] == 12'b011001100101) begin
Tests: T1 T2 T3
309 1/1 packet_valid_d = 1;
Tests: T1 T3 T28
310 end
311
312 // check for packet end: SE0 SE0
313 1/1 else if (packet_valid_q && see_eop) begin
Tests: T1 T2 T3
314 1/1 packet_valid_d = 0;
Tests: T1 T3 T28
315
316 end else begin
317 1/1 packet_valid_d = packet_valid_q;
Tests: T1 T2 T3
318 end
319 end else begin
320 1/1 packet_valid_d = packet_valid_q;
Tests: T1 T2 T3
321 end
322 end
323
324 // keep a history of the last two states on the line
325 1/1 assign line_history_d = line_state_valid ? {line_history_q[9:0], line_state_rx[1:0]} :
Tests: T1 T2 T3
326 line_history_q;
327
328 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_reg_pkt_line
329 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
330 1/1 packet_valid_q <= 0;
Tests: T1 T2 T3
331 1/1 line_history_q <= 12'b101010101010; // all K
Tests: T1 T2 T3
332 end else begin
333 1/1 if (link_reset_i) begin
Tests: T1 T2 T3
334 1/1 packet_valid_q <= 0;
Tests: T1 T2 T3
335 1/1 line_history_q <= 12'b101010101010; // all K
Tests: T1 T2 T3
336 end else begin
337 1/1 packet_valid_q <= packet_valid_d;
Tests: T1 T2 T3
338 1/1 line_history_q <= line_history_d;
Tests: T1 T2 T3
339 end
340 end
341 end
342
343 // mask out idle detection when transmitting (because rx may be forced to
344 // J and look like an idle symbol)
345 logic rx_idle_det_d, rx_idle_det_q;
346 1/1 assign rx_idle_det_d = (~tx_en_i & line_state_valid) ? (line_state_q == DJ) : rx_idle_det_q;
Tests: T1 T2 T3
347 1/1 assign rx_idle_det_o = rx_idle_det_q;
Tests: T1 T2 T3
348
349 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_reg_idle_det
350 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
351 1/1 rx_idle_det_q <= 1'b0;
Tests: T1 T2 T3
352 end else begin
353 1/1 rx_idle_det_q <= rx_idle_det_d;
Tests: T1 T2 T3
354 end
355 end
356
357 // Used for seeing a J after the completion of resume signaling
358 1/1 assign rx_j_det_o = diff_rx_ok_i & ~tx_en_i & (line_history_q[1:0] == 2'b10);
Tests: T1 T2 T3
359
360 /////////////////
361 // NRZI decode //
362 /////////////////
363
364 // in order to ensure there are enough bit transitions for a receiver to recover
365 // the clock usb uses NRZI encoding.
366
367 // https://en.wikipedia.org/wiki/Non-return-to-zero
368
369 logic dvalid_raw;
370 logic din;
371
372 always_comb begin
373 1/1 unique case (line_history_q[3:0])
Tests: T1 T2 T3
374 1/1 4'b0101 : din = 1;
Tests: T1 T3 T28
375 1/1 4'b0110 : din = 0;
Tests: T1 T3 T28
376 1/1 4'b1001 : din = 0;
Tests: T1 T3 T28
377 1/1 4'b1010 : din = 1;
Tests: T1 T2 T3
378 default : din = 0;
379 endcase
380
381 1/1 if (packet_valid_q && line_state_valid) begin
Tests: T1 T2 T3
382 1/1 unique case (line_history_q[3:0])
Tests: T1 T3 T28
383 1/1 4'b0101 : dvalid_raw = 1;
Tests: T1 T3 T28
384 1/1 4'b0110 : dvalid_raw = 1;
Tests: T1 T3 T28
385 1/1 4'b1001 : dvalid_raw = 1;
Tests: T1 T3 T28
386 1/1 4'b1010 : dvalid_raw = 1;
Tests: T1 T3 T28
387 default : dvalid_raw = 0;
388 endcase
389 end else begin
390 1/1 dvalid_raw = 0;
Tests: T1 T2 T3
391 end
392 end
393
394 //////////////////////////////////////////////////////
395 // Undo bit stuffing and detect bit stuffing errors //
396 //////////////////////////////////////////////////////
397
398 always_comb begin : proc_bitstuff_history_d
399 1/1 if (packet_end) begin
Tests: T1 T2 T3
400 1/1 bitstuff_history_d = '0;
Tests: T1 T3 T28
401 1/1 end else if (dvalid_raw) begin
Tests: T1 T2 T3
402 1/1 bitstuff_history_d = {bitstuff_history_q[5:0], din};
Tests: T1 T3 T28
403 end else begin
404 1/1 bitstuff_history_d = bitstuff_history_q;
Tests: T1 T2 T3
405 end
406 end
407
408 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_bitstuff_history_q
409 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
410 1/1 bitstuff_history_q <= 0;
Tests: T1 T2 T3
411 end else begin
412 1/1 if (link_reset_i) begin
Tests: T1 T2 T3
413 1/1 bitstuff_history_q <= 0;
Tests: T1 T2 T3
414 end else begin
415 1/1 bitstuff_history_q <= bitstuff_history_d;
Tests: T1 T2 T3
416 end
417 end
418 end
419
420 logic dvalid;
421 1/1 assign dvalid = dvalid_raw && !(bitstuff_history_q[5:0] == 6'b111111);
Tests: T1 T2 T3
422
423 // 7 consecutive ones should not be seen on the bus
424 // USB spec, 7.1.9.1: "If the receiver sees seven
425 // consecutive ones anywhere in the packet, then a bit stuffing error
426 // has occurred and the packet should be ignored."
427 1/1 assign bitstuff_error = bitstuff_history_q == 7'b1111111;
Tests: T1 T2 T3
428
429 // remember the bitstuff errors
430 always_comb begin : proc_bistuff_error_d
431 1/1 bitstuff_error_d = bitstuff_error_q;
Tests: T1 T2 T3
432 1/1 if (packet_start) begin
Tests: T1 T2 T3
433 1/1 bitstuff_error_d = 0;
Tests: T1 T3 T28
434 1/1 end else if (bitstuff_error && dvalid_raw) begin
Tests: T1 T2 T3
435 1/1 bitstuff_error_d = 1;
Tests: T3 T84 T79
436 end
MISSING_ELSE
437 end
438
439 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_bitstuff_error_q
440 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
441 1/1 bitstuff_error_q <= 0;
Tests: T1 T2 T3
442 end else begin
443 1/1 bitstuff_error_q <= bitstuff_error_d;
Tests: T1 T2 T3
444 end
445 end
446
447 1/1 assign bitstuff_error_o = bitstuff_error_q && packet_end;
Tests: T1 T2 T3
448
449
450 ////////////////////////
451 // save and check pid //
452 ////////////////////////
453
454 // shift in the entire 8-bit pid with an additional 9th bit used as a sentinel.
455
456 logic [8:0] full_pid_q, full_pid_d;
457 logic pid_valid, pid_complete;
458
459 1/1 assign pid_valid = full_pid_q[4:1] == ~full_pid_q[8:5];
Tests: T1 T2 T3
460 1/1 assign pid_complete = full_pid_q[0];
Tests: T1 T2 T3
461
462 always_comb begin : proc_full_pid_d
463 1/1 if (dvalid && !pid_complete) begin
Tests: T1 T2 T3
464 1/1 full_pid_d = {din, full_pid_q[8:1]};
Tests: T1 T3 T28
465 1/1 end else if (packet_start) begin
Tests: T1 T2 T3
466 1/1 full_pid_d = 9'b100000000;
Tests: T1 T3 T28
467 end else begin
468 1/1 full_pid_d = full_pid_q;
Tests: T1 T2 T3
469 end
470 end
471
472 ////////////////
473 // check crc5 //
474 ////////////////
475 logic [4:0] crc5_q, crc5_d;
476 logic crc5_valid, crc5_invert;
477 1/1 assign crc5_valid = crc5_q == 5'b01100;
Tests: T1 T2 T3
478 1/1 assign crc5_invert = din ^ crc5_q[4];
Tests: T1 T2 T3
479
480 always_comb begin
481 1/1 crc5_d = crc5_q; // default value
Tests: T1 T2 T3
482
483 1/1 if (packet_start) begin
Tests: T1 T2 T3
484 1/1 crc5_d = 5'b11111;
Tests: T1 T3 T28
485 end
MISSING_ELSE
486
487 1/1 if (dvalid && pid_complete) begin
Tests: T1 T2 T3
488 1/1 crc5_d = {crc5_q[3:0], 1'b0} ^ ({5{crc5_invert}} & 5'b00101);
Tests: T1 T3 T28
489 end
MISSING_ELSE
490 end
491
492
493 /////////////////
494 // check crc16 //
495 /////////////////
496 logic [15:0] crc16_q, crc16_d;
497 logic crc16_valid, crc16_invert;
498
499 1/1 assign crc16_valid = crc16_q == 16'b1000000000001101;
Tests: T1 T2 T3
500 1/1 assign crc16_invert = din ^ crc16_q[15];
Tests: T1 T2 T3
501
502 always_comb begin
503 1/1 crc16_d = crc16_q; // default value
Tests: T1 T2 T3
504
505 1/1 if (packet_start) begin
Tests: T1 T2 T3
506 1/1 crc16_d = 16'b1111111111111111;
Tests: T1 T3 T28
507 end
MISSING_ELSE
508
509 1/1 if (dvalid && pid_complete) begin
Tests: T1 T2 T3
510 1/1 crc16_d = {crc16_q[14:0], 1'b0} ^ ({16{crc16_invert}} & 16'b1000000000000101);
Tests: T1 T3 T28
511 end
MISSING_ELSE
512 end
513
514
515 ////////////////////////////
516 // output control signals //
517 ////////////////////////////
518 logic valid_token_len, valid_data_len, valid_handshake_len;
519
520 logic pkt_is_token, pkt_is_data, pkt_is_handshake;
521 1/1 assign pkt_is_token = full_pid_q[2:1] == 2'b01;
Tests: T1 T2 T3
522 1/1 assign pkt_is_data = full_pid_q[2:1] == 2'b11;
Tests: T1 T2 T3
523 1/1 assign pkt_is_handshake = full_pid_q[2:1] == 2'b10;
Tests: T1 T2 T3
524
525 1/1 assign see_preamble = packet_valid_q & pid_valid & pid_complete &&
Tests: T1 T2 T3
526 (usb_pid_e'(full_pid_q[4:1]) == UsbPidPre);
527
528 1/1 assign valid_pid_o = pid_valid;
Tests: T1 T2 T3
529
530 1/1 assign valid_packet_o = pid_valid && !bitstuff_error_q &&
Tests: T1 T2 T3
531 ((pkt_is_handshake && valid_handshake_len) ||
532 (pkt_is_data && valid_data_len && crc16_valid) ||
533 (pkt_is_token && valid_token_len && crc5_valid));
534
535 // Detect CRC errors
536 1/1 assign crc5_error_o = pkt_is_token & packet_end & !crc5_valid;
Tests: T1 T2 T3
537 1/1 assign crc16_error_o = pkt_is_data & packet_end & !crc16_valid;
Tests: T1 T2 T3
538
539 // Detect PID errors
540 1/1 assign pid_error_o = !pid_valid && packet_end;
Tests: T1 T2 T3
541
542 logic [11:0] token_payload_q, token_payload_d;
543 logic token_payload_done;
544
545 1/1 assign token_payload_done = token_payload_q[0];
Tests: T1 T2 T3
546
547 logic [6:0] addr_q, addr_d;
548 logic [3:0] endp_q, endp_d;
549 logic [10:0] frame_num_q, frame_num_d;
550
551 always_comb begin
552 1/1 token_payload_d = token_payload_q; // default
Tests: T1 T2 T3
553
554 1/1 if (packet_start) begin
Tests: T1 T2 T3
555 1/1 token_payload_d = 12'b100000000000;
Tests: T1 T3 T28
556 end
MISSING_ELSE
557
558 1/1 if (dvalid && pid_complete && pkt_is_token && !token_payload_done) begin
Tests: T1 T2 T3
559 1/1 token_payload_d = {din, token_payload_q[11:1]};
Tests: T1 T3 T28
560 end
MISSING_ELSE
561 end
562
563 always_comb begin
564 // defaults
565 1/1 addr_d = addr_q;
Tests: T1 T2 T3
566 1/1 endp_d = endp_q;
Tests: T1 T2 T3
567 1/1 frame_num_d = frame_num_q;
Tests: T1 T2 T3
568
569 1/1 if (token_payload_done && pkt_is_token) begin
Tests: T1 T2 T3
570 1/1 addr_d = token_payload_q[7:1];
Tests: T1 T3 T28
571 1/1 endp_d = token_payload_q[11:8];
Tests: T1 T3 T28
572 1/1 frame_num_d = token_payload_q[11:1];
Tests: T1 T3 T28
573 end
MISSING_ELSE
574 end
575
576 1/1 assign addr_o = addr_q;
Tests: T1 T2 T3
577 1/1 assign endp_o = endp_q;
Tests: T1 T2 T3
578 1/1 assign frame_num_o = frame_num_q;
Tests: T1 T2 T3
579 1/1 assign pid_o = full_pid_q[4:1];
Tests: T1 T2 T3
580
581 1/1 assign pkt_start_o = see_sop;
Tests: T1 T2 T3
582 1/1 assign pkt_end_o = packet_end;
Tests: T1 T2 T3
583
584
585 /////////////////////////////////
586 // deserialize and output data //
587 /////////////////////////////////
588 logic [8:0] rx_data_buffer_q, rx_data_buffer_d;
589 logic rx_data_buffer_full;
590
591 1/1 assign rx_data_buffer_full = rx_data_buffer_q[0];
Tests: T1 T2 T3
592 1/1 assign rx_data_put_o = rx_data_buffer_full;
Tests: T1 T2 T3
593 1/1 assign rx_data_o = rx_data_buffer_q[8:1];
Tests: T1 T2 T3
594
595 always_comb begin
596 1/1 rx_data_buffer_d = rx_data_buffer_q; // default
Tests: T1 T2 T3
597
598 1/1 if (packet_start || rx_data_buffer_full) begin
Tests: T1 T2 T3
599 1/1 rx_data_buffer_d = 9'b100000000;
Tests: T1 T3 T28
600 end
MISSING_ELSE
601
602 1/1 if (dvalid && pid_complete && pkt_is_data) begin
Tests: T1 T2 T3
603 1/1 rx_data_buffer_d = {din, rx_data_buffer_q[8:1]};
Tests: T1 T3 T28
604 end
MISSING_ELSE
605 end
606
607 // Counting packet length in bits; we need to know whether the length is byte-aligned,
608 // and whether it's equal to 16 (token packet) or at least 16 (data packet; CRC16 required).
609 logic rx_data_len16_q, rx_data_len16_d;
610 logic [3:0] rx_data_len_q, rx_data_len_d;
611
612 // Valid packet length indications.
613 1/1 assign valid_token_len = rx_data_len16_q & ~|rx_data_len_q;
Tests: T1 T2 T3
614 1/1 assign valid_data_len = rx_data_len16_q & ~|rx_data_len_q[2:0]; // Must be byte-aligned.
Tests: T1 T2 T3
615 1/1 assign valid_handshake_len = ~|{rx_data_len16_q, rx_data_len_q};
Tests: T1 T2 T3
616
617 always_comb begin
618 1/1 rx_data_len16_d = rx_data_len16_q;
Tests: T1 T2 T3
619 1/1 rx_data_len_d = rx_data_len_q;
Tests: T1 T2 T3
620
621 1/1 if (packet_start) begin
Tests: T1 T2 T3
622 1/1 rx_data_len16_d = 1'b0;
Tests: T1 T3 T28
623 1/1 rx_data_len_d = 4'h0;
Tests: T1 T3 T28
624 end
MISSING_ELSE
625 1/1 if (dvalid && pid_complete) begin
Tests: T1 T2 T3
626 1/1 rx_data_len16_d = rx_data_len16_q | &rx_data_len_q;
Tests: T1 T3 T28
627 1/1 rx_data_len_d = rx_data_len_q + 4'h1;
Tests: T1 T3 T28
628 end
MISSING_ELSE
629 end
630
631 ///////////////
632 // Registers //
633 ///////////////
634 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_gp_regs
635 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
636 1/1 full_pid_q <= 0;
Tests: T1 T2 T3
637 1/1 crc16_q <= 0;
Tests: T1 T2 T3
638 1/1 crc5_q <= 0;
Tests: T1 T2 T3
639 1/1 token_payload_q <= 0;
Tests: T1 T2 T3
640 1/1 addr_q <= 0;
Tests: T1 T2 T3
641 1/1 endp_q <= 0;
Tests: T1 T2 T3
642 1/1 frame_num_q <= 0;
Tests: T1 T2 T3
643 1/1 rx_data_buffer_q <= 0;
Tests: T1 T2 T3
644 1/1 rx_data_len16_q <= 0;
Tests: T1 T2 T3
645 1/1 rx_data_len_q <= 0;
Tests: T1 T2 T3
646 end else begin
647 1/1 if (link_reset_i) begin
Tests: T1 T2 T3
648 1/1 full_pid_q <= 0;
Tests: T1 T2 T3
649 1/1 crc16_q <= 0;
Tests: T1 T2 T3
650 1/1 crc5_q <= 0;
Tests: T1 T2 T3
651 1/1 token_payload_q <= 0;
Tests: T1 T2 T3
652 1/1 addr_q <= 0;
Tests: T1 T2 T3
653 1/1 endp_q <= 0;
Tests: T1 T2 T3
654 1/1 frame_num_q <= 0;
Tests: T1 T2 T3
655 1/1 rx_data_buffer_q <= 0;
Tests: T1 T2 T3
656 1/1 rx_data_len16_q <= 0;
Tests: T1 T2 T3
657 1/1 rx_data_len_q <= 0;
Tests: T1 T2 T3
658 end else begin
659 1/1 full_pid_q <= full_pid_d;
Tests: T1 T2 T3
660 1/1 crc16_q <= crc16_d;
Tests: T1 T2 T3
661 1/1 crc5_q <= crc5_d;
Tests: T1 T2 T3
662 1/1 token_payload_q <= token_payload_d;
Tests: T1 T2 T3
663 1/1 addr_q <= addr_d;
Tests: T1 T2 T3
664 1/1 endp_q <= endp_d;
Tests: T1 T2 T3
665 1/1 frame_num_q <= frame_num_d;
Tests: T1 T2 T3
666 1/1 rx_data_buffer_q <= rx_data_buffer_d;
Tests: T1 T2 T3
667 1/1 rx_data_len16_q <= rx_data_len16_d;
Tests: T1 T2 T3
668 1/1 rx_data_len_q <= rx_data_len_d;
Tests: T1 T2 T3
Cond Coverage for Module :
usb_fs_rx
| Total | Covered | Percent |
|---|
| Conditions | 206 | 202 | 98.06 |
| Logical | 206 | 202 | 98.06 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 73
EXPRESSION (cfg_pinflip_i ? usb_dn_i : usb_dp_i)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T49,T50 |
LINE 74
EXPRESSION (cfg_pinflip_i ? usb_dp_i : usb_dn_i)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T49,T50 |
LINE 75
EXPRESSION (usb_d_i ^ cfg_pinflip_i)
---1--- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T7,T49,T50 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T7,T49,T274 |
LINE 130
EXPRESSION (usb_d_flipped ? DJ[1:0] : DK[1:0])
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION (line_state_q == DT)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (dpair != line_state_q[1:0])
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 174
EXPRESSION (diff_state_q == DT)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 182
EXPRESSION (ddiff != diff_state_q[1:0])
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 224
EXPRESSION ((line_state_q == SE0) || ((line_state_q == DT) && (line_state_qq == SE0)))
----------1---------- ------------------------2-----------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 224
SUB-EXPRESSION (line_state_q == SE0)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 224
SUB-EXPRESSION ((line_state_q == DT) && (line_state_qq == SE0))
----------1--------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 224
SUB-EXPRESSION (line_state_q == DT)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 224
SUB-EXPRESSION (line_state_qq == SE0)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 225
EXPRESSION (cfg_use_diff_rcvr_i ? (use_se ? line_state_q : diff_state_q) : line_state_q)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 225
SUB-EXPRESSION (use_se ? line_state_q : diff_state_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 245
EXPRESSION (bit_phase_q == 2'b1)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 246
EXPRESSION (bit_phase_q == 2'd2)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 249
EXPRESSION ((line_state_rx == DT) ? 0 : ((bit_phase_q + 1)))
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 249
SUB-EXPRESSION (line_state_rx == DT)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 279
EXPRESSION (packet_valid_d & ((~packet_valid_q)))
-------1------ ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 280
EXPRESSION (((~packet_valid_d)) & packet_valid_q)
---------1--------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 285
EXPRESSION ((cfg_eop_single_bit_i && (line_history_q[1:0] == 2'b0)) || (line_history_q[3:0] == 4'b0) || bitstuff_error_q || see_preamble)
---------------------------1--------------------------- --------------2-------------- --------3------- ------4-----
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | Covered | T42,T86,T68 |
| 0 | 0 | 1 | 0 | Covered | T3,T84,T79 |
| 0 | 1 | 0 | 0 | Covered | T1,T2,T3 |
| 1 | 0 | 0 | 0 | Covered | T1,T2,T3 |
LINE 285
SUB-EXPRESSION (cfg_eop_single_bit_i && (line_history_q[1:0] == 2'b0))
----------1--------- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 285
SUB-EXPRESSION (line_history_q[1:0] == 2'b0)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 285
SUB-EXPRESSION (line_history_q[3:0] == 4'b0)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 289
EXPRESSION ((line_history_q[3:0] == 4'b1001) & ((~tx_en_i)) & ((~in_packet_q)))
----------------1--------------- ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | 1 | Covered | T1,T3,T28 |
LINE 289
SUB-EXPRESSION (line_history_q[3:0] == 4'b1001)
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 290
EXPRESSION (see_eop ? 1'b0 : (see_sop ? 1'b1 : in_packet_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 290
SUB-EXPRESSION (see_sop ? 1'b1 : in_packet_q)
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 308
EXPRESSION (((!packet_valid_q)) && (line_history_q[11:0] == 12'b011001100101))
---------1--------- ---------------------2--------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 308
SUB-EXPRESSION (line_history_q[11:0] == 12'b011001100101)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 313
EXPRESSION (packet_valid_q && see_eop)
-------1------ ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 325
EXPRESSION (line_state_valid ? ({line_history_q[9:0], line_state_rx[1:0]}) : line_history_q)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 346
EXPRESSION ((((~tx_en_i)) & line_state_valid) ? (line_state_q == DJ) : rx_idle_det_q)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 346
SUB-EXPRESSION (((~tx_en_i)) & line_state_valid)
------1----- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T28,T29 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 346
SUB-EXPRESSION (line_state_q == DJ)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 358
EXPRESSION (diff_rx_ok_i & ((~tx_en_i)) & (line_history_q[1:0] == 2'b10))
------1----- ------2----- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T28,T29 |
| 1 | 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 358
SUB-EXPRESSION (line_history_q[1:0] == 2'b10)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 381
EXPRESSION (packet_valid_q && line_state_valid)
-------1------ --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 421
EXPRESSION (dvalid_raw && ( ! (bitstuff_history_q[5:0] == 6'b111111) ))
-----1---- ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 421
SUB-EXPRESSION ( ! (bitstuff_history_q[5:0] == 6'b111111) )
-------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 421
SUB-EXPRESSION (bitstuff_history_q[5:0] == 6'b111111)
-------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 427
EXPRESSION (bitstuff_history_q == 7'b1111111)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T84,T79 |
LINE 434
EXPRESSION (bitstuff_error && dvalid_raw)
-------1------ -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T3,T84,T79 |
| 1 | 1 | Covered | T3,T84,T79 |
LINE 447
EXPRESSION (bitstuff_error_q && packet_end)
--------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T3,T84,T79 |
| 1 | 1 | Covered | T3,T84,T79 |
LINE 459
EXPRESSION (full_pid_q[4:1] == (~full_pid_q[8:5]))
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 463
EXPRESSION (dvalid && ((!pid_complete)))
---1-- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 477
EXPRESSION (crc5_q == 5'b01100)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 478
EXPRESSION (din ^ crc5_q[4])
-1- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 487
EXPRESSION (dvalid && pid_complete)
---1-- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 499
EXPRESSION (crc16_q == 16'b1000000000001101)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T28,T29 |
LINE 500
EXPRESSION (din ^ crc16_q[15])
-1- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 509
EXPRESSION (dvalid && pid_complete)
---1-- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 521
EXPRESSION (full_pid_q[2:1] == 2'b1)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 522
EXPRESSION (full_pid_q[2:1] == 2'b11)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 523
EXPRESSION (full_pid_q[2:1] == 2'b10)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 525
EXPRESSION ((packet_valid_q & pid_valid & pid_complete) && (usb_pid_e'(full_pid_q[4:1]) == UsbPidPre))
---------------------1--------------------- ---------------------2--------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T42,T86,T68 |
LINE 525
SUB-EXPRESSION (packet_valid_q & pid_valid & pid_complete)
-------1------ ----2---- ------3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | 1 | Covered | T78,T79,T80 |
| 1 | 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | 1 | Covered | T1,T3,T28 |
LINE 525
SUB-EXPRESSION (usb_pid_e'(full_pid_q[4:1]) == UsbPidPre)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 530
EXPRESSION
Number Term
1 pid_valid &&
2 ((!bitstuff_error_q)) &&
3 ((pkt_is_handshake && valid_handshake_len) || (pkt_is_data && valid_data_len && crc16_valid) || (pkt_is_token && valid_token_len && crc5_valid)))
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | 1 | Covered | T1,T3,T28 |
LINE 530
SUB-EXPRESSION ((pkt_is_handshake && valid_handshake_len) || (pkt_is_data && valid_data_len && crc16_valid) || (pkt_is_token && valid_token_len && crc5_valid))
--------------------1-------------------- -----------------------2---------------------- -----------------------3-----------------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T1,T3,T28 |
| 0 | 1 | 0 | Covered | T1,T28,T29 |
| 1 | 0 | 0 | Covered | T1,T3,T28 |
LINE 530
SUB-EXPRESSION (pkt_is_handshake && valid_handshake_len)
--------1------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T79,T82,T83 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 530
SUB-EXPRESSION (pkt_is_data && valid_data_len && crc16_valid)
-----1----- -------2------ -----3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T5,T107,T275 |
| 1 | 1 | 0 | Covered | T1,T28,T29 |
| 1 | 1 | 1 | Covered | T1,T28,T29 |
LINE 530
SUB-EXPRESSION (pkt_is_token && valid_token_len && crc5_valid)
------1----- -------2------- -----3----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T29,T30,T42 |
| 1 | 0 | 1 | Covered | T3,T29,T42 |
| 1 | 1 | 0 | Covered | T79,T76,T82 |
| 1 | 1 | 1 | Covered | T1,T3,T28 |
LINE 536
EXPRESSION (pkt_is_token & packet_end & ((!crc5_valid)))
------1----- -----2---- -------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | 1 | Covered | T1,T3,T28 |
| 1 | 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | 1 | Covered | T84,T79,T76 |
LINE 537
EXPRESSION (pkt_is_data & packet_end & ((!crc16_valid)))
-----1----- -----2---- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | 1 | Covered | T1,T3,T28 |
| 1 | 1 | 0 | Covered | T1,T28,T29 |
| 1 | 1 | 1 | Covered | T3,T32,T38 |
LINE 540
EXPRESSION (((!pid_valid)) && packet_end)
-------1------ -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T78,T79,T80 |
LINE 558
EXPRESSION (dvalid && pid_complete && pkt_is_token && ((!token_payload_done)))
---1-- ------2----- ------3----- -----------4-----------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | 1 | 1 | Covered | T29,T30,T42 |
| 1 | 1 | 0 | 1 | Covered | T1,T3,T28 |
| 1 | 1 | 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | 1 | 1 | Covered | T1,T3,T28 |
LINE 569
EXPRESSION (token_payload_done && pkt_is_token)
---------1-------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 598
EXPRESSION (packet_start || rx_data_buffer_full)
------1----- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T3,T28 |
LINE 602
EXPRESSION (dvalid && pid_complete && pkt_is_data)
---1-- ------2----- -----3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | 1 | Covered | T1,T3,T28 |
| 1 | 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | 1 | Covered | T1,T3,T28 |
LINE 613
EXPRESSION (rx_data_len16_q & ((~|rx_data_len_q)))
-------1------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T28,T29 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 614
EXPRESSION (rx_data_len16_q & ((~|rx_data_len_q[2:0])))
-------1------- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T28,T29 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 625
EXPRESSION (dvalid && pid_complete)
---1-- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 626
EXPRESSION (rx_data_len16_q | ((&rx_data_len_q)))
-------1------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T3,T28 |
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T28,T29 |
Branch Coverage for Module :
usb_fs_rx
| Line No. | Total | Covered | Percent |
| Branches |
|
93 |
93 |
100.00 |
| TERNARY |
73 |
2 |
2 |
100.00 |
| TERNARY |
74 |
2 |
2 |
100.00 |
| TERNARY |
225 |
3 |
3 |
100.00 |
| TERNARY |
249 |
2 |
2 |
100.00 |
| TERNARY |
290 |
3 |
3 |
100.00 |
| TERNARY |
325 |
2 |
2 |
100.00 |
| TERNARY |
346 |
2 |
2 |
100.00 |
| IF |
125 |
3 |
3 |
100.00 |
| IF |
135 |
3 |
3 |
100.00 |
| IF |
156 |
3 |
3 |
100.00 |
| IF |
174 |
3 |
3 |
100.00 |
| IF |
252 |
3 |
3 |
100.00 |
| IF |
294 |
2 |
2 |
100.00 |
| IF |
302 |
5 |
5 |
100.00 |
| IF |
329 |
3 |
3 |
100.00 |
| IF |
350 |
2 |
2 |
100.00 |
| CASE |
373 |
5 |
5 |
100.00 |
| IF |
381 |
6 |
6 |
100.00 |
| IF |
399 |
3 |
3 |
100.00 |
| IF |
409 |
3 |
3 |
100.00 |
| IF |
432 |
3 |
3 |
100.00 |
| IF |
440 |
2 |
2 |
100.00 |
| IF |
463 |
3 |
3 |
100.00 |
| IF |
483 |
2 |
2 |
100.00 |
| IF |
487 |
2 |
2 |
100.00 |
| IF |
505 |
2 |
2 |
100.00 |
| IF |
509 |
2 |
2 |
100.00 |
| IF |
554 |
2 |
2 |
100.00 |
| IF |
558 |
2 |
2 |
100.00 |
| IF |
569 |
2 |
2 |
100.00 |
| IF |
598 |
2 |
2 |
100.00 |
| IF |
602 |
2 |
2 |
100.00 |
| IF |
621 |
2 |
2 |
100.00 |
| IF |
625 |
2 |
2 |
100.00 |
| IF |
635 |
3 |
3 |
100.00 |
73 assign usb_dp_flipped = cfg_pinflip_i ? usb_dn_i : usb_dp_i;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T49,T50 |
| 0 |
Covered |
T1,T2,T3 |
74 assign usb_dn_flipped = cfg_pinflip_i ? usb_dp_i : usb_dn_i;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T49,T50 |
| 0 |
Covered |
T1,T2,T3 |
225 assign line_state_rx = cfg_use_diff_rcvr_i ? (use_se ? line_state_q : diff_state_q) :
-1- -2-
==>
==> ==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
1 |
Covered |
T1,T2,T3 |
| 1 |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
Covered |
T1,T2,T3 |
249 assign bit_phase_d = (line_state_rx == DT) ? 0 : bit_phase_q + 1;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
290 assign in_packet_d = see_eop ? 1'b0 :
-1-
==>
291 see_sop ? 1'b1 : in_packet_q;
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T3,T28 |
| 0 |
0 |
Covered |
T1,T2,T3 |
325 assign line_history_d = line_state_valid ? {line_history_q[9:0], line_state_rx[1:0]} :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
346 assign rx_idle_det_d = (~tx_en_i & line_state_valid) ? (line_state_q == DJ) : rx_idle_det_q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
125 if (tx_en_i) begin
-1-
126 dpair = DJ[1:0]; // J
==>
127 ddiff = DJ[1:0]; // J
128 end else begin
129 dpair = {usb_dp_flipped, usb_dn_flipped};
130 ddiff = usb_d_flipped ? DJ[1:0] : DK[1:0]; // equiv to {usb_d_i, ~usb_d_i}
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T28,T29 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
135 if (!rst_ni) begin
-1-
136 line_state_q <= SE0;
==>
137 line_state_qq <= SE0;
138 diff_state_q <= SE0;
139 end else begin
140 if (link_reset_i) begin
-2-
141 line_state_q <= SE0;
==>
142 line_state_qq <= SE0;
143 diff_state_q <= SE0;
144 end else begin
145 line_state_q <= line_state_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
156 if (line_state_q == DT) begin
-1-
157 // if we are in a transition state, then we can sample the pair and
158 // move to the next corresponding line state
159 line_state_d = {1'b0, dpair};
==>
160
161 end else begin
162 // if we are in a valid line state and the value of the pair changes,
163 // then we need to move to the transition state
164 if (dpair != line_state_q[1:0]) begin
-2-
165 line_state_d = DT;
==>
166 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
174 if (diff_state_q == DT) begin
-1-
175 // if we are in a transition state, then we can sample the diff input and
176 // move to the next corresponding line state
177 diff_state_d = {1'b0, ddiff};
==>
178
179 end else begin
180 // if we are in a valid line state and the value of the diff input changes,
181 // then we need to move to the transition state
182 if (ddiff != diff_state_q[1:0]) begin
-2-
183 diff_state_d = DT;
==>
184 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
252 if (!rst_ni) begin
-1-
253 bit_phase_q <= 0;
==>
254 end else begin
255 if (link_reset_i) begin
-2-
256 bit_phase_q <= 0;
==>
257 end else begin
258 bit_phase_q <= bit_phase_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
294 if (!rst_ni) begin
-1-
295 in_packet_q <= 1'b0;
==>
296 end else begin
297 in_packet_q <= in_packet_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
302 if (line_state_valid) begin
-1-
303 // If the differential K and J symbols are not valid, reject the
304 // containing packet as invalid.
305 if (~diff_rx_ok_i) begin
-2-
306 packet_valid_d = 0;
==>
307 // check for packet start: KJKJKK, we use the last 6 bits
308 end else if (!packet_valid_q && line_history_q[11:0] == 12'b011001100101) begin
-3-
309 packet_valid_d = 1;
==>
310 end
311
312 // check for packet end: SE0 SE0
313 else if (packet_valid_q && see_eop) begin
-4-
314 packet_valid_d = 0;
==>
315
316 end else begin
317 packet_valid_d = packet_valid_q;
==>
318 end
319 end else begin
320 packet_valid_d = packet_valid_q;
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
1 |
- |
- |
Covered |
T7,T22,T8 |
| 1 |
0 |
1 |
- |
Covered |
T1,T3,T28 |
| 1 |
0 |
0 |
1 |
Covered |
T1,T3,T28 |
| 1 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
Covered |
T1,T2,T3 |
329 if (!rst_ni) begin
-1-
330 packet_valid_q <= 0;
==>
331 line_history_q <= 12'b101010101010; // all K
332 end else begin
333 if (link_reset_i) begin
-2-
334 packet_valid_q <= 0;
==>
335 line_history_q <= 12'b101010101010; // all K
336 end else begin
337 packet_valid_q <= packet_valid_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
350 if (!rst_ni) begin
-1-
351 rx_idle_det_q <= 1'b0;
==>
352 end else begin
353 rx_idle_det_q <= rx_idle_det_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
373 unique case (line_history_q[3:0])
-1-
374 4'b0101 : din = 1;
==>
375 4'b0110 : din = 0;
==>
376 4'b1001 : din = 0;
==>
377 4'b1010 : din = 1;
==>
378 default : din = 0;
==>
Branches:
| -1- | Status | Tests |
| 4'b0101 |
Covered |
T1,T3,T28 |
| 4'b0110 |
Covered |
T1,T3,T28 |
| 4'b1001 |
Covered |
T1,T3,T28 |
| 4'b1010 |
Covered |
T1,T2,T3 |
| default |
Covered |
T1,T2,T3 |
381 if (packet_valid_q && line_state_valid) begin
-1-
382 unique case (line_history_q[3:0])
-2-
383 4'b0101 : dvalid_raw = 1;
==>
384 4'b0110 : dvalid_raw = 1;
==>
385 4'b1001 : dvalid_raw = 1;
==>
386 4'b1010 : dvalid_raw = 1;
==>
387 default : dvalid_raw = 0;
==>
388 endcase
389 end else begin
390 dvalid_raw = 0;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
4'b0101 |
Covered |
T1,T3,T28 |
| 1 |
4'b0110 |
Covered |
T1,T3,T28 |
| 1 |
4'b1001 |
Covered |
T1,T3,T28 |
| 1 |
4'b1010 |
Covered |
T1,T3,T28 |
| 1 |
default |
Covered |
T1,T3,T28 |
| 0 |
- |
Covered |
T1,T2,T3 |
399 if (packet_end) begin
-1-
400 bitstuff_history_d = '0;
==>
401 end else if (dvalid_raw) begin
-2-
402 bitstuff_history_d = {bitstuff_history_q[5:0], din};
==>
403 end else begin
404 bitstuff_history_d = bitstuff_history_q;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T3,T28 |
| 0 |
1 |
Covered |
T1,T3,T28 |
| 0 |
0 |
Covered |
T1,T2,T3 |
409 if (!rst_ni) begin
-1-
410 bitstuff_history_q <= 0;
==>
411 end else begin
412 if (link_reset_i) begin
-2-
413 bitstuff_history_q <= 0;
==>
414 end else begin
415 bitstuff_history_q <= bitstuff_history_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
432 if (packet_start) begin
-1-
433 bitstuff_error_d = 0;
==>
434 end else if (bitstuff_error && dvalid_raw) begin
-2-
435 bitstuff_error_d = 1;
==>
436 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T3,T28 |
| 0 |
1 |
Covered |
T3,T84,T79 |
| 0 |
0 |
Covered |
T1,T2,T3 |
440 if (!rst_ni) begin
-1-
441 bitstuff_error_q <= 0;
==>
442 end else begin
443 bitstuff_error_q <= bitstuff_error_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
463 if (dvalid && !pid_complete) begin
-1-
464 full_pid_d = {din, full_pid_q[8:1]};
==>
465 end else if (packet_start) begin
-2-
466 full_pid_d = 9'b100000000;
==>
467 end else begin
468 full_pid_d = full_pid_q;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T3,T28 |
| 0 |
1 |
Covered |
T1,T3,T28 |
| 0 |
0 |
Covered |
T1,T2,T3 |
483 if (packet_start) begin
-1-
484 crc5_d = 5'b11111;
==>
485 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
487 if (dvalid && pid_complete) begin
-1-
488 crc5_d = {crc5_q[3:0], 1'b0} ^ ({5{crc5_invert}} & 5'b00101);
==>
489 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
505 if (packet_start) begin
-1-
506 crc16_d = 16'b1111111111111111;
==>
507 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
509 if (dvalid && pid_complete) begin
-1-
510 crc16_d = {crc16_q[14:0], 1'b0} ^ ({16{crc16_invert}} & 16'b1000000000000101);
==>
511 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
554 if (packet_start) begin
-1-
555 token_payload_d = 12'b100000000000;
==>
556 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
558 if (dvalid && pid_complete && pkt_is_token && !token_payload_done) begin
-1-
559 token_payload_d = {din, token_payload_q[11:1]};
==>
560 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
569 if (token_payload_done && pkt_is_token) begin
-1-
570 addr_d = token_payload_q[7:1];
==>
571 endp_d = token_payload_q[11:8];
572 frame_num_d = token_payload_q[11:1];
573 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
598 if (packet_start || rx_data_buffer_full) begin
-1-
599 rx_data_buffer_d = 9'b100000000;
==>
600 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
602 if (dvalid && pid_complete && pkt_is_data) begin
-1-
603 rx_data_buffer_d = {din, rx_data_buffer_q[8:1]};
==>
604 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
621 if (packet_start) begin
-1-
622 rx_data_len16_d = 1'b0;
==>
623 rx_data_len_d = 4'h0;
624 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
625 if (dvalid && pid_complete) begin
-1-
626 rx_data_len16_d = rx_data_len16_q | &rx_data_len_q;
==>
627 rx_data_len_d = rx_data_len_q + 4'h1;
628 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
635 if (!rst_ni) begin
-1-
636 full_pid_q <= 0;
==>
637 crc16_q <= 0;
638 crc5_q <= 0;
639 token_payload_q <= 0;
640 addr_q <= 0;
641 endp_q <= 0;
642 frame_num_q <= 0;
643 rx_data_buffer_q <= 0;
644 rx_data_len16_q <= 0;
645 rx_data_len_q <= 0;
646 end else begin
647 if (link_reset_i) begin
-2-
648 full_pid_q <= 0;
==>
649 crc16_q <= 0;
650 crc5_q <= 0;
651 token_payload_q <= 0;
652 addr_q <= 0;
653 endp_q <= 0;
654 frame_num_q <= 0;
655 rx_data_buffer_q <= 0;
656 rx_data_len16_q <= 0;
657 rx_data_len_q <= 0;
658 end else begin
659 full_pid_q <= full_pid_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_rx
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 204 | 204 | 100.00 |
| CONT_ASSIGN | 73 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 75 | 1 | 1 | 100.00 |
| ALWAYS | 125 | 5 | 5 | 100.00 |
| ALWAYS | 135 | 11 | 11 | 100.00 |
| ALWAYS | 154 | 5 | 5 | 100.00 |
| ALWAYS | 172 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 224 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 225 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 245 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 246 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
| ALWAYS | 252 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 290 | 1 | 1 | 100.00 |
| ALWAYS | 294 | 3 | 3 | 100.00 |
| ALWAYS | 302 | 9 | 9 | 100.00 |
| CONT_ASSIGN | 325 | 1 | 1 | 100.00 |
| ALWAYS | 329 | 8 | 8 | 100.00 |
| CONT_ASSIGN | 346 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 347 | 1 | 1 | 100.00 |
| ALWAYS | 350 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 358 | 1 | 1 | 100.00 |
| ALWAYS | 373 | 12 | 12 | 100.00 |
| ALWAYS | 399 | 5 | 5 | 100.00 |
| ALWAYS | 409 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 421 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 427 | 1 | 1 | 100.00 |
| ALWAYS | 431 | 5 | 5 | 100.00 |
| ALWAYS | 440 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 447 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 460 | 1 | 1 | 100.00 |
| ALWAYS | 463 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 477 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 478 | 1 | 1 | 100.00 |
| ALWAYS | 481 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 499 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 500 | 1 | 1 | 100.00 |
| ALWAYS | 503 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 521 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 522 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 523 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 525 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 528 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 530 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 536 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 537 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 540 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 545 | 1 | 1 | 100.00 |
| ALWAYS | 552 | 5 | 5 | 100.00 |
| ALWAYS | 565 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 576 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 577 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 578 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 579 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 581 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 582 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 591 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 592 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 593 | 1 | 1 | 100.00 |
| ALWAYS | 596 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 613 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 614 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 615 | 1 | 1 | 100.00 |
| ALWAYS | 618 | 8 | 8 | 100.00 |
| ALWAYS | 635 | 32 | 32 | 100.00 |
72 logic usb_dp_flipped, usb_dn_flipped, usb_d_flipped;
73 1/1 assign usb_dp_flipped = cfg_pinflip_i ? usb_dn_i : usb_dp_i;
Tests: T1 T2 T3
74 1/1 assign usb_dn_flipped = cfg_pinflip_i ? usb_dp_i : usb_dn_i;
Tests: T1 T2 T3
75 1/1 assign usb_d_flipped = usb_d_i ^ cfg_pinflip_i;
Tests: T1 T2 T3
76
77 ///////////////////////////////////////
78 // line state recovery state machine //
79 ///////////////////////////////////////
80
81 // If the receive path is set NOT to use an external differential receiver:
82 // This block samples data purely from the usb_dp_i/usb_dn_i pair.
83 // There is a chance that one of the signals in the pair will appear to have
84 // changed to the new state while the other is still in the old state. The
85 // following state machine detects transitions and waits an extra sampling clock
86 // before decoding the state on the dp/dn pair. This transition period will
87 // only ever last for one clock as long as there is no noise on the line.
88 // If there is enough noise on the line then the data may be corrupted and the
89 // packet will fail the data integrity checks.
90
91 // If the receive path uses an external differential receiver:
92 // This block uses the usb_d_i input to detect K and J symbols.
93 // The individual signals of the differential pair must still be connected
94 // to this block to detect SE0.
95 // Note that the spec warns in section 7.1.4.1:
96 // Both D+ and D- may temporarily be less than VIH (min) during differential
97 // signal transitions. This period can be up to 14 ns (TFST) for full-speed
98 // transitions and up to 210 ns (TLST) for low-speed transitions. Logic in the
99 // receiver must ensure that this is not interpreted as an SE0.
100 // Since the 48MHz sample clock is 20.833ns period we will either miss this or
101 // sample it only once, so it will be covered by line_state=DT and the next
102 // sample will not be SE0 unless this was a real SE0 transition
103 // Note: if it is a real SE0 the usb_d_i input could be doing anything.
104
105 logic [2:0] line_state_qq, line_state_q, line_state_d;
106 logic [2:0] diff_state_q, diff_state_d;
107 logic [2:0] line_state_rx;
108 logic use_se;
109
110 localparam logic [2:0] DT = 3'b100; // transition state
111 localparam logic [2:0] DJ = 3'b010; // J - idle line state
112 localparam logic [2:0] DK = 3'b001; // K - inverse of J
113 localparam logic [2:0] SE0 = 3'b000; // single-ended 0 - end of packet or detached
114 // localparam logic [2:0] SE1 = 3'b011; // single-ended 1 - illegal
115
116 // Mute the input if we're transmitting
117 // dpair is the usb_dp_i/usb_dn_i pair, used in both modes. With
118 // an external differential receiver, it is only used for detecting SE0 and
119 // transitions. Without an external differential receiver driving the
120 // usb_d_i input, it is used for all symbols.
121 // ddiff is the decoded data input from an external differential receiver,
122 // if available, and it is only for K and J symbols, plus transition detection.
123 logic [1:0] dpair, ddiff;
124 always_comb begin : proc_dpair_mute
125 1/1 if (tx_en_i) begin
Tests: T1 T2 T3
126 1/1 dpair = DJ[1:0]; // J
Tests: T1 T28 T29
127 1/1 ddiff = DJ[1:0]; // J
Tests: T1 T28 T29
128 end else begin
129 1/1 dpair = {usb_dp_flipped, usb_dn_flipped};
Tests: T1 T2 T3
130 1/1 ddiff = usb_d_flipped ? DJ[1:0] : DK[1:0]; // equiv to {usb_d_i, ~usb_d_i}
Tests: T1 T2 T3
131 end
132 end
133
134 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_line_state_q
135 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
136 1/1 line_state_q <= SE0;
Tests: T1 T2 T3
137 1/1 line_state_qq <= SE0;
Tests: T1 T2 T3
138 1/1 diff_state_q <= SE0;
Tests: T1 T2 T3
139 end else begin
140 1/1 if (link_reset_i) begin
Tests: T1 T2 T3
141 1/1 line_state_q <= SE0;
Tests: T1 T2 T3
142 1/1 line_state_qq <= SE0;
Tests: T1 T2 T3
143 1/1 diff_state_q <= SE0;
Tests: T1 T2 T3
144 end else begin
145 1/1 line_state_q <= line_state_d;
Tests: T1 T2 T3
146 1/1 line_state_qq <= line_state_q;
Tests: T1 T2 T3
147 1/1 diff_state_q <= diff_state_d;
Tests: T1 T2 T3
148 end
149 end
150 end
151
152 always_comb begin : proc_line_state_d
153 // Default assignment
154 1/1 line_state_d = line_state_q;
Tests: T1 T2 T3
155
156 1/1 if (line_state_q == DT) begin
Tests: T1 T2 T3
157 // if we are in a transition state, then we can sample the pair and
158 // move to the next corresponding line state
159 1/1 line_state_d = {1'b0, dpair};
Tests: T1 T2 T3
160
161 end else begin
162 // if we are in a valid line state and the value of the pair changes,
163 // then we need to move to the transition state
164 1/1 if (dpair != line_state_q[1:0]) begin
Tests: T1 T2 T3
165 1/1 line_state_d = DT;
Tests: T1 T2 T3
166 end
MISSING_ELSE
167 end
168 end
169
170 always_comb begin : proc_diff_state_d
171 // Default assignment
172 1/1 diff_state_d = diff_state_q;
Tests: T1 T2 T3
173
174 1/1 if (diff_state_q == DT) begin
Tests: T1 T2 T3
175 // if we are in a transition state, then we can sample the diff input and
176 // move to the next corresponding line state
177 1/1 diff_state_d = {1'b0, ddiff};
Tests: T1 T2 T3
178
179 end else begin
180 // if we are in a valid line state and the value of the diff input changes,
181 // then we need to move to the transition state
182 1/1 if (ddiff != diff_state_q[1:0]) begin
Tests: T1 T2 T3
183 1/1 diff_state_d = DT;
Tests: T1 T2 T3
184 end
MISSING_ELSE
185 end
186 end
187
188 // The received line state depends on how the receiver is configured:
189 // NOT using a differential receiver: it is just the line_state_q that was captured
190 //
191 // Using a differential receiver: recovered from the differential receiver (diff_state_q)
192 // unless the diff pair indicate SE0 when the differential
193 // receiver could produce any value
194 //
195 // Transition where the dp/dn pair happen to see SE0 will look like (driven by diff DT)
196 // line_state D? DT D?...
197 // diff_state Dx DT Dy (expect Dy to be inverse of Dx since diff changed)
198 //
199 // Transition to SE0 when usb_d_i changes will look like:
200 // line_state DT D? D? D? DT SE0 SE0... (DT is the first sample at SE0)
201 // diff_state DT Dx Dx Dx DT ?? ??... (diff saw transition as line went SE0)
202 // --> out DT Dx Dx Dx DT SE0 SE0 (if no transition then DT would be Dx and n=3)
203 // bit_phase n 0 1 2 3 0 1 (n=3 unless there was a clock resync)
204 //
205 // Transition to SE0 when usb_d_i does not change will look like:
206 // line_state DT D? D? D? DT SE0 SE0... (DT is the first sample at SE0)
207 // diff_state DT Dx Dx Dx Dx ?? ??... (diff no transition as line went SE0)
208 // --> out DT Dx Dx Dx Dx SE0 SE0 (if no transition then DT would be Dx and n=3)
209 // bit_phase n 0 1 2 3 0 1 (n=3 unless there was a clock resync)
210 //
211 // Transition to SE0 when usb_d_i does not change and clock resync earlier:
212 // line_state DT D? D? DT SE0 SE0 SE0... (DT is the first sample at SE0, should resync clock)
213 // diff_state DT Dx Dx Dx Dx ?? ??... (diff no transition as line went SE0)
214 // --> out DT Dx Dx Dx SE0 SE0 SE0 (if no transition then DT would be Dx and n=3)
215 // bit_phase n 0 1 2 3 0 1 (n=3 unless there was a clock resync)
216 //
217 // On transition back from SE0 want to generate a DT to resync the clock
218 // since SE0 could have gone on a while no idea what bit_phase is
219 // line_state SE0 SE0 DT D? D? D?
220 // diff_state ?? ?? ?? Dx Dx Dx
221 // --> out SE0 SE0 DT Dx Dx Dx
222 // bit_phase ? ? ? 0 1 2
223
224 1/1 assign use_se = (line_state_q == SE0) || ((line_state_q == DT) && (line_state_qq == SE0));
Tests: T1 T2 T3
225 1/1 assign line_state_rx = cfg_use_diff_rcvr_i ? (use_se ? line_state_q : diff_state_q) :
Tests: T1 T2 T3
226 line_state_q;
227
228 ////////////////////
229 // clock recovery //
230 ////////////////////
231
232 // the DT state from the line state recovery state machine is used to align to
233 // transmit clock. the line state is sampled in the middle of the bit time.
234
235 // example of signal relationships
236 // -------------------------------
237 // line_state DT DJ DJ DJ DT DK DK DK DK DK DK DT DJ DJ DJ
238 // line_state_valid ________----____________----____________----________----____
239 // bit_phase 0 0 1 2 3 0 1 2 3 0 1 2 0 1 2
240
241
242 logic [1:0] bit_phase_q, bit_phase_d;
243 logic line_state_valid;
244
245 1/1 assign line_state_valid = (bit_phase_q == 2'd1);
Tests: T1 T2 T3
246 1/1 assign bit_strobe_o = (bit_phase_q == 2'd2);
Tests: T1 T2 T3
247
248 // keep track of phase within each bit
249 1/1 assign bit_phase_d = (line_state_rx == DT) ? 0 : bit_phase_q + 1;
Tests: T1 T2 T3
250
251 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_bit_phase_q
252 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
253 1/1 bit_phase_q <= 0;
Tests: T1 T2 T3
254 end else begin
255 1/1 if (link_reset_i) begin
Tests: T1 T2 T3
256 1/1 bit_phase_q <= 0;
Tests: T1 T2 T3
257 end else begin
258 1/1 bit_phase_q <= bit_phase_d;
Tests: T1 T2 T3
259 end
260 end
261 end
262
263
264 //////////////////////
265 // packet detection //
266 //////////////////////
267
268 // usb uses a sync to denote the beginning of a packet's PID and two
269 // single-ended-0 to denote the end of a packet. this state machine
270 // recognizes the beginning and end of packets for subsequent layers to
271 // process.
272
273 logic [11:0] line_history_q, line_history_d;
274 logic packet_valid_q, packet_valid_d;
275 logic see_sop, see_eop, see_preamble, packet_start, packet_end;
276 logic in_packet_d, in_packet_q;
277
278 // A bit of a misnomer: packet_start pulses when the PID begins, not SOP.
279 1/1 assign packet_start = packet_valid_d & ~packet_valid_q;
Tests: T1 T2 T3
280 1/1 assign packet_end = ~packet_valid_d & packet_valid_q;
Tests: T1 T2 T3
281
282 // EOP detection is configurable for 1/2 bit periods of SE0.
283 // The standard (Table 7-7) mandates min = 82 ns = 1 bit period.
284 // We also trigger an EOP on seeing a bitstuff error or a PRE PID.
285 1/1 assign see_eop = (cfg_eop_single_bit_i && line_history_q[1:0] == 2'b00)
Tests: T1 T2 T3
286 || (line_history_q[3:0] == 4'b0000) || bitstuff_error_q || see_preamble;
287
288 // SOP is the transition from idle (J) to K
289 1/1 assign see_sop = (line_history_q[3:0] == 4'b1001) & ~tx_en_i & ~in_packet_q;
Tests: T1 T2 T3
290 1/1 assign in_packet_d = see_eop ? 1'b0 :
Tests: T1 T2 T3
291 see_sop ? 1'b1 : in_packet_q;
292
293 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_reg_in_packet
294 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
295 1/1 in_packet_q <= 1'b0;
Tests: T1 T2 T3
296 end else begin
297 1/1 in_packet_q <= in_packet_d;
Tests: T1 T2 T3
298 end
299 end
300
301 always_comb begin : proc_packet_valid_d
302 1/1 if (line_state_valid) begin
Tests: T1 T2 T3
303 // If the differential K and J symbols are not valid, reject the
304 // containing packet as invalid.
305 1/1 if (~diff_rx_ok_i) begin
Tests: T1 T2 T3
306 1/1 packet_valid_d = 0;
Tests: T7 T22 T8
307 // check for packet start: KJKJKK, we use the last 6 bits
308 1/1 end else if (!packet_valid_q && line_history_q[11:0] == 12'b011001100101) begin
Tests: T1 T2 T3
309 1/1 packet_valid_d = 1;
Tests: T1 T3 T28
310 end
311
312 // check for packet end: SE0 SE0
313 1/1 else if (packet_valid_q && see_eop) begin
Tests: T1 T2 T3
314 1/1 packet_valid_d = 0;
Tests: T1 T3 T28
315
316 end else begin
317 1/1 packet_valid_d = packet_valid_q;
Tests: T1 T2 T3
318 end
319 end else begin
320 1/1 packet_valid_d = packet_valid_q;
Tests: T1 T2 T3
321 end
322 end
323
324 // keep a history of the last two states on the line
325 1/1 assign line_history_d = line_state_valid ? {line_history_q[9:0], line_state_rx[1:0]} :
Tests: T1 T2 T3
326 line_history_q;
327
328 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_reg_pkt_line
329 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
330 1/1 packet_valid_q <= 0;
Tests: T1 T2 T3
331 1/1 line_history_q <= 12'b101010101010; // all K
Tests: T1 T2 T3
332 end else begin
333 1/1 if (link_reset_i) begin
Tests: T1 T2 T3
334 1/1 packet_valid_q <= 0;
Tests: T1 T2 T3
335 1/1 line_history_q <= 12'b101010101010; // all K
Tests: T1 T2 T3
336 end else begin
337 1/1 packet_valid_q <= packet_valid_d;
Tests: T1 T2 T3
338 1/1 line_history_q <= line_history_d;
Tests: T1 T2 T3
339 end
340 end
341 end
342
343 // mask out idle detection when transmitting (because rx may be forced to
344 // J and look like an idle symbol)
345 logic rx_idle_det_d, rx_idle_det_q;
346 1/1 assign rx_idle_det_d = (~tx_en_i & line_state_valid) ? (line_state_q == DJ) : rx_idle_det_q;
Tests: T1 T2 T3
347 1/1 assign rx_idle_det_o = rx_idle_det_q;
Tests: T1 T2 T3
348
349 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_reg_idle_det
350 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
351 1/1 rx_idle_det_q <= 1'b0;
Tests: T1 T2 T3
352 end else begin
353 1/1 rx_idle_det_q <= rx_idle_det_d;
Tests: T1 T2 T3
354 end
355 end
356
357 // Used for seeing a J after the completion of resume signaling
358 1/1 assign rx_j_det_o = diff_rx_ok_i & ~tx_en_i & (line_history_q[1:0] == 2'b10);
Tests: T1 T2 T3
359
360 /////////////////
361 // NRZI decode //
362 /////////////////
363
364 // in order to ensure there are enough bit transitions for a receiver to recover
365 // the clock usb uses NRZI encoding.
366
367 // https://en.wikipedia.org/wiki/Non-return-to-zero
368
369 logic dvalid_raw;
370 logic din;
371
372 always_comb begin
373 1/1 unique case (line_history_q[3:0])
Tests: T1 T2 T3
374 1/1 4'b0101 : din = 1;
Tests: T1 T3 T28
375 1/1 4'b0110 : din = 0;
Tests: T1 T3 T28
376 1/1 4'b1001 : din = 0;
Tests: T1 T3 T28
377 1/1 4'b1010 : din = 1;
Tests: T1 T2 T3
378 default : din = 0;
379 endcase
380
381 1/1 if (packet_valid_q && line_state_valid) begin
Tests: T1 T2 T3
382 1/1 unique case (line_history_q[3:0])
Tests: T1 T3 T28
383 1/1 4'b0101 : dvalid_raw = 1;
Tests: T1 T3 T28
384 1/1 4'b0110 : dvalid_raw = 1;
Tests: T1 T3 T28
385 1/1 4'b1001 : dvalid_raw = 1;
Tests: T1 T3 T28
386 1/1 4'b1010 : dvalid_raw = 1;
Tests: T1 T3 T28
387 default : dvalid_raw = 0;
388 endcase
389 end else begin
390 1/1 dvalid_raw = 0;
Tests: T1 T2 T3
391 end
392 end
393
394 //////////////////////////////////////////////////////
395 // Undo bit stuffing and detect bit stuffing errors //
396 //////////////////////////////////////////////////////
397
398 always_comb begin : proc_bitstuff_history_d
399 1/1 if (packet_end) begin
Tests: T1 T2 T3
400 1/1 bitstuff_history_d = '0;
Tests: T1 T3 T28
401 1/1 end else if (dvalid_raw) begin
Tests: T1 T2 T3
402 1/1 bitstuff_history_d = {bitstuff_history_q[5:0], din};
Tests: T1 T3 T28
403 end else begin
404 1/1 bitstuff_history_d = bitstuff_history_q;
Tests: T1 T2 T3
405 end
406 end
407
408 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_bitstuff_history_q
409 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
410 1/1 bitstuff_history_q <= 0;
Tests: T1 T2 T3
411 end else begin
412 1/1 if (link_reset_i) begin
Tests: T1 T2 T3
413 1/1 bitstuff_history_q <= 0;
Tests: T1 T2 T3
414 end else begin
415 1/1 bitstuff_history_q <= bitstuff_history_d;
Tests: T1 T2 T3
416 end
417 end
418 end
419
420 logic dvalid;
421 1/1 assign dvalid = dvalid_raw && !(bitstuff_history_q[5:0] == 6'b111111);
Tests: T1 T2 T3
422
423 // 7 consecutive ones should not be seen on the bus
424 // USB spec, 7.1.9.1: "If the receiver sees seven
425 // consecutive ones anywhere in the packet, then a bit stuffing error
426 // has occurred and the packet should be ignored."
427 1/1 assign bitstuff_error = bitstuff_history_q == 7'b1111111;
Tests: T1 T2 T3
428
429 // remember the bitstuff errors
430 always_comb begin : proc_bistuff_error_d
431 1/1 bitstuff_error_d = bitstuff_error_q;
Tests: T1 T2 T3
432 1/1 if (packet_start) begin
Tests: T1 T2 T3
433 1/1 bitstuff_error_d = 0;
Tests: T1 T3 T28
434 1/1 end else if (bitstuff_error && dvalid_raw) begin
Tests: T1 T2 T3
435 1/1 bitstuff_error_d = 1;
Tests: T3 T84 T79
436 end
MISSING_ELSE
437 end
438
439 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_bitstuff_error_q
440 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
441 1/1 bitstuff_error_q <= 0;
Tests: T1 T2 T3
442 end else begin
443 1/1 bitstuff_error_q <= bitstuff_error_d;
Tests: T1 T2 T3
444 end
445 end
446
447 1/1 assign bitstuff_error_o = bitstuff_error_q && packet_end;
Tests: T1 T2 T3
448
449
450 ////////////////////////
451 // save and check pid //
452 ////////////////////////
453
454 // shift in the entire 8-bit pid with an additional 9th bit used as a sentinel.
455
456 logic [8:0] full_pid_q, full_pid_d;
457 logic pid_valid, pid_complete;
458
459 1/1 assign pid_valid = full_pid_q[4:1] == ~full_pid_q[8:5];
Tests: T1 T2 T3
460 1/1 assign pid_complete = full_pid_q[0];
Tests: T1 T2 T3
461
462 always_comb begin : proc_full_pid_d
463 1/1 if (dvalid && !pid_complete) begin
Tests: T1 T2 T3
464 1/1 full_pid_d = {din, full_pid_q[8:1]};
Tests: T1 T3 T28
465 1/1 end else if (packet_start) begin
Tests: T1 T2 T3
466 1/1 full_pid_d = 9'b100000000;
Tests: T1 T3 T28
467 end else begin
468 1/1 full_pid_d = full_pid_q;
Tests: T1 T2 T3
469 end
470 end
471
472 ////////////////
473 // check crc5 //
474 ////////////////
475 logic [4:0] crc5_q, crc5_d;
476 logic crc5_valid, crc5_invert;
477 1/1 assign crc5_valid = crc5_q == 5'b01100;
Tests: T1 T2 T3
478 1/1 assign crc5_invert = din ^ crc5_q[4];
Tests: T1 T2 T3
479
480 always_comb begin
481 1/1 crc5_d = crc5_q; // default value
Tests: T1 T2 T3
482
483 1/1 if (packet_start) begin
Tests: T1 T2 T3
484 1/1 crc5_d = 5'b11111;
Tests: T1 T3 T28
485 end
MISSING_ELSE
486
487 1/1 if (dvalid && pid_complete) begin
Tests: T1 T2 T3
488 1/1 crc5_d = {crc5_q[3:0], 1'b0} ^ ({5{crc5_invert}} & 5'b00101);
Tests: T1 T3 T28
489 end
MISSING_ELSE
490 end
491
492
493 /////////////////
494 // check crc16 //
495 /////////////////
496 logic [15:0] crc16_q, crc16_d;
497 logic crc16_valid, crc16_invert;
498
499 1/1 assign crc16_valid = crc16_q == 16'b1000000000001101;
Tests: T1 T2 T3
500 1/1 assign crc16_invert = din ^ crc16_q[15];
Tests: T1 T2 T3
501
502 always_comb begin
503 1/1 crc16_d = crc16_q; // default value
Tests: T1 T2 T3
504
505 1/1 if (packet_start) begin
Tests: T1 T2 T3
506 1/1 crc16_d = 16'b1111111111111111;
Tests: T1 T3 T28
507 end
MISSING_ELSE
508
509 1/1 if (dvalid && pid_complete) begin
Tests: T1 T2 T3
510 1/1 crc16_d = {crc16_q[14:0], 1'b0} ^ ({16{crc16_invert}} & 16'b1000000000000101);
Tests: T1 T3 T28
511 end
MISSING_ELSE
512 end
513
514
515 ////////////////////////////
516 // output control signals //
517 ////////////////////////////
518 logic valid_token_len, valid_data_len, valid_handshake_len;
519
520 logic pkt_is_token, pkt_is_data, pkt_is_handshake;
521 1/1 assign pkt_is_token = full_pid_q[2:1] == 2'b01;
Tests: T1 T2 T3
522 1/1 assign pkt_is_data = full_pid_q[2:1] == 2'b11;
Tests: T1 T2 T3
523 1/1 assign pkt_is_handshake = full_pid_q[2:1] == 2'b10;
Tests: T1 T2 T3
524
525 1/1 assign see_preamble = packet_valid_q & pid_valid & pid_complete &&
Tests: T1 T2 T3
526 (usb_pid_e'(full_pid_q[4:1]) == UsbPidPre);
527
528 1/1 assign valid_pid_o = pid_valid;
Tests: T1 T2 T3
529
530 1/1 assign valid_packet_o = pid_valid && !bitstuff_error_q &&
Tests: T1 T2 T3
531 ((pkt_is_handshake && valid_handshake_len) ||
532 (pkt_is_data && valid_data_len && crc16_valid) ||
533 (pkt_is_token && valid_token_len && crc5_valid));
534
535 // Detect CRC errors
536 1/1 assign crc5_error_o = pkt_is_token & packet_end & !crc5_valid;
Tests: T1 T2 T3
537 1/1 assign crc16_error_o = pkt_is_data & packet_end & !crc16_valid;
Tests: T1 T2 T3
538
539 // Detect PID errors
540 1/1 assign pid_error_o = !pid_valid && packet_end;
Tests: T1 T2 T3
541
542 logic [11:0] token_payload_q, token_payload_d;
543 logic token_payload_done;
544
545 1/1 assign token_payload_done = token_payload_q[0];
Tests: T1 T2 T3
546
547 logic [6:0] addr_q, addr_d;
548 logic [3:0] endp_q, endp_d;
549 logic [10:0] frame_num_q, frame_num_d;
550
551 always_comb begin
552 1/1 token_payload_d = token_payload_q; // default
Tests: T1 T2 T3
553
554 1/1 if (packet_start) begin
Tests: T1 T2 T3
555 1/1 token_payload_d = 12'b100000000000;
Tests: T1 T3 T28
556 end
MISSING_ELSE
557
558 1/1 if (dvalid && pid_complete && pkt_is_token && !token_payload_done) begin
Tests: T1 T2 T3
559 1/1 token_payload_d = {din, token_payload_q[11:1]};
Tests: T1 T3 T28
560 end
MISSING_ELSE
561 end
562
563 always_comb begin
564 // defaults
565 1/1 addr_d = addr_q;
Tests: T1 T2 T3
566 1/1 endp_d = endp_q;
Tests: T1 T2 T3
567 1/1 frame_num_d = frame_num_q;
Tests: T1 T2 T3
568
569 1/1 if (token_payload_done && pkt_is_token) begin
Tests: T1 T2 T3
570 1/1 addr_d = token_payload_q[7:1];
Tests: T1 T3 T28
571 1/1 endp_d = token_payload_q[11:8];
Tests: T1 T3 T28
572 1/1 frame_num_d = token_payload_q[11:1];
Tests: T1 T3 T28
573 end
MISSING_ELSE
574 end
575
576 1/1 assign addr_o = addr_q;
Tests: T1 T2 T3
577 1/1 assign endp_o = endp_q;
Tests: T1 T2 T3
578 1/1 assign frame_num_o = frame_num_q;
Tests: T1 T2 T3
579 1/1 assign pid_o = full_pid_q[4:1];
Tests: T1 T2 T3
580
581 1/1 assign pkt_start_o = see_sop;
Tests: T1 T2 T3
582 1/1 assign pkt_end_o = packet_end;
Tests: T1 T2 T3
583
584
585 /////////////////////////////////
586 // deserialize and output data //
587 /////////////////////////////////
588 logic [8:0] rx_data_buffer_q, rx_data_buffer_d;
589 logic rx_data_buffer_full;
590
591 1/1 assign rx_data_buffer_full = rx_data_buffer_q[0];
Tests: T1 T2 T3
592 1/1 assign rx_data_put_o = rx_data_buffer_full;
Tests: T1 T2 T3
593 1/1 assign rx_data_o = rx_data_buffer_q[8:1];
Tests: T1 T2 T3
594
595 always_comb begin
596 1/1 rx_data_buffer_d = rx_data_buffer_q; // default
Tests: T1 T2 T3
597
598 1/1 if (packet_start || rx_data_buffer_full) begin
Tests: T1 T2 T3
599 1/1 rx_data_buffer_d = 9'b100000000;
Tests: T1 T3 T28
600 end
MISSING_ELSE
601
602 1/1 if (dvalid && pid_complete && pkt_is_data) begin
Tests: T1 T2 T3
603 1/1 rx_data_buffer_d = {din, rx_data_buffer_q[8:1]};
Tests: T1 T3 T28
604 end
MISSING_ELSE
605 end
606
607 // Counting packet length in bits; we need to know whether the length is byte-aligned,
608 // and whether it's equal to 16 (token packet) or at least 16 (data packet; CRC16 required).
609 logic rx_data_len16_q, rx_data_len16_d;
610 logic [3:0] rx_data_len_q, rx_data_len_d;
611
612 // Valid packet length indications.
613 1/1 assign valid_token_len = rx_data_len16_q & ~|rx_data_len_q;
Tests: T1 T2 T3
614 1/1 assign valid_data_len = rx_data_len16_q & ~|rx_data_len_q[2:0]; // Must be byte-aligned.
Tests: T1 T2 T3
615 1/1 assign valid_handshake_len = ~|{rx_data_len16_q, rx_data_len_q};
Tests: T1 T2 T3
616
617 always_comb begin
618 1/1 rx_data_len16_d = rx_data_len16_q;
Tests: T1 T2 T3
619 1/1 rx_data_len_d = rx_data_len_q;
Tests: T1 T2 T3
620
621 1/1 if (packet_start) begin
Tests: T1 T2 T3
622 1/1 rx_data_len16_d = 1'b0;
Tests: T1 T3 T28
623 1/1 rx_data_len_d = 4'h0;
Tests: T1 T3 T28
624 end
MISSING_ELSE
625 1/1 if (dvalid && pid_complete) begin
Tests: T1 T2 T3
626 1/1 rx_data_len16_d = rx_data_len16_q | &rx_data_len_q;
Tests: T1 T3 T28
627 1/1 rx_data_len_d = rx_data_len_q + 4'h1;
Tests: T1 T3 T28
628 end
MISSING_ELSE
629 end
630
631 ///////////////
632 // Registers //
633 ///////////////
634 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_gp_regs
635 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
636 1/1 full_pid_q <= 0;
Tests: T1 T2 T3
637 1/1 crc16_q <= 0;
Tests: T1 T2 T3
638 1/1 crc5_q <= 0;
Tests: T1 T2 T3
639 1/1 token_payload_q <= 0;
Tests: T1 T2 T3
640 1/1 addr_q <= 0;
Tests: T1 T2 T3
641 1/1 endp_q <= 0;
Tests: T1 T2 T3
642 1/1 frame_num_q <= 0;
Tests: T1 T2 T3
643 1/1 rx_data_buffer_q <= 0;
Tests: T1 T2 T3
644 1/1 rx_data_len16_q <= 0;
Tests: T1 T2 T3
645 1/1 rx_data_len_q <= 0;
Tests: T1 T2 T3
646 end else begin
647 1/1 if (link_reset_i) begin
Tests: T1 T2 T3
648 1/1 full_pid_q <= 0;
Tests: T1 T2 T3
649 1/1 crc16_q <= 0;
Tests: T1 T2 T3
650 1/1 crc5_q <= 0;
Tests: T1 T2 T3
651 1/1 token_payload_q <= 0;
Tests: T1 T2 T3
652 1/1 addr_q <= 0;
Tests: T1 T2 T3
653 1/1 endp_q <= 0;
Tests: T1 T2 T3
654 1/1 frame_num_q <= 0;
Tests: T1 T2 T3
655 1/1 rx_data_buffer_q <= 0;
Tests: T1 T2 T3
656 1/1 rx_data_len16_q <= 0;
Tests: T1 T2 T3
657 1/1 rx_data_len_q <= 0;
Tests: T1 T2 T3
658 end else begin
659 1/1 full_pid_q <= full_pid_d;
Tests: T1 T2 T3
660 1/1 crc16_q <= crc16_d;
Tests: T1 T2 T3
661 1/1 crc5_q <= crc5_d;
Tests: T1 T2 T3
662 1/1 token_payload_q <= token_payload_d;
Tests: T1 T2 T3
663 1/1 addr_q <= addr_d;
Tests: T1 T2 T3
664 1/1 endp_q <= endp_d;
Tests: T1 T2 T3
665 1/1 frame_num_q <= frame_num_d;
Tests: T1 T2 T3
666 1/1 rx_data_buffer_q <= rx_data_buffer_d;
Tests: T1 T2 T3
667 1/1 rx_data_len16_q <= rx_data_len16_d;
Tests: T1 T2 T3
668 1/1 rx_data_len_q <= rx_data_len_d;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_rx
| Total | Covered | Percent |
|---|
| Conditions | 205 | 202 | 98.54 |
| Logical | 205 | 202 | 98.54 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 73
EXPRESSION (cfg_pinflip_i ? usb_dn_i : usb_dp_i)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T49,T50 |
LINE 74
EXPRESSION (cfg_pinflip_i ? usb_dp_i : usb_dn_i)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T49,T50 |
LINE 75
EXPRESSION (usb_d_i ^ cfg_pinflip_i)
---1--- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T7,T49,T50 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T7,T49,T274 |
LINE 130
EXPRESSION (usb_d_flipped ? DJ[1:0] : DK[1:0])
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION (line_state_q == DT)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (dpair != line_state_q[1:0])
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 174
EXPRESSION (diff_state_q == DT)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 182
EXPRESSION (ddiff != diff_state_q[1:0])
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 224
EXPRESSION ((line_state_q == SE0) || ((line_state_q == DT) && (line_state_qq == SE0)))
----------1---------- ------------------------2-----------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 224
SUB-EXPRESSION (line_state_q == SE0)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 224
SUB-EXPRESSION ((line_state_q == DT) && (line_state_qq == SE0))
----------1--------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 224
SUB-EXPRESSION (line_state_q == DT)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 224
SUB-EXPRESSION (line_state_qq == SE0)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 225
EXPRESSION (cfg_use_diff_rcvr_i ? (use_se ? line_state_q : diff_state_q) : line_state_q)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 225
SUB-EXPRESSION (use_se ? line_state_q : diff_state_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 245
EXPRESSION (bit_phase_q == 2'b1)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 246
EXPRESSION (bit_phase_q == 2'd2)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 249
EXPRESSION ((line_state_rx == DT) ? 0 : ((bit_phase_q + 1)))
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 249
SUB-EXPRESSION (line_state_rx == DT)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 279
EXPRESSION (packet_valid_d & ((~packet_valid_q)))
-------1------ ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 280
EXPRESSION (((~packet_valid_d)) & packet_valid_q)
---------1--------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 285
EXPRESSION ((cfg_eop_single_bit_i && (line_history_q[1:0] == 2'b0)) || (line_history_q[3:0] == 4'b0) || bitstuff_error_q || see_preamble)
---------------------------1--------------------------- --------------2-------------- --------3------- ------4-----
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | Covered | T42,T86,T68 |
| 0 | 0 | 1 | 0 | Covered | T3,T84,T79 |
| 0 | 1 | 0 | 0 | Covered | T1,T2,T3 |
| 1 | 0 | 0 | 0 | Covered | T1,T2,T3 |
LINE 285
SUB-EXPRESSION (cfg_eop_single_bit_i && (line_history_q[1:0] == 2'b0))
----------1--------- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 285
SUB-EXPRESSION (line_history_q[1:0] == 2'b0)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 285
SUB-EXPRESSION (line_history_q[3:0] == 4'b0)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 289
EXPRESSION ((line_history_q[3:0] == 4'b1001) & ((~tx_en_i)) & ((~in_packet_q)))
----------------1--------------- ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | 1 | Covered | T1,T3,T28 |
LINE 289
SUB-EXPRESSION (line_history_q[3:0] == 4'b1001)
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 290
EXPRESSION (see_eop ? 1'b0 : (see_sop ? 1'b1 : in_packet_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 290
SUB-EXPRESSION (see_sop ? 1'b1 : in_packet_q)
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 308
EXPRESSION (((!packet_valid_q)) && (line_history_q[11:0] == 12'b011001100101))
---------1--------- ---------------------2--------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 308
SUB-EXPRESSION (line_history_q[11:0] == 12'b011001100101)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 313
EXPRESSION (packet_valid_q && see_eop)
-------1------ ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 325
EXPRESSION (line_state_valid ? ({line_history_q[9:0], line_state_rx[1:0]}) : line_history_q)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 346
EXPRESSION ((((~tx_en_i)) & line_state_valid) ? (line_state_q == DJ) : rx_idle_det_q)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 346
SUB-EXPRESSION (((~tx_en_i)) & line_state_valid)
------1----- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T28,T29 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 346
SUB-EXPRESSION (line_state_q == DJ)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 358
EXPRESSION (diff_rx_ok_i & ((~tx_en_i)) & (line_history_q[1:0] == 2'b10))
------1----- ------2----- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T28,T29 |
| 1 | 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 358
SUB-EXPRESSION (line_history_q[1:0] == 2'b10)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 381
EXPRESSION (packet_valid_q && line_state_valid)
-------1------ --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 421
EXPRESSION (dvalid_raw && ( ! (bitstuff_history_q[5:0] == 6'b111111) ))
-----1---- ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 421
SUB-EXPRESSION ( ! (bitstuff_history_q[5:0] == 6'b111111) )
-------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 421
SUB-EXPRESSION (bitstuff_history_q[5:0] == 6'b111111)
-------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 427
EXPRESSION (bitstuff_history_q == 7'b1111111)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T84,T79 |
LINE 434
EXPRESSION (bitstuff_error && dvalid_raw)
-------1------ -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T3,T84,T79 |
| 1 | 1 | Covered | T3,T84,T79 |
LINE 447
EXPRESSION (bitstuff_error_q && packet_end)
--------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T3,T84,T79 |
| 1 | 1 | Covered | T3,T84,T79 |
LINE 459
EXPRESSION (full_pid_q[4:1] == (~full_pid_q[8:5]))
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 463
EXPRESSION (dvalid && ((!pid_complete)))
---1-- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 477
EXPRESSION (crc5_q == 5'b01100)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 478
EXPRESSION (din ^ crc5_q[4])
-1- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 487
EXPRESSION (dvalid && pid_complete)
---1-- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 499
EXPRESSION (crc16_q == 16'b1000000000001101)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T28,T29 |
LINE 500
EXPRESSION (din ^ crc16_q[15])
-1- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 509
EXPRESSION (dvalid && pid_complete)
---1-- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 521
EXPRESSION (full_pid_q[2:1] == 2'b1)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 522
EXPRESSION (full_pid_q[2:1] == 2'b11)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 523
EXPRESSION (full_pid_q[2:1] == 2'b10)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 525
EXPRESSION ((packet_valid_q & pid_valid & pid_complete) && (usb_pid_e'(full_pid_q[4:1]) == UsbPidPre))
---------------------1--------------------- ---------------------2--------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T42,T86,T68 |
LINE 525
SUB-EXPRESSION (packet_valid_q & pid_valid & pid_complete)
-------1------ ----2---- ------3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | 1 | Covered | T78,T79,T80 |
| 1 | 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | 1 | Covered | T1,T3,T28 |
LINE 525
SUB-EXPRESSION (usb_pid_e'(full_pid_q[4:1]) == UsbPidPre)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T3,T28 |
LINE 530
EXPRESSION
Number Term
1 pid_valid &&
2 ((!bitstuff_error_q)) &&
3 ((pkt_is_handshake && valid_handshake_len) || (pkt_is_data && valid_data_len && crc16_valid) || (pkt_is_token && valid_token_len && crc5_valid)))
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | 1 | Covered | T1,T3,T28 |
LINE 530
SUB-EXPRESSION ((pkt_is_handshake && valid_handshake_len) || (pkt_is_data && valid_data_len && crc16_valid) || (pkt_is_token && valid_token_len && crc5_valid))
--------------------1-------------------- -----------------------2---------------------- -----------------------3-----------------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T1,T3,T28 |
| 0 | 1 | 0 | Covered | T1,T28,T29 |
| 1 | 0 | 0 | Covered | T1,T3,T28 |
LINE 530
SUB-EXPRESSION (pkt_is_handshake && valid_handshake_len)
--------1------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T79,T82,T83 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 530
SUB-EXPRESSION (pkt_is_data && valid_data_len && crc16_valid)
-----1----- -------2------ -----3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T5,T107,T275 |
| 1 | 1 | 0 | Covered | T1,T28,T29 |
| 1 | 1 | 1 | Covered | T1,T28,T29 |
LINE 530
SUB-EXPRESSION (pkt_is_token && valid_token_len && crc5_valid)
------1----- -------2------- -----3----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T29,T30,T42 |
| 1 | 0 | 1 | Covered | T3,T29,T42 |
| 1 | 1 | 0 | Covered | T79,T76,T82 |
| 1 | 1 | 1 | Covered | T1,T3,T28 |
LINE 536
EXPRESSION (pkt_is_token & packet_end & ((!crc5_valid)))
------1----- -----2---- -------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | 1 | Covered | T1,T3,T28 |
| 1 | 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | 1 | Covered | T84,T79,T76 |
LINE 537
EXPRESSION (pkt_is_data & packet_end & ((!crc16_valid)))
-----1----- -----2---- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | 1 | Covered | T1,T3,T28 |
| 1 | 1 | 0 | Covered | T1,T28,T29 |
| 1 | 1 | 1 | Covered | T3,T32,T38 |
LINE 540
EXPRESSION (((!pid_valid)) && packet_end)
-------1------ -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T78,T79,T80 |
LINE 558
EXPRESSION (dvalid && pid_complete && pkt_is_token && ((!token_payload_done)))
---1-- ------2----- ------3----- -----------4-----------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | 1 | 1 | Covered | T29,T30,T42 |
| 1 | 1 | 0 | 1 | Covered | T1,T3,T28 |
| 1 | 1 | 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | 1 | 1 | Covered | T1,T3,T28 |
LINE 569
EXPRESSION (token_payload_done && pkt_is_token)
---------1-------- ------2-----
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 598
EXPRESSION (packet_start || rx_data_buffer_full)
------1----- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T3,T28 |
LINE 602
EXPRESSION (dvalid && pid_complete && pkt_is_data)
---1-- ------2----- -----3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | 1 | Covered | T1,T3,T28 |
| 1 | 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | 1 | Covered | T1,T3,T28 |
LINE 613
EXPRESSION (rx_data_len16_q & ((~|rx_data_len_q)))
-------1------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T28,T29 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 614
EXPRESSION (rx_data_len16_q & ((~|rx_data_len_q[2:0])))
-------1------- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T28,T29 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 625
EXPRESSION (dvalid && pid_complete)
---1-- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T3,T28 |
LINE 626
EXPRESSION (rx_data_len16_q | ((&rx_data_len_q)))
-------1------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T3,T28 |
| 0 | 1 | Covered | T1,T3,T28 |
| 1 | 0 | Covered | T1,T28,T29 |
Branch Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_rx
| Line No. | Total | Covered | Percent |
| Branches |
|
93 |
93 |
100.00 |
| TERNARY |
73 |
2 |
2 |
100.00 |
| TERNARY |
74 |
2 |
2 |
100.00 |
| TERNARY |
225 |
3 |
3 |
100.00 |
| TERNARY |
249 |
2 |
2 |
100.00 |
| TERNARY |
290 |
3 |
3 |
100.00 |
| TERNARY |
325 |
2 |
2 |
100.00 |
| TERNARY |
346 |
2 |
2 |
100.00 |
| IF |
125 |
3 |
3 |
100.00 |
| IF |
135 |
3 |
3 |
100.00 |
| IF |
156 |
3 |
3 |
100.00 |
| IF |
174 |
3 |
3 |
100.00 |
| IF |
252 |
3 |
3 |
100.00 |
| IF |
294 |
2 |
2 |
100.00 |
| IF |
302 |
5 |
5 |
100.00 |
| IF |
329 |
3 |
3 |
100.00 |
| IF |
350 |
2 |
2 |
100.00 |
| CASE |
373 |
5 |
5 |
100.00 |
| IF |
381 |
6 |
6 |
100.00 |
| IF |
399 |
3 |
3 |
100.00 |
| IF |
409 |
3 |
3 |
100.00 |
| IF |
432 |
3 |
3 |
100.00 |
| IF |
440 |
2 |
2 |
100.00 |
| IF |
463 |
3 |
3 |
100.00 |
| IF |
483 |
2 |
2 |
100.00 |
| IF |
487 |
2 |
2 |
100.00 |
| IF |
505 |
2 |
2 |
100.00 |
| IF |
509 |
2 |
2 |
100.00 |
| IF |
554 |
2 |
2 |
100.00 |
| IF |
558 |
2 |
2 |
100.00 |
| IF |
569 |
2 |
2 |
100.00 |
| IF |
598 |
2 |
2 |
100.00 |
| IF |
602 |
2 |
2 |
100.00 |
| IF |
621 |
2 |
2 |
100.00 |
| IF |
625 |
2 |
2 |
100.00 |
| IF |
635 |
3 |
3 |
100.00 |
73 assign usb_dp_flipped = cfg_pinflip_i ? usb_dn_i : usb_dp_i;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T49,T50 |
| 0 |
Covered |
T1,T2,T3 |
74 assign usb_dn_flipped = cfg_pinflip_i ? usb_dp_i : usb_dn_i;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T49,T50 |
| 0 |
Covered |
T1,T2,T3 |
225 assign line_state_rx = cfg_use_diff_rcvr_i ? (use_se ? line_state_q : diff_state_q) :
-1- -2-
==>
==> ==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
1 |
Covered |
T1,T2,T3 |
| 1 |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
Covered |
T1,T2,T3 |
249 assign bit_phase_d = (line_state_rx == DT) ? 0 : bit_phase_q + 1;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
290 assign in_packet_d = see_eop ? 1'b0 :
-1-
==>
291 see_sop ? 1'b1 : in_packet_q;
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T3,T28 |
| 0 |
0 |
Covered |
T1,T2,T3 |
325 assign line_history_d = line_state_valid ? {line_history_q[9:0], line_state_rx[1:0]} :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
346 assign rx_idle_det_d = (~tx_en_i & line_state_valid) ? (line_state_q == DJ) : rx_idle_det_q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
125 if (tx_en_i) begin
-1-
126 dpair = DJ[1:0]; // J
==>
127 ddiff = DJ[1:0]; // J
128 end else begin
129 dpair = {usb_dp_flipped, usb_dn_flipped};
130 ddiff = usb_d_flipped ? DJ[1:0] : DK[1:0]; // equiv to {usb_d_i, ~usb_d_i}
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T28,T29 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
135 if (!rst_ni) begin
-1-
136 line_state_q <= SE0;
==>
137 line_state_qq <= SE0;
138 diff_state_q <= SE0;
139 end else begin
140 if (link_reset_i) begin
-2-
141 line_state_q <= SE0;
==>
142 line_state_qq <= SE0;
143 diff_state_q <= SE0;
144 end else begin
145 line_state_q <= line_state_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
156 if (line_state_q == DT) begin
-1-
157 // if we are in a transition state, then we can sample the pair and
158 // move to the next corresponding line state
159 line_state_d = {1'b0, dpair};
==>
160
161 end else begin
162 // if we are in a valid line state and the value of the pair changes,
163 // then we need to move to the transition state
164 if (dpair != line_state_q[1:0]) begin
-2-
165 line_state_d = DT;
==>
166 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
174 if (diff_state_q == DT) begin
-1-
175 // if we are in a transition state, then we can sample the diff input and
176 // move to the next corresponding line state
177 diff_state_d = {1'b0, ddiff};
==>
178
179 end else begin
180 // if we are in a valid line state and the value of the diff input changes,
181 // then we need to move to the transition state
182 if (ddiff != diff_state_q[1:0]) begin
-2-
183 diff_state_d = DT;
==>
184 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
252 if (!rst_ni) begin
-1-
253 bit_phase_q <= 0;
==>
254 end else begin
255 if (link_reset_i) begin
-2-
256 bit_phase_q <= 0;
==>
257 end else begin
258 bit_phase_q <= bit_phase_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
294 if (!rst_ni) begin
-1-
295 in_packet_q <= 1'b0;
==>
296 end else begin
297 in_packet_q <= in_packet_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
302 if (line_state_valid) begin
-1-
303 // If the differential K and J symbols are not valid, reject the
304 // containing packet as invalid.
305 if (~diff_rx_ok_i) begin
-2-
306 packet_valid_d = 0;
==>
307 // check for packet start: KJKJKK, we use the last 6 bits
308 end else if (!packet_valid_q && line_history_q[11:0] == 12'b011001100101) begin
-3-
309 packet_valid_d = 1;
==>
310 end
311
312 // check for packet end: SE0 SE0
313 else if (packet_valid_q && see_eop) begin
-4-
314 packet_valid_d = 0;
==>
315
316 end else begin
317 packet_valid_d = packet_valid_q;
==>
318 end
319 end else begin
320 packet_valid_d = packet_valid_q;
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
1 |
- |
- |
Covered |
T7,T22,T8 |
| 1 |
0 |
1 |
- |
Covered |
T1,T3,T28 |
| 1 |
0 |
0 |
1 |
Covered |
T1,T3,T28 |
| 1 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
- |
Covered |
T1,T2,T3 |
329 if (!rst_ni) begin
-1-
330 packet_valid_q <= 0;
==>
331 line_history_q <= 12'b101010101010; // all K
332 end else begin
333 if (link_reset_i) begin
-2-
334 packet_valid_q <= 0;
==>
335 line_history_q <= 12'b101010101010; // all K
336 end else begin
337 packet_valid_q <= packet_valid_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
350 if (!rst_ni) begin
-1-
351 rx_idle_det_q <= 1'b0;
==>
352 end else begin
353 rx_idle_det_q <= rx_idle_det_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
373 unique case (line_history_q[3:0])
-1-
374 4'b0101 : din = 1;
==>
375 4'b0110 : din = 0;
==>
376 4'b1001 : din = 0;
==>
377 4'b1010 : din = 1;
==>
378 default : din = 0;
==>
Branches:
| -1- | Status | Tests |
| 4'b0101 |
Covered |
T1,T3,T28 |
| 4'b0110 |
Covered |
T1,T3,T28 |
| 4'b1001 |
Covered |
T1,T3,T28 |
| 4'b1010 |
Covered |
T1,T2,T3 |
| default |
Covered |
T1,T2,T3 |
381 if (packet_valid_q && line_state_valid) begin
-1-
382 unique case (line_history_q[3:0])
-2-
383 4'b0101 : dvalid_raw = 1;
==>
384 4'b0110 : dvalid_raw = 1;
==>
385 4'b1001 : dvalid_raw = 1;
==>
386 4'b1010 : dvalid_raw = 1;
==>
387 default : dvalid_raw = 0;
==>
388 endcase
389 end else begin
390 dvalid_raw = 0;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
4'b0101 |
Covered |
T1,T3,T28 |
| 1 |
4'b0110 |
Covered |
T1,T3,T28 |
| 1 |
4'b1001 |
Covered |
T1,T3,T28 |
| 1 |
4'b1010 |
Covered |
T1,T3,T28 |
| 1 |
default |
Covered |
T1,T3,T28 |
| 0 |
- |
Covered |
T1,T2,T3 |
399 if (packet_end) begin
-1-
400 bitstuff_history_d = '0;
==>
401 end else if (dvalid_raw) begin
-2-
402 bitstuff_history_d = {bitstuff_history_q[5:0], din};
==>
403 end else begin
404 bitstuff_history_d = bitstuff_history_q;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T3,T28 |
| 0 |
1 |
Covered |
T1,T3,T28 |
| 0 |
0 |
Covered |
T1,T2,T3 |
409 if (!rst_ni) begin
-1-
410 bitstuff_history_q <= 0;
==>
411 end else begin
412 if (link_reset_i) begin
-2-
413 bitstuff_history_q <= 0;
==>
414 end else begin
415 bitstuff_history_q <= bitstuff_history_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
432 if (packet_start) begin
-1-
433 bitstuff_error_d = 0;
==>
434 end else if (bitstuff_error && dvalid_raw) begin
-2-
435 bitstuff_error_d = 1;
==>
436 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T3,T28 |
| 0 |
1 |
Covered |
T3,T84,T79 |
| 0 |
0 |
Covered |
T1,T2,T3 |
440 if (!rst_ni) begin
-1-
441 bitstuff_error_q <= 0;
==>
442 end else begin
443 bitstuff_error_q <= bitstuff_error_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
463 if (dvalid && !pid_complete) begin
-1-
464 full_pid_d = {din, full_pid_q[8:1]};
==>
465 end else if (packet_start) begin
-2-
466 full_pid_d = 9'b100000000;
==>
467 end else begin
468 full_pid_d = full_pid_q;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T3,T28 |
| 0 |
1 |
Covered |
T1,T3,T28 |
| 0 |
0 |
Covered |
T1,T2,T3 |
483 if (packet_start) begin
-1-
484 crc5_d = 5'b11111;
==>
485 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
487 if (dvalid && pid_complete) begin
-1-
488 crc5_d = {crc5_q[3:0], 1'b0} ^ ({5{crc5_invert}} & 5'b00101);
==>
489 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
505 if (packet_start) begin
-1-
506 crc16_d = 16'b1111111111111111;
==>
507 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
509 if (dvalid && pid_complete) begin
-1-
510 crc16_d = {crc16_q[14:0], 1'b0} ^ ({16{crc16_invert}} & 16'b1000000000000101);
==>
511 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
554 if (packet_start) begin
-1-
555 token_payload_d = 12'b100000000000;
==>
556 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
558 if (dvalid && pid_complete && pkt_is_token && !token_payload_done) begin
-1-
559 token_payload_d = {din, token_payload_q[11:1]};
==>
560 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
569 if (token_payload_done && pkt_is_token) begin
-1-
570 addr_d = token_payload_q[7:1];
==>
571 endp_d = token_payload_q[11:8];
572 frame_num_d = token_payload_q[11:1];
573 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
598 if (packet_start || rx_data_buffer_full) begin
-1-
599 rx_data_buffer_d = 9'b100000000;
==>
600 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
602 if (dvalid && pid_complete && pkt_is_data) begin
-1-
603 rx_data_buffer_d = {din, rx_data_buffer_q[8:1]};
==>
604 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
621 if (packet_start) begin
-1-
622 rx_data_len16_d = 1'b0;
==>
623 rx_data_len_d = 4'h0;
624 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
625 if (dvalid && pid_complete) begin
-1-
626 rx_data_len16_d = rx_data_len16_q | &rx_data_len_q;
==>
627 rx_data_len_d = rx_data_len_q + 4'h1;
628 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T3,T28 |
| 0 |
Covered |
T1,T2,T3 |
635 if (!rst_ni) begin
-1-
636 full_pid_q <= 0;
==>
637 crc16_q <= 0;
638 crc5_q <= 0;
639 token_payload_q <= 0;
640 addr_q <= 0;
641 endp_q <= 0;
642 frame_num_q <= 0;
643 rx_data_buffer_q <= 0;
644 rx_data_len16_q <= 0;
645 rx_data_len_q <= 0;
646 end else begin
647 if (link_reset_i) begin
-2-
648 full_pid_q <= 0;
==>
649 crc16_q <= 0;
650 crc5_q <= 0;
651 token_payload_q <= 0;
652 addr_q <= 0;
653 endp_q <= 0;
654 frame_num_q <= 0;
655 rx_data_buffer_q <= 0;
656 rx_data_len16_q <= 0;
657 rx_data_len_q <= 0;
658 end else begin
659 full_pid_q <= full_pid_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |