Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9607316	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10231265

1

T1

9

T2

6

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19209764	1			T1	8		T2	8		T3	3
values[0x0]	313994	1			T1	4		T2	4		T3	4
values[0x1]	314823	1			T1	3		T2	5		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7640811	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

12197770

1

T1

11

T2

7

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	58991	1			T7	2		T18	2		T20	1
valid_sources[0x01]	57711	1			T37	2		T7	1		T18	2
valid_sources[0x02]	70074	1			T7	3		T18	3		T30	47
valid_sources[0x03]	60108	1			T18	2		T20	1		T30	73
valid_sources[0x04]	77255	1			T18	1		T30	64		T61	11
valid_sources[0x05]	132278	1			T7	1		T17	9		T18	3
valid_sources[0x06]	57613	1			T37	1		T7	1		T30	48
valid_sources[0x07]	58677	1			T18	1		T20	1		T30	80
valid_sources[0x08]	58532	1			T18	1		T20	2		T30	68
valid_sources[0x09]	58336	1			T7	2		T18	1		T20	2
valid_sources[0x0a]	69377	1			T7	2		T18	2		T30	53
valid_sources[0x0b]	76260	1			T18	3		T30	49		T61	25
valid_sources[0x0c]	58167	1			T7	1		T30	76		T31	4
valid_sources[0x0d]	59580	1			T7	3		T18	1		T24	1
valid_sources[0x0e]	121695	1			T1	6		T18	1		T30	54
valid_sources[0x0f]	107477	1			T30	52		T61	6		T63	2
valid_sources[0x10]	57294	1			T7	1		T17	2		T18	1
valid_sources[0x11]	78995	1			T7	3		T18	1		T20	1
valid_sources[0x12]	138761	1			T17	20		T30	61		T31	1
valid_sources[0x13]	59819	1			T7	1		T30	37		T31	6
valid_sources[0x14]	66920	1			T7	1		T18	3		T21	1
valid_sources[0x15]	128687	1			T37	2		T18	2		T24	1
valid_sources[0x16]	121085	1			T7	1		T18	1		T30	62
valid_sources[0x17]	57710	1			T18	1		T24	2		T30	60
valid_sources[0x18]	59340	1			T7	4		T18	1		T30	66
valid_sources[0x19]	59727	1			T7	3		T30	61		T61	16
valid_sources[0x1a]	59337	1			T7	2		T18	3		T30	67
valid_sources[0x1b]	58427	1			T7	2		T18	2		T20	1
valid_sources[0x1c]	77971	1			T7	1		T30	71		T61	23
valid_sources[0x1d]	59169	1			T18	1		T30	61		T35	1
valid_sources[0x1e]	174772	1			T7	3		T18	1		T20	1
valid_sources[0x1f]	57477	1			T37	1		T7	2		T30	70
valid_sources[0x20]	80757	1			T7	4		T18	2		T20	1
valid_sources[0x21]	59148	1			T30	60		T61	15		T63	7
valid_sources[0x22]	79677	1			T7	1		T18	2		T30	47
valid_sources[0x23]	58464	1			T7	1		T17	3		T18	1
valid_sources[0x24]	59752	1			T18	1		T22	46		T30	49
valid_sources[0x25]	64344	1			T7	1		T30	60		T61	7
valid_sources[0x26]	59585	1			T7	1		T24	5		T30	59
valid_sources[0x27]	57727	1			T18	1		T20	1		T30	50
valid_sources[0x28]	72943	1			T7	1		T18	1		T30	68
valid_sources[0x29]	57966	1			T37	2		T18	2		T30	60
valid_sources[0x2a]	58163	1			T7	3		T18	1		T30	67
valid_sources[0x2b]	176531	1			T7	1		T17	17		T18	1
valid_sources[0x2c]	80846	1			T37	1		T7	4		T24	2
valid_sources[0x2d]	58997	1			T7	1		T17	13		T18	3
valid_sources[0x2e]	126555	1			T18	1		T30	50		T61	12
valid_sources[0x2f]	58792	1			T7	2		T30	69		T61	16
valid_sources[0x30]	57902	1			T7	2		T18	2		T30	47
valid_sources[0x31]	59165	1			T37	1		T30	49		T61	8
valid_sources[0x32]	71384	1			T7	2		T18	1		T24	6
valid_sources[0x33]	85410	1			T7	1		T18	2		T30	68
valid_sources[0x34]	79746	1			T37	1		T18	2		T30	76
valid_sources[0x35]	228296	1			T30	56		T61	22		T63	4
valid_sources[0x36]	58244	1			T7	1		T18	1		T30	70
valid_sources[0x37]	58179	1			T7	1		T30	67		T61	4
valid_sources[0x38]	212577	1			T30	44		T61	10		T63	3
valid_sources[0x39]	60631	1			T7	2		T18	1		T30	42
valid_sources[0x3a]	58326	1			T7	1		T18	1		T30	72
valid_sources[0x3b]	57941	1			T7	1		T18	3		T24	1
valid_sources[0x3c]	57499	1			T7	1		T20	1		T30	68
valid_sources[0x3d]	107148	1			T20	1		T30	60		T61	14
valid_sources[0x3e]	76476	1			T7	5		T18	2		T20	2
valid_sources[0x3f]	57850	1			T7	1		T30	36		T61	12
valid_sources[0x40]	59276	1			T18	3		T30	59		T61	24
valid_sources[0x41]	57532	1			T7	3		T18	1		T30	61
valid_sources[0x42]	59610	1			T7	3		T18	1		T30	64
valid_sources[0x43]	57235	1			T7	2		T18	2		T20	2
valid_sources[0x44]	75948	1			T21	1		T24	1		T30	61
valid_sources[0x45]	59535	1			T30	67		T61	26		T63	3
valid_sources[0x46]	59138	1			T18	2		T30	61		T61	7
valid_sources[0x47]	56956	1			T18	2		T20	1		T30	61
valid_sources[0x48]	141110	1			T7	2		T18	2		T20	1
valid_sources[0x49]	108518	1			T18	2		T30	57		T61	13
valid_sources[0x4a]	58231	1			T7	1		T18	1		T22	5
valid_sources[0x4b]	57954	1			T20	1		T21	1		T30	42
valid_sources[0x4c]	57764	1			T7	1		T18	3		T20	1
valid_sources[0x4d]	75565	1			T30	53		T106	1		T61	10
valid_sources[0x4e]	57899	1			T30	59		T61	8		T63	7
valid_sources[0x4f]	75473	1			T7	1		T18	2		T20	2
valid_sources[0x50]	58824	1			T7	2		T18	2		T30	66
valid_sources[0x51]	57684	1			T30	67		T31	4		T61	6
valid_sources[0x52]	57555	1			T7	4		T18	2		T30	62
valid_sources[0x53]	58818	1			T30	63		T61	21		T63	2
valid_sources[0x54]	59074	1			T7	1		T18	1		T30	74
valid_sources[0x55]	58613	1			T7	1		T17	9		T30	66
valid_sources[0x56]	59044	1			T7	3		T17	3		T30	43
valid_sources[0x57]	172925	1			T18	4		T20	2		T30	59
valid_sources[0x58]	59272	1			T7	1		T18	1		T20	1
valid_sources[0x59]	61155	1			T7	2		T30	53		T61	2
valid_sources[0x5a]	57228	1			T17	4		T18	1		T30	49
valid_sources[0x5b]	58203	1			T7	2		T30	56		T61	14
valid_sources[0x5c]	57331	1			T30	59		T61	21		T63	5
valid_sources[0x5d]	134271	1			T20	1		T24	6		T30	51
valid_sources[0x5e]	76718	1			T2	17		T20	1		T30	56
valid_sources[0x5f]	76771	1			T18	3		T24	2		T30	63
valid_sources[0x60]	75075	1			T18	2		T20	1		T30	87
valid_sources[0x61]	80328	1			T7	4		T18	2		T30	66
valid_sources[0x62]	61096	1			T18	2		T30	79		T61	14
valid_sources[0x63]	186322	1			T3	12		T7	2		T18	2
valid_sources[0x64]	57716	1			T30	68		T61	18		T63	7
valid_sources[0x65]	98136	1			T18	1		T19	11		T30	68
valid_sources[0x66]	74419	1			T18	1		T30	60		T61	9
valid_sources[0x67]	58980	1			T7	1		T18	3		T30	69
valid_sources[0x68]	56673	1			T18	4		T20	1		T30	71
valid_sources[0x69]	58011	1			T7	1		T18	3		T30	56
valid_sources[0x6a]	122442	1			T7	3		T18	1		T30	57
valid_sources[0x6b]	99722	1			T7	2		T18	1		T30	59
valid_sources[0x6c]	58524	1			T7	2		T18	1		T30	58
valid_sources[0x6d]	70889	1			T7	1		T18	1		T20	1
valid_sources[0x6e]	67652	1			T30	65		T61	15		T63	2
valid_sources[0x6f]	57444	1			T18	3		T30	66		T61	7
valid_sources[0x70]	58376	1			T7	2		T18	1		T30	56
valid_sources[0x71]	75422	1			T18	4		T30	59		T61	18
valid_sources[0x72]	65614	1			T18	1		T30	63		T62	1
valid_sources[0x73]	57182	1			T7	1		T30	74		T61	15
valid_sources[0x74]	61479	1			T17	8		T18	3		T30	56
valid_sources[0x75]	75760	1			T7	3		T24	3		T30	80
valid_sources[0x76]	82820	1			T7	1		T18	1		T30	63
valid_sources[0x77]	88618	1			T7	1		T17	4		T18	2
valid_sources[0x78]	59179	1			T18	3		T30	54		T61	11
valid_sources[0x79]	58864	1			T7	1		T18	1		T30	70
valid_sources[0x7a]	57253	1			T18	3		T30	59		T61	8
valid_sources[0x7b]	121057	1			T7	1		T30	54		T61	11
valid_sources[0x7c]	58143	1			T7	1		T18	1		T30	60
valid_sources[0x7d]	57682	1			T37	1		T18	1		T30	69
valid_sources[0x7e]	67508	1			T7	1		T18	1		T30	51
valid_sources[0x7f]	57973	1			T20	1		T30	80		T61	6
valid_sources[0x80]	81972	1			T7	1		T30	40		T31	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9723168

1

T1

5

T2

2

T3

1

values[0x0]

all_enables

biggest_size

262683

1

T1

4

T2

2

T3

4

values[0x1]

all_enables

biggest_size

245414

1

T2

2

T37

3

T7

5