Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

9622058

1

T1

6

T2

11

T3

7

full_word

10232283

1

T1

9

T2

6

T3

5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	19854021	1			T1	15		T2	17		T3	12
auto[TlIntgErrCmd]	115	1			T227	12		T228	4		T229	4
auto[TlIntgErrData]	111	1			T227	2		T228	2		T229	7
auto[TlIntgErrBoth]	94	1			T227	6		T228	4		T229	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19211565

1

T1

8

T2

8

T3

3

auto[1]

642776

1

T1

7

T2

9

T3

9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9488084	1			T1	3		T2	6		T3	2
auto[TlIntgErrNone]	partial	auto[1]	133677	1			T1	3		T2	5		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	9723323	1			T1	5		T2	2		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	508937	1			T1	4		T2	4		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	54	1			T227	5		T228	2		T229	3
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T227	6		T228	2		T229	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T486	1		T487	1		T488	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T227	1		T482	1		T489	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T228	2		T229	3		T275	4
auto[TlIntgErrData]	partial	auto[1]	46	1			T227	2		T229	4		T275	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T490	1		T489	3		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T484	1		T491	1		T490	2
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T227	3		T228	2		T229	5
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T227	3		T228	1		T229	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T229	1		T492	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T228	1		T491	1		T486	1