Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	573261852	11736	0	0
ep_in_enable_rd_A	573261852	2670	0	0
ep_out_enable_rd_A	573261852	2955	0	0
in_iso_rd_A	573261852	3232	0	0
intr_enable_rd_A	573261852	4385	0	0
out_iso_rd_A	573261852	2822	0	0
phy_config_rd_A	573261852	2194	0	0
phy_pins_drive_rd_A	573261852	2848	0	0
rxenable_setup_rd_A	573261852	2834	0	0
set_nak_out_rd_A	573261852	2781	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	573261852	11736	0	0
T184	6782	298	0	0
T185	6374	11	0	0
T186	6050	16	0	0
T219	10723	918	0	0
T226	12388	778	0	0
T227	48348	4	0	0
T228	22274	3	0	0
T235	9602	562	0	0
T239	6859	4	0	0
T243	6686	7	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	573261852	2670	0	0
T228	22274	178	0	0
T231	10292	105	0	0
T243	6686	10	0	0
T259	9605	2	0	0
T261	6156	4	0	0
T263	41175	109	0	0
T274	85463	315	0	0
T275	38827	260	0	0
T276	7985	9	0	0
T277	10908	2	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	573261852	2955	0	0
T228	22274	300	0	0
T231	10292	90	0	0
T243	6686	4	0	0
T259	9605	2	0	0
T261	6156	3	0	0
T263	41175	129	0	0
T274	85463	274	0	0
T275	38827	281	0	0
T276	7985	66	0	0
T277	10908	23	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	573261852	3232	0	0
T228	22274	252	0	0
T231	10292	127	0	0
T243	6686	6	0	0
T259	9605	6	0	0
T261	6156	1	0	0
T263	41175	98	0	0
T274	85463	302	0	0
T275	38827	303	0	0
T276	7985	82	0	0
T277	10908	18	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	573261852	4385	0	0
T195	2035	10	0	0
T198	1721	19	0	0
T228	22274	320	0	0
T231	10292	114	0	0
T243	6686	1	0	0
T259	9605	7	0	0
T261	6156	7	0	0
T274	85463	262	0	0
T275	38827	399	0	0
T278	1878	13	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	573261852	2822	0	0
T228	22274	218	0	0
T231	10292	106	0	0
T243	6686	6	0	0
T259	9605	8	0	0
T261	6156	2	0	0
T263	41175	100	0	0
T274	85463	289	0	0
T275	38827	222	0	0
T276	7985	64	0	0
T277	10908	17	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	573261852	2194	0	0
T228	22274	140	0	0
T231	10292	79	0	0
T243	6686	17	0	0
T259	9605	2	0	0
T261	6156	10	0	0
T263	41175	113	0	0
T274	85463	201	0	0
T275	38827	125	0	0
T276	7985	31	0	0
T277	10908	5	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	573261852	2848	0	0
T228	22274	264	0	0
T231	10292	105	0	0
T243	6686	3	0	0
T259	9605	5	0	0
T261	6156	3	0	0
T263	41175	92	0	0
T274	85463	260	0	0
T275	38827	181	0	0
T276	7985	43	0	0
T277	10908	9	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	573261852	2834	0	0
T228	22274	206	0	0
T231	10292	99	0	0
T243	6686	4	0	0
T261	6156	16	0	0
T263	41175	101	0	0
T274	85463	251	0	0
T275	38827	210	0	0
T276	7985	47	0	0
T277	10908	37	0	0
T279	7970	47	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	573261852	2781	0	0
T228	22274	352	0	0
T231	10292	117	0	0
T243	6686	6	0	0
T259	9605	6	0	0
T261	6156	6	0	0
T263	41175	114	0	0
T274	85463	195	0	0
T275	38827	192	0	0
T276	7985	87	0	0
T277	10908	21	0	0