Line Coverage for Instance : tb.dut.usbdev_avsetupfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T20 T23 T24
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T20 T23 T24
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 assign rdata_o = empty ? Width'(0) : rdata_int;
139 end else begin : gen_no_output_zero
140 1/1 assign rdata_o = rdata_int;
Tests: T20 T23 T24
Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo
| Total | Covered | Percent |
|---|
| Conditions | 11 | 10 | 90.91 |
| Logical | 11 | 10 | 90.91 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T23,T4,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T20,T23,T24 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T84 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T20,T23,T24 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T20,T23,T24 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T61,T4,T5 |
Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T23,T24 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
130041712 |
0 |
0 |
| T4 |
0 |
143974 |
0 |
0 |
| T5 |
0 |
183942 |
0 |
0 |
| T20 |
62175 |
56404 |
0 |
0 |
| T21 |
1641 |
0 |
0 |
0 |
| T22 |
38148 |
0 |
0 |
0 |
| T23 |
7815 |
1428 |
0 |
0 |
| T24 |
35418 |
22172 |
0 |
0 |
| T30 |
40129 |
0 |
0 |
0 |
| T31 |
24235 |
0 |
0 |
0 |
| T32 |
11871 |
0 |
0 |
0 |
| T33 |
6980 |
0 |
0 |
0 |
| T41 |
199294 |
0 |
0 |
0 |
| T43 |
0 |
568 |
0 |
0 |
| T44 |
0 |
575 |
0 |
0 |
| T45 |
0 |
570 |
0 |
0 |
| T61 |
0 |
138137 |
0 |
0 |
| T83 |
0 |
580 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
571139677 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
571139677 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
571139677 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
130041712 |
0 |
0 |
| T4 |
0 |
143974 |
0 |
0 |
| T5 |
0 |
183942 |
0 |
0 |
| T20 |
62175 |
56404 |
0 |
0 |
| T21 |
1641 |
0 |
0 |
0 |
| T22 |
38148 |
0 |
0 |
0 |
| T23 |
7815 |
1428 |
0 |
0 |
| T24 |
35418 |
22172 |
0 |
0 |
| T30 |
40129 |
0 |
0 |
0 |
| T31 |
24235 |
0 |
0 |
0 |
| T32 |
11871 |
0 |
0 |
0 |
| T33 |
6980 |
0 |
0 |
0 |
| T41 |
199294 |
0 |
0 |
0 |
| T43 |
0 |
568 |
0 |
0 |
| T44 |
0 |
575 |
0 |
0 |
| T45 |
0 |
570 |
0 |
0 |
| T61 |
0 |
138137 |
0 |
0 |
| T83 |
0 |
580 |
0 |
0 |
Line Coverage for Instance : tb.dut.usbdev_avoutfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T1 T2 T3
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T1 T2 T3
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 assign rdata_o = empty ? Width'(0) : rdata_int;
139 end else begin : gen_no_output_zero
140 1/1 assign rdata_o = rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.usbdev_avoutfifo
| Total | Covered | Percent |
|---|
| Conditions | 11 | 10 | 90.91 |
| Logical | 11 | 10 | 90.91 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T37,T23,T4 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T37,T57,T58 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T2,T7 |
Branch Coverage for Instance : tb.dut.usbdev_avoutfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.usbdev_avoutfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
276739317 |
0 |
0 |
| T1 |
7880 |
660 |
0 |
0 |
| T2 |
10360 |
2159 |
0 |
0 |
| T3 |
7739 |
1432 |
0 |
0 |
| T7 |
553937 |
1284 |
0 |
0 |
| T8 |
717299 |
0 |
0 |
0 |
| T17 |
22464 |
9170 |
0 |
0 |
| T18 |
49517 |
22034 |
0 |
0 |
| T19 |
7027 |
993 |
0 |
0 |
| T20 |
62175 |
55786 |
0 |
0 |
| T22 |
0 |
13609 |
0 |
0 |
| T37 |
9175 |
904 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
571139677 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
571139677 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
571139677 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
276739317 |
0 |
0 |
| T1 |
7880 |
660 |
0 |
0 |
| T2 |
10360 |
2159 |
0 |
0 |
| T3 |
7739 |
1432 |
0 |
0 |
| T7 |
553937 |
1284 |
0 |
0 |
| T8 |
717299 |
0 |
0 |
0 |
| T17 |
22464 |
9170 |
0 |
0 |
| T18 |
49517 |
22034 |
0 |
0 |
| T19 |
7027 |
993 |
0 |
0 |
| T20 |
62175 |
55786 |
0 |
0 |
| T22 |
0 |
13609 |
0 |
0 |
| T37 |
9175 |
904 |
0 |
0 |
Line Coverage for Instance : tb.dut.usbdev_rxfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T1 T2 T7
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T1 T2 T7
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.usbdev_rxfifo
| Total | Covered | Percent |
|---|
| Conditions | 12 | 11 | 91.67 |
| Logical | 12 | 11 | 91.67 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T47,T48,T49 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T1,T2,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T2,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T1,T2,T7 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T7,T17 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T7 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.usbdev_rxfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T7 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T7 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.usbdev_rxfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
42325355 |
0 |
0 |
| T1 |
7880 |
109 |
0 |
0 |
| T2 |
10360 |
1101 |
0 |
0 |
| T3 |
7739 |
0 |
0 |
0 |
| T7 |
553937 |
108 |
0 |
0 |
| T8 |
717299 |
0 |
0 |
0 |
| T17 |
22464 |
775 |
0 |
0 |
| T18 |
49517 |
725 |
0 |
0 |
| T19 |
7027 |
0 |
0 |
0 |
| T20 |
62175 |
0 |
0 |
0 |
| T22 |
0 |
1135 |
0 |
0 |
| T31 |
0 |
9772 |
0 |
0 |
| T32 |
0 |
2959 |
0 |
0 |
| T35 |
0 |
89 |
0 |
0 |
| T36 |
0 |
2140 |
0 |
0 |
| T37 |
9175 |
0 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
571139677 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
571139677 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
571139677 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
42325355 |
0 |
0 |
| T1 |
7880 |
109 |
0 |
0 |
| T2 |
10360 |
1101 |
0 |
0 |
| T3 |
7739 |
0 |
0 |
0 |
| T7 |
553937 |
108 |
0 |
0 |
| T8 |
717299 |
0 |
0 |
0 |
| T17 |
22464 |
775 |
0 |
0 |
| T18 |
49517 |
725 |
0 |
0 |
| T19 |
7027 |
0 |
0 |
0 |
| T20 |
62175 |
0 |
0 |
0 |
| T22 |
0 |
1135 |
0 |
0 |
| T31 |
0 |
9772 |
0 |
0 |
| T32 |
0 |
2959 |
0 |
0 |
| T35 |
0 |
89 |
0 |
0 |
| T36 |
0 |
2140 |
0 |
0 |
| T37 |
9175 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
20149285 |
0 |
0 |
| T1 |
7880 |
15 |
0 |
0 |
| T2 |
10360 |
17 |
0 |
0 |
| T3 |
7739 |
12 |
0 |
0 |
| T7 |
553937 |
296 |
0 |
0 |
| T8 |
717299 |
943 |
0 |
0 |
| T17 |
22464 |
155 |
0 |
0 |
| T18 |
49517 |
302 |
0 |
0 |
| T19 |
7027 |
11 |
0 |
0 |
| T20 |
62175 |
70 |
0 |
0 |
| T37 |
9175 |
22 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
572936531 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
572936531 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
572936531 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
3724 |
3724 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T20 |
1 |
1 |
0 |
0 |
| T37 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
28169372 |
0 |
0 |
| T1 |
7880 |
54 |
0 |
0 |
| T2 |
10360 |
17 |
0 |
0 |
| T3 |
7739 |
12 |
0 |
0 |
| T7 |
553937 |
296 |
0 |
0 |
| T8 |
717299 |
943 |
0 |
0 |
| T17 |
22464 |
529 |
0 |
0 |
| T18 |
49517 |
1367 |
0 |
0 |
| T19 |
7027 |
39 |
0 |
0 |
| T20 |
62175 |
70 |
0 |
0 |
| T37 |
9175 |
22 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
572936531 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
572936531 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
572936531 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
3724 |
3724 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T20 |
1 |
1 |
0 |
0 |
| T37 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
931631 |
0 |
0 |
| T1 |
7880 |
3 |
0 |
0 |
| T2 |
10360 |
0 |
0 |
0 |
| T3 |
7739 |
0 |
0 |
0 |
| T7 |
553937 |
0 |
0 |
0 |
| T8 |
717299 |
0 |
0 |
0 |
| T17 |
22464 |
55 |
0 |
0 |
| T18 |
49517 |
56 |
0 |
0 |
| T19 |
7027 |
0 |
0 |
0 |
| T20 |
62175 |
8 |
0 |
0 |
| T22 |
0 |
81 |
0 |
0 |
| T24 |
0 |
8 |
0 |
0 |
| T35 |
0 |
4 |
0 |
0 |
| T37 |
9175 |
0 |
0 |
0 |
| T61 |
0 |
666 |
0 |
0 |
| T80 |
0 |
16 |
0 |
0 |
| T81 |
0 |
9 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
572936531 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
572936531 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
572936531 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
3724 |
3724 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T20 |
1 |
1 |
0 |
0 |
| T37 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
1819315 |
0 |
0 |
| T1 |
7880 |
10 |
0 |
0 |
| T2 |
10360 |
0 |
0 |
0 |
| T3 |
7739 |
0 |
0 |
0 |
| T7 |
553937 |
0 |
0 |
0 |
| T8 |
717299 |
0 |
0 |
0 |
| T17 |
22464 |
201 |
0 |
0 |
| T18 |
49517 |
257 |
0 |
0 |
| T19 |
7027 |
0 |
0 |
0 |
| T20 |
62175 |
8 |
0 |
0 |
| T22 |
0 |
81 |
0 |
0 |
| T24 |
0 |
8 |
0 |
0 |
| T35 |
0 |
4 |
0 |
0 |
| T37 |
9175 |
0 |
0 |
0 |
| T61 |
0 |
2900 |
0 |
0 |
| T80 |
0 |
16 |
0 |
0 |
| T81 |
0 |
31 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
572936531 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
572936531 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
572936531 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
3724 |
3724 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T20 |
1 |
1 |
0 |
0 |
| T37 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
19157225 |
0 |
0 |
| T1 |
7880 |
12 |
0 |
0 |
| T2 |
10360 |
17 |
0 |
0 |
| T3 |
7739 |
12 |
0 |
0 |
| T7 |
553937 |
296 |
0 |
0 |
| T8 |
717299 |
943 |
0 |
0 |
| T17 |
22464 |
100 |
0 |
0 |
| T18 |
49517 |
246 |
0 |
0 |
| T19 |
7027 |
11 |
0 |
0 |
| T20 |
62175 |
62 |
0 |
0 |
| T37 |
9175 |
22 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
572936531 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
572936531 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
572936531 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
3724 |
3724 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T20 |
1 |
1 |
0 |
0 |
| T37 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
43 // device facing
44 1/1 assign rvalid_o = wvalid_i;
Tests: T1 T2 T3
45 1/1 assign rdata_o = wdata_i;
Tests: T1 T2 T3
46
47 // host facing
48 1/1 assign wready_o = rready_i;
Tests: T1 T2 T3
49 1/1 assign full_o = rready_i;
Tests: T1 T2 T3
50
51 // this avoids lint warnings
52 logic unused_clr;
53 unreachable assign unused_clr = clr_i;
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
26350057 |
0 |
0 |
| T1 |
7880 |
44 |
0 |
0 |
| T2 |
10360 |
17 |
0 |
0 |
| T3 |
7739 |
12 |
0 |
0 |
| T7 |
553937 |
296 |
0 |
0 |
| T8 |
717299 |
943 |
0 |
0 |
| T17 |
22464 |
328 |
0 |
0 |
| T18 |
49517 |
1110 |
0 |
0 |
| T19 |
7027 |
39 |
0 |
0 |
| T20 |
62175 |
62 |
0 |
0 |
| T37 |
9175 |
22 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
572936531 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
572936531 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
573261852 |
572936531 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
3724 |
3724 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T20 |
1 |
1 |
0 |
0 |
| T37 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T1 T17 T18
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T1 T17 T18
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T1 T17 T18
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
| Total | Covered | Percent |
|---|
| Conditions | 11 | 11 | 100.00 |
| Logical | 11 | 11 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T17,T18 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T1,T17,T18 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T17,T18 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | Covered | T1,T17,T18 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T17,T18 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T17,T18 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T17,T18 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T17,T18 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
1776529 |
0 |
0 |
| T1 |
7880 |
10 |
0 |
0 |
| T2 |
10360 |
0 |
0 |
0 |
| T3 |
7739 |
0 |
0 |
0 |
| T7 |
553937 |
0 |
0 |
0 |
| T8 |
717299 |
0 |
0 |
0 |
| T17 |
22464 |
201 |
0 |
0 |
| T18 |
49517 |
257 |
0 |
0 |
| T19 |
7027 |
0 |
0 |
0 |
| T20 |
62175 |
8 |
0 |
0 |
| T22 |
0 |
81 |
0 |
0 |
| T24 |
0 |
8 |
0 |
0 |
| T35 |
0 |
4 |
0 |
0 |
| T37 |
9175 |
0 |
0 |
0 |
| T61 |
0 |
2900 |
0 |
0 |
| T80 |
0 |
16 |
0 |
0 |
| T81 |
0 |
31 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
571139677 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
571139677 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
571139677 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
1776529 |
0 |
0 |
| T1 |
7880 |
10 |
0 |
0 |
| T2 |
10360 |
0 |
0 |
0 |
| T3 |
7739 |
0 |
0 |
0 |
| T7 |
553937 |
0 |
0 |
0 |
| T8 |
717299 |
0 |
0 |
0 |
| T17 |
22464 |
201 |
0 |
0 |
| T18 |
49517 |
257 |
0 |
0 |
| T19 |
7027 |
0 |
0 |
0 |
| T20 |
62175 |
8 |
0 |
0 |
| T22 |
0 |
81 |
0 |
0 |
| T24 |
0 |
8 |
0 |
0 |
| T35 |
0 |
4 |
0 |
0 |
| T37 |
9175 |
0 |
0 |
0 |
| T61 |
0 |
2900 |
0 |
0 |
| T80 |
0 |
16 |
0 |
0 |
| T81 |
0 |
31 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T1 T17 T18
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T1 T17 T18
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T1 T17 T18
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
| Total | Covered | Percent |
|---|
| Conditions | 10 | 10 | 100.00 |
| Logical | 10 | 10 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T17,T18 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T1,T17,T18 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T17,T18 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T17,T18 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T17,T18 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T17,T18 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T17,T18 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
603496 |
0 |
0 |
| T1 |
7880 |
3 |
0 |
0 |
| T2 |
10360 |
0 |
0 |
0 |
| T3 |
7739 |
0 |
0 |
0 |
| T7 |
553937 |
0 |
0 |
0 |
| T8 |
717299 |
0 |
0 |
0 |
| T17 |
22464 |
55 |
0 |
0 |
| T18 |
49517 |
56 |
0 |
0 |
| T19 |
7027 |
0 |
0 |
0 |
| T20 |
62175 |
0 |
0 |
0 |
| T22 |
0 |
81 |
0 |
0 |
| T35 |
0 |
4 |
0 |
0 |
| T37 |
9175 |
0 |
0 |
0 |
| T43 |
0 |
16 |
0 |
0 |
| T61 |
0 |
126 |
0 |
0 |
| T80 |
0 |
16 |
0 |
0 |
| T81 |
0 |
9 |
0 |
0 |
| T82 |
0 |
6 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
571139677 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
571139677 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
571139677 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
603496 |
0 |
0 |
| T1 |
7880 |
3 |
0 |
0 |
| T2 |
10360 |
0 |
0 |
0 |
| T3 |
7739 |
0 |
0 |
0 |
| T7 |
553937 |
0 |
0 |
0 |
| T8 |
717299 |
0 |
0 |
0 |
| T17 |
22464 |
55 |
0 |
0 |
| T18 |
49517 |
56 |
0 |
0 |
| T19 |
7027 |
0 |
0 |
0 |
| T20 |
62175 |
0 |
0 |
0 |
| T22 |
0 |
81 |
0 |
0 |
| T35 |
0 |
4 |
0 |
0 |
| T37 |
9175 |
0 |
0 |
0 |
| T43 |
0 |
16 |
0 |
0 |
| T61 |
0 |
126 |
0 |
0 |
| T80 |
0 |
16 |
0 |
0 |
| T81 |
0 |
9 |
0 |
0 |
| T82 |
0 |
6 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T1 T17 T18
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T1 T17 T18
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
| Total | Covered | Percent |
|---|
| Conditions | 18 | 18 | 100.00 |
| Logical | 18 | 18 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T17,T18 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T1,T17,T18 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T17,T18 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 1 | Covered | T1,T17,T18 |
| 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | Covered | T1,T17,T18 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T17,T18 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T17,T18 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T17,T18 |
| 1 | 0 | Covered | T1,T17,T18 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T17,T18 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
| Line No. | Total | Covered | Percent |
| Branches |
|
9 |
9 |
100.00 |
| TERNARY |
130 |
2 |
2 |
100.00 |
| TERNARY |
138 |
2 |
2 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
111 |
2 |
2 |
100.00 |
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T17,T18 |
| 0 |
Covered |
T1,T2,T3 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T17,T18 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T17,T18 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
1231158 |
0 |
0 |
| T1 |
7880 |
10 |
0 |
0 |
| T2 |
10360 |
0 |
0 |
0 |
| T3 |
7739 |
0 |
0 |
0 |
| T7 |
553937 |
0 |
0 |
0 |
| T8 |
717299 |
0 |
0 |
0 |
| T17 |
22464 |
201 |
0 |
0 |
| T18 |
49517 |
257 |
0 |
0 |
| T19 |
7027 |
0 |
0 |
0 |
| T20 |
62175 |
0 |
0 |
0 |
| T22 |
0 |
81 |
0 |
0 |
| T35 |
0 |
4 |
0 |
0 |
| T37 |
9175 |
0 |
0 |
0 |
| T43 |
0 |
16 |
0 |
0 |
| T61 |
0 |
597 |
0 |
0 |
| T80 |
0 |
16 |
0 |
0 |
| T81 |
0 |
31 |
0 |
0 |
| T82 |
0 |
25 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
571139677 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
571139677 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
571139677 |
0 |
0 |
| T1 |
7880 |
7822 |
0 |
0 |
| T2 |
10360 |
10264 |
0 |
0 |
| T3 |
7739 |
7652 |
0 |
0 |
| T7 |
553937 |
553870 |
0 |
0 |
| T8 |
717299 |
717211 |
0 |
0 |
| T17 |
22464 |
22402 |
0 |
0 |
| T18 |
49517 |
49445 |
0 |
0 |
| T19 |
7027 |
6958 |
0 |
0 |
| T20 |
62175 |
62099 |
0 |
0 |
| T37 |
9175 |
9106 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
571423708 |
1231158 |
0 |
0 |
| T1 |
7880 |
10 |
0 |
0 |
| T2 |
10360 |
0 |
0 |
0 |
| T3 |
7739 |
0 |
0 |
0 |
| T7 |
553937 |
0 |
0 |
0 |
| T8 |
717299 |
0 |
0 |
0 |
| T17 |
22464 |
201 |
0 |
0 |
| T18 |
49517 |
257 |
0 |
0 |
| T19 |
7027 |
0 |
0 |
0 |
| T20 |
62175 |
0 |
0 |
0 |
| T22 |
0 |
81 |
0 |
0 |
| T35 |
0 |
4 |
0 |
0 |
| T37 |
9175 |
0 |
0 |
0 |
| T43 |
0 |
16 |
0 |
0 |
| T61 |
0 |
597 |
0 |
0 |
| T80 |
0 |
16 |
0 |
0 |
| T81 |
0 |
31 |
0 |
0 |
| T82 |
0 |
25 |
0 |
0 |