Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9257150	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9859681

1

T1

4

T2

4

T3

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	18479146	1			T1	3		T2	8		T3	7
values[0x0]	318318	1			T1	2		T2	2		T3	5
values[0x1]	319367	1			T1	7		T2	7		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7358243	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

11758588

1

T1

7

T2

9

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55464	1			T49	6		T91	1		T4	45
valid_sources[0x01]	60195	1			T4	65		T92	4		T116	101
valid_sources[0x02]	57367	1			T36	2		T49	6		T64	1
valid_sources[0x03]	59024	1			T49	6		T4	58		T92	4
valid_sources[0x04]	62963	1			T36	1		T49	6		T4	33
valid_sources[0x05]	74853	1			T40	2		T36	5		T49	8
valid_sources[0x06]	97044	1			T36	2		T49	1		T52	1
valid_sources[0x07]	59532	1			T49	1		T4	63		T92	5
valid_sources[0x08]	55301	1			T3	2		T49	7		T8	2
valid_sources[0x09]	54963	1			T49	5		T91	3		T313	1
valid_sources[0x0a]	56841	1			T40	2		T312	1		T52	1
valid_sources[0x0b]	107817	1			T49	12		T64	3		T4	32
valid_sources[0x0c]	102639	1			T18	2		T4	55		T92	1
valid_sources[0x0d]	55832	1			T50	3		T49	5		T4	35
valid_sources[0x0e]	55459	1			T49	3		T4	20		T20	5
valid_sources[0x0f]	82329	1			T36	1		T4	56		T92	3
valid_sources[0x10]	57389	1			T48	5		T49	3		T4	46
valid_sources[0x11]	92931	1			T49	10		T4	43		T327	1
valid_sources[0x12]	71856	1			T49	3		T4	28		T92	5
valid_sources[0x13]	86485	1			T48	1		T49	8		T4	20
valid_sources[0x14]	65889	1			T49	9		T105	1		T4	24
valid_sources[0x15]	82453	1			T77	1		T49	6		T64	1
valid_sources[0x16]	54505	1			T49	20		T52	1		T91	2
valid_sources[0x17]	55457	1			T77	1		T49	3		T4	23
valid_sources[0x18]	138915	1			T3	1		T40	3		T49	11
valid_sources[0x19]	70639	1			T49	7		T52	2		T4	29
valid_sources[0x1a]	60866	1			T49	5		T4	25		T92	1
valid_sources[0x1b]	58311	1			T49	3		T52	2		T341	1
valid_sources[0x1c]	56461	1			T49	4		T52	1		T341	1
valid_sources[0x1d]	103955	1			T49	12		T313	1		T18	1
valid_sources[0x1e]	55601	1			T42	1		T49	16		T313	1
valid_sources[0x1f]	56328	1			T49	2		T4	34		T92	1
valid_sources[0x20]	70072	1			T36	1		T77	1		T49	12
valid_sources[0x21]	84023	1			T49	14		T313	1		T4	64
valid_sources[0x22]	55540	1			T36	5		T49	10		T4	43
valid_sources[0x23]	69199	1			T49	7		T105	1		T4	49
valid_sources[0x24]	74472	1			T49	5		T4	32		T92	7
valid_sources[0x25]	154844	1			T49	4		T91	1		T313	1
valid_sources[0x26]	76468	1			T49	2		T8	2		T4	17
valid_sources[0x27]	55851	1			T49	8		T91	1		T4	56
valid_sources[0x28]	76759	1			T312	1		T49	6		T4	30
valid_sources[0x29]	62304	1			T27	1		T49	5		T4	28
valid_sources[0x2a]	56314	1			T49	6		T64	1		T4	46
valid_sources[0x2b]	276588	1			T30	2		T49	1		T64	1
valid_sources[0x2c]	56636	1			T3	1		T41	1		T49	1
valid_sources[0x2d]	77244	1			T49	11		T196	3		T18	2
valid_sources[0x2e]	56066	1			T48	1		T49	4		T4	44
valid_sources[0x2f]	55647	1			T4	88		T92	4		T116	76
valid_sources[0x30]	56375	1			T49	13		T4	48		T226	1
valid_sources[0x31]	59352	1			T36	2		T49	16		T105	1
valid_sources[0x32]	56078	1			T1	1		T49	2		T4	21
valid_sources[0x33]	74334	1			T49	11		T4	35		T327	1
valid_sources[0x34]	54864	1			T3	1		T49	1		T18	1
valid_sources[0x35]	54622	1			T48	2		T77	1		T49	2
valid_sources[0x36]	142739	1			T42	1		T53	13		T4	35
valid_sources[0x37]	55798	1			T49	8		T18	1		T4	60
valid_sources[0x38]	113052	1			T42	1		T49	2		T8	1
valid_sources[0x39]	55450	1			T49	2		T4	16		T20	3
valid_sources[0x3a]	55287	1			T49	8		T4	59		T92	6
valid_sources[0x3b]	55534	1			T49	7		T91	2		T4	50
valid_sources[0x3c]	55933	1			T49	14		T313	1		T4	32
valid_sources[0x3d]	86517	1			T50	2		T49	7		T4	62
valid_sources[0x3e]	76546	1			T49	4		T4	48		T92	2
valid_sources[0x3f]	162015	1			T40	2		T28	163		T49	7
valid_sources[0x40]	57339	1			T42	1		T49	1		T4	46
valid_sources[0x41]	108637	1			T49	1		T53	2		T8	1
valid_sources[0x42]	126903	1			T49	10		T52	1		T4	36
valid_sources[0x43]	64427	1			T36	3		T49	7		T52	1
valid_sources[0x44]	57040	1			T49	4		T4	39		T92	6
valid_sources[0x45]	55600	1			T49	1		T4	24		T20	4
valid_sources[0x46]	55566	1			T49	1		T8	1		T4	53
valid_sources[0x47]	70313	1			T49	3		T4	50		T92	5
valid_sources[0x48]	56029	1			T49	5		T52	1		T4	92
valid_sources[0x49]	55852	1			T42	1		T49	3		T4	41
valid_sources[0x4a]	65894	1			T49	4		T24	1		T4	24
valid_sources[0x4b]	69905	1			T4	61		T20	3		T92	7
valid_sources[0x4c]	55226	1			T77	1		T49	4		T313	1
valid_sources[0x4d]	56630	1			T49	2		T4	31		T327	1
valid_sources[0x4e]	59479	1			T49	2		T24	2		T313	2
valid_sources[0x4f]	56745	1			T40	3		T41	2		T34	58
valid_sources[0x50]	54642	1			T87	20		T77	1		T49	1
valid_sources[0x51]	56228	1			T49	5		T4	38		T92	7
valid_sources[0x52]	74338	1			T49	2		T4	47		T92	6
valid_sources[0x53]	54974	1			T50	1		T49	8		T4	6
valid_sources[0x54]	56344	1			T1	1		T49	7		T64	1
valid_sources[0x55]	77003	1			T50	1		T49	6		T8	1
valid_sources[0x56]	56558	1			T27	1		T49	5		T4	49
valid_sources[0x57]	56412	1			T3	1		T42	1		T49	4
valid_sources[0x58]	123174	1			T3	1		T32	3		T49	10
valid_sources[0x59]	56699	1			T3	1		T39	1		T49	3
valid_sources[0x5a]	55833	1			T42	1		T30	1		T50	1
valid_sources[0x5b]	105977	1			T40	14		T49	6		T313	1
valid_sources[0x5c]	55716	1			T49	7		T4	48		T92	6
valid_sources[0x5d]	56579	1			T49	1		T4	24		T92	6
valid_sources[0x5e]	81540	1			T39	1		T312	1		T49	4
valid_sources[0x5f]	56617	1			T36	3		T49	1		T8	7
valid_sources[0x60]	56923	1			T50	1		T49	5		T18	1
valid_sources[0x61]	56531	1			T312	2		T49	5		T4	38
valid_sources[0x62]	90615	1			T49	7		T4	46		T92	1
valid_sources[0x63]	56615	1			T49	10		T4	42		T116	99
valid_sources[0x64]	61164	1			T49	1		T4	37		T20	4
valid_sources[0x65]	55658	1			T49	9		T4	66		T92	3
valid_sources[0x66]	123369	1			T49	9		T4	48		T92	5
valid_sources[0x67]	56028	1			T49	10		T196	3		T52	1
valid_sources[0x68]	69447	1			T49	10		T64	2		T4	37
valid_sources[0x69]	59545	1			T49	10		T52	1		T341	1
valid_sources[0x6a]	56737	1			T37	12		T77	1		T105	2
valid_sources[0x6b]	120179	1			T3	1		T50	1		T49	8
valid_sources[0x6c]	56450	1			T36	1		T49	4		T4	60
valid_sources[0x6d]	74157	1			T49	2		T4	34		T92	6
valid_sources[0x6e]	136133	1			T75	58		T18	1		T4	75
valid_sources[0x6f]	58537	1			T36	1		T49	4		T64	3
valid_sources[0x70]	78171	1			T50	1		T49	4		T52	6
valid_sources[0x71]	57132	1			T50	3		T49	8		T4	50
valid_sources[0x72]	85524	1			T49	5		T4	50		T92	5
valid_sources[0x73]	70183	1			T40	4		T49	6		T4	22
valid_sources[0x74]	64020	1			T49	1		T105	2		T4	75
valid_sources[0x75]	54587	1			T76	2		T49	24		T8	1
valid_sources[0x76]	56428	1			T27	3		T40	1		T30	2
valid_sources[0x77]	159298	1			T42	1		T29	270		T49	1
valid_sources[0x78]	55770	1			T76	2		T49	10		T64	1
valid_sources[0x79]	57256	1			T49	10		T8	1		T4	76
valid_sources[0x7a]	319569	1			T49	5		T8	1		T4	33
valid_sources[0x7b]	56819	1			T49	5		T64	1		T4	57
valid_sources[0x7c]	56634	1			T49	1		T341	1		T4	55
valid_sources[0x7d]	56945	1			T50	1		T49	4		T4	74
valid_sources[0x7e]	54969	1			T27	1		T50	2		T49	2
valid_sources[0x7f]	55757	1			T40	6		T32	1		T89	13
valid_sources[0x80]	55164	1			T40	3		T49	11		T4	37

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9339601

1

T1

1

T2

2

T3

5

values[0x0]

all_enables

biggest_size

268317

1

T1

1

T2

2

T3

2

values[0x1]

all_enables

biggest_size

251763

1

T1

2

T3

4

T27

2