Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

9271641

1

T1

8

T2

13

T3

11

full_word

9860682

1

T1

4

T2

4

T3

11

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	19132043	1			T1	12		T2	17		T3	22
auto[TlIntgErrCmd]	89	1			T230	6		T242	3		T243	4
auto[TlIntgErrData]	92	1			T230	6		T242	10		T243	5
auto[TlIntgErrBoth]	99	1			T230	8		T242	7		T243	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18481101

1

T1

3

T2

8

T3

7

auto[1]

651222

1

T1

9

T2

9

T3

15

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9141190	1			T1	2		T2	6		T3	2
auto[TlIntgErrNone]	partial	auto[1]	130197	1			T1	6		T2	7		T3	9
auto[TlIntgErrNone]	full_word	auto[0]	9339786	1			T1	1		T2	2		T3	5
auto[TlIntgErrNone]	full_word	auto[1]	520870	1			T1	3		T2	2		T3	6
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T230	3		T512	4		T513	1
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T230	3		T242	2		T243	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T514	1		T511	1		T515	2
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T242	1		T243	1		T513	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T230	3		T242	5		T514	4
auto[TlIntgErrData]	partial	auto[1]	45	1			T230	3		T242	5		T243	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T514	1		T301	1		T515	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T243	1		T516	1		T515	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T230	6		T514	1		T512	4
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T230	1		T242	7		T243	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T230	1		T511	1		T517	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T301	2		T511	1		T515	1