Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	580365803	11962	0	0
ep_in_enable_rd_A	580365803	1036	0	0
ep_out_enable_rd_A	580365803	1119	0	0
in_iso_rd_A	580365803	1087	0	0
intr_enable_rd_A	580365803	1499	0	0
out_iso_rd_A	580365803	1134	0	0
phy_config_rd_A	580365803	798	0	0
phy_pins_drive_rd_A	580365803	1072	0	0
rxenable_setup_rd_A	580365803	1038	0	0
set_nak_out_rd_A	580365803	1067	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580365803	11962	0	0
T213	6870	18	0	0
T214	3456	621	0	0
T215	6817	693	0	0
T230	31951	3	0	0
T242	126877	4	0	0
T243	16456	2	0	0
T245	7033	460	0	0
T249	11773	701	0	0
T256	7683	13	0	0
T257	2720	10	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580365803	1036	0	0
T233	20503	209	0	0
T247	8257	49	0	0
T271	33313	114	0	0
T273	4064	4	0	0
T276	21020	193	0	0
T294	8959	56	0	0
T295	4684	15	0	0
T296	4636	13	0	0
T297	10691	27	0	0
T298	7321	29	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580365803	1119	0	0
T233	20503	179	0	0
T244	3556	4	0	0
T247	8257	63	0	0
T271	33313	115	0	0
T273	4064	5	0	0
T276	21020	232	0	0
T294	8959	45	0	0
T296	4636	4	0	0
T297	10691	13	0	0
T298	7321	4	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580365803	1087	0	0
T233	20503	189	0	0
T246	15205	9	0	0
T247	8257	55	0	0
T271	33313	148	0	0
T273	4064	14	0	0
T276	21020	222	0	0
T294	8959	79	0	0
T295	4684	41	0	0
T296	4636	10	0	0
T297	10691	50	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580365803	1499	0	0
T218	2457	9	0	0
T233	20503	223	0	0
T247	8257	60	0	0
T271	33313	157	0	0
T273	4064	8	0	0
T276	21020	183	0	0
T294	8959	37	0	0
T295	4684	39	0	0
T299	2241	13	0	0
T300	1534	15	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580365803	1134	0	0
T233	20503	224	0	0
T244	3556	8	0	0
T247	8257	65	0	0
T271	33313	159	0	0
T273	4064	3	0	0
T276	21020	153	0	0
T294	8959	37	0	0
T295	4684	1	0	0
T296	4636	13	0	0
T297	10691	16	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580365803	798	0	0
T233	20503	202	0	0
T244	3556	3	0	0
T247	8257	24	0	0
T271	33313	81	0	0
T273	4064	6	0	0
T276	21020	171	0	0
T294	8959	51	0	0
T295	4684	8	0	0
T296	4636	7	0	0
T297	10691	28	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580365803	1072	0	0
T233	20503	212	0	0
T244	3556	7	0	0
T247	8257	18	0	0
T271	33313	139	0	0
T273	4064	2	0	0
T276	21020	171	0	0
T294	8959	39	0	0
T295	4684	35	0	0
T296	4636	15	0	0
T297	10691	6	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580365803	1038	0	0
T233	20503	212	0	0
T247	8257	55	0	0
T271	33313	127	0	0
T273	4064	4	0	0
T276	21020	203	0	0
T294	8959	29	0	0
T295	4684	32	0	0
T296	4636	12	0	0
T298	7321	42	0	0
T301	58588	249	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580365803	1067	0	0
T233	20503	203	0	0
T244	3556	7	0	0
T247	8257	63	0	0
T249	11773	4	0	0
T271	33313	117	0	0
T273	4064	13	0	0
T276	21020	186	0	0
T294	8959	34	0	0
T295	4684	18	0	0
T296	4636	6	0	0