Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_filter
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_filter.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.usbdev_impl.u_usbdev_linkstate.filter_se0 100.00 100.00 100.00 100.00
tb.dut.usbdev_impl.u_usbdev_linkstate.filter_pwr_sense 100.00 100.00 100.00 100.00


Module Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_se0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.33 97.12 95.52 96.00 98.00 100.00 u_usbdev_linkstate


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_pwr_sense

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.33 97.12 95.52 96.00 98.00 100.00 u_usbdev_linkstate


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_filter
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN4411100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00


43                        end else begin : gen_sync
44         1/1              assign filter_synced = filter_i;
           Tests:       T1 T2 T3 
45                        end
46                      
47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T1 T2 T3 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T1 T2 T3 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T1 T2 T3 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T1 T2 T3 
Cond Coverage for Module : prim_filter
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3
Branch Coverage for Module : prim_filter
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 70 1 1 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00 



70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==> (Unreachable)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable 



48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_se0
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN4411100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00


43                        end else begin : gen_sync
44         1/1              assign filter_synced = filter_i;
           Tests:       T1 T2 T3 
45                        end
46                      
47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T1 T2 T3 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T1 T2 T3 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T1 T2 T3 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_se0
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_se0
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 70 1 1 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00 



70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==> (Unreachable)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable 



48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_pwr_sense
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN4411100.00
ALWAYS4844100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
ALWAYS5933100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7011100.00


43                        end else begin : gen_sync
44         1/1              assign filter_synced = filter_i;
           Tests:       T1 T2 T3 
45                        end
46                      
47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
49         1/1                stored_value_q <= 1'b0;
           Tests:       T1 T2 T3 
50         1/1              end else if (update_stored_value) begin
           Tests:       T1 T2 T3 
51         1/1                stored_value_q <= filter_synced;
           Tests:       T1 T2 T3 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_synced};
           Tests:       T1 T2 T3 
56         1/1            assign unused_stored_vector_q_msb = stored_vector_q[Cycles-1];
           Tests:       T1 T2 T3 
57                      
58                        always_ff @(posedge clk_i or negedge rst_ni) begin
59         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
60         1/1                stored_vector_q <= '0;
           Tests:       T1 T2 T3 
61                          end else begin
62         1/1                stored_vector_q <= stored_vector_d;
           Tests:       T1 T2 T3 
63                          end
64                        end
65                      
66         1/1            assign update_stored_value =
           Tests:       T1 T2 T3 
67                                   (stored_vector_d == {Cycles{1'b0}}) |
68                                   (stored_vector_d == {Cycles{1'b1}});
69                      
70         1/1            assign filter_o = enable_i ? stored_value_q : filter_synced;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_pwr_sense
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION ((stored_vector_d == {Cycles {1'b0}}) | (stored_vector_d == {Cycles {1'b1}}))
             ------------------1-----------------   ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b0}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (stored_vector_d == {Cycles {1'b1}})
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       70
 EXPRESSION (enable_i ? stored_value_q : filter_synced)
             ----1---
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate.filter_pwr_sense
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 70 1 1 100.00
IF 48 3 3 100.00
IF 59 2 2 100.00 



70           assign filter_o = enable_i ? stored_value_q : filter_synced;
                                        -1-  
                                        ==>  
                                        ==> (Unreachable)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable 



48             if (!rst_ni) begin
               -1-  
49               stored_value_q <= 1'b0;
                 ==>
50             end else if (update_stored_value) begin
                        -2-  
51               stored_value_q <= filter_synced;
                 ==>
52             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



59             if (!rst_ni) begin
               -1-  
60               stored_vector_q <= '0;
                 ==>
61             end else begin
62               stored_vector_q <= stored_vector_d;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%