Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9179267	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9810299

1

T1

9

T2

4

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	18330956	1			T1	7		T2	10		T3	414
values[0x0]	328595	1			T1	4		T2	3		T3	6
values[0x1]	330015	1			T1	3		T2	7		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7297583	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

11691983

1

T1

10

T2

13

T3

149

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55481	1			T20	1		T29	15		T30	1
valid_sources[0x01]	56063	1			T20	1		T28	2		T30	2
valid_sources[0x02]	56045	1			T3	7		T59	120		T108	129
valid_sources[0x03]	56348	1			T20	1		T29	2		T59	129
valid_sources[0x04]	57870	1			T28	3		T29	3		T59	100
valid_sources[0x05]	56116	1			T29	11		T30	2		T59	135
valid_sources[0x06]	57203	1			T28	1		T29	1		T59	115
valid_sources[0x07]	55236	1			T29	1		T59	105		T108	71
valid_sources[0x08]	79298	1			T29	17		T30	1		T59	102
valid_sources[0x09]	55641	1			T29	1		T59	104		T108	112
valid_sources[0x0a]	56625	1			T29	11		T59	110		T108	96
valid_sources[0x0b]	109789	1			T20	1		T28	3		T29	6
valid_sources[0x0c]	56037	1			T28	4		T29	3		T59	104
valid_sources[0x0d]	75528	1			T23	29		T24	6		T28	2
valid_sources[0x0e]	56068	1			T2	1		T59	117		T108	57
valid_sources[0x0f]	56269	1			T28	2		T29	6		T70	2
valid_sources[0x10]	127967	1			T29	19		T59	96		T108	104
valid_sources[0x11]	92980	1			T22	7		T29	19		T59	114
valid_sources[0x12]	111501	1			T20	1		T29	1		T59	115
valid_sources[0x13]	76992	1			T3	44		T20	2		T29	6
valid_sources[0x14]	161315	1			T28	5		T29	3		T59	108
valid_sources[0x15]	75366	1			T2	1		T24	1		T29	8
valid_sources[0x16]	59604	1			T20	1		T28	4		T29	2
valid_sources[0x17]	109590	1			T29	13		T70	4		T59	106
valid_sources[0x18]	75667	1			T3	2		T20	2		T29	9
valid_sources[0x19]	61407	1			T29	6		T59	114		T108	131
valid_sources[0x1a]	85321	1			T29	1		T42	12		T59	108
valid_sources[0x1b]	82864	1			T20	2		T29	8		T59	107
valid_sources[0x1c]	56715	1			T29	15		T59	102		T108	44
valid_sources[0x1d]	63602	1			T20	1		T28	1		T30	1
valid_sources[0x1e]	110209	1			T3	2		T28	3		T29	6
valid_sources[0x1f]	55203	1			T20	1		T59	117		T108	83
valid_sources[0x20]	63357	1			T3	18		T28	10		T34	1
valid_sources[0x21]	163489	1			T2	1		T28	2		T59	105
valid_sources[0x22]	58509	1			T29	10		T59	104		T108	95
valid_sources[0x23]	97632	1			T28	3		T29	6		T59	99
valid_sources[0x24]	56470	1			T20	2		T24	5		T29	2
valid_sources[0x25]	55377	1			T3	25		T29	10		T59	103
valid_sources[0x26]	55882	1			T20	1		T28	2		T59	98
valid_sources[0x27]	63795	1			T29	7		T59	102		T108	71
valid_sources[0x28]	79902	1			T28	6		T29	6		T30	1
valid_sources[0x29]	66480	1			T29	14		T59	99		T108	56
valid_sources[0x2a]	80523	1			T28	8		T29	4		T59	95
valid_sources[0x2b]	117457	1			T2	1		T20	1		T29	6
valid_sources[0x2c]	56471	1			T28	1		T59	114		T108	89
valid_sources[0x2d]	75687	1			T20	1		T29	1		T59	91
valid_sources[0x2e]	72026	1			T16	1		T29	4		T59	110
valid_sources[0x2f]	54357	1			T3	17		T28	1		T59	95
valid_sources[0x30]	55912	1			T3	43		T29	9		T59	105
valid_sources[0x31]	55444	1			T28	1		T29	2		T59	127
valid_sources[0x32]	58206	1			T19	6		T29	9		T30	1
valid_sources[0x33]	73132	1			T3	22		T28	1		T29	1
valid_sources[0x34]	56930	1			T29	2		T70	1		T59	92
valid_sources[0x35]	55820	1			T20	1		T29	1		T30	1
valid_sources[0x36]	54670	1			T29	4		T59	100		T108	63
valid_sources[0x37]	57134	1			T20	1		T29	5		T70	1
valid_sources[0x38]	135573	1			T28	1		T29	1		T59	110
valid_sources[0x39]	55185	1			T28	2		T70	1		T59	111
valid_sources[0x3a]	88817	1			T28	1		T59	101		T108	133
valid_sources[0x3b]	159410	1			T3	12		T16	1		T28	1
valid_sources[0x3c]	74276	1			T20	1		T29	6		T7	80
valid_sources[0x3d]	55209	1			T20	1		T29	7		T59	87
valid_sources[0x3e]	57853	1			T59	118		T108	70		T66	5
valid_sources[0x3f]	56907	1			T29	1		T59	104		T108	97
valid_sources[0x40]	77622	1			T29	7		T59	95		T108	82
valid_sources[0x41]	55293	1			T3	11		T30	1		T59	112
valid_sources[0x42]	64450	1			T28	1		T59	112		T108	85
valid_sources[0x43]	105714	1			T28	1		T29	5		T59	132
valid_sources[0x44]	55417	1			T17	1		T29	5		T59	105
valid_sources[0x45]	87012	1			T28	2		T59	112		T108	168
valid_sources[0x46]	89112	1			T20	3		T29	14		T59	95
valid_sources[0x47]	74383	1			T20	2		T29	1		T59	116
valid_sources[0x48]	57389	1			T17	3		T24	1		T28	3
valid_sources[0x49]	57559	1			T29	4		T30	1		T70	2
valid_sources[0x4a]	56038	1			T28	1		T29	9		T30	1
valid_sources[0x4b]	72565	1			T3	3		T20	1		T29	9
valid_sources[0x4c]	55436	1			T29	4		T59	84		T108	83
valid_sources[0x4d]	87618	1			T28	1		T29	6		T34	2
valid_sources[0x4e]	56081	1			T29	10		T59	111		T108	109
valid_sources[0x4f]	68245	1			T32	1		T59	124		T108	94
valid_sources[0x50]	56076	1			T29	1		T59	107		T108	120
valid_sources[0x51]	55336	1			T17	1		T29	5		T59	122
valid_sources[0x52]	113119	1			T3	52		T29	4		T59	104
valid_sources[0x53]	80014	1			T2	1		T3	9		T29	2
valid_sources[0x54]	56130	1			T20	1		T28	5		T29	8
valid_sources[0x55]	56837	1			T59	89		T108	73		T43	5
valid_sources[0x56]	57373	1			T24	2		T28	3		T29	16
valid_sources[0x57]	65999	1			T28	1		T29	4		T30	1
valid_sources[0x58]	56826	1			T28	1		T29	4		T59	103
valid_sources[0x59]	56095	1			T20	1		T59	125		T108	127
valid_sources[0x5a]	140786	1			T28	3		T29	11		T59	128
valid_sources[0x5b]	72068	1			T28	1		T29	12		T32	2
valid_sources[0x5c]	56683	1			T30	2		T59	101		T108	87
valid_sources[0x5d]	69561	1			T28	1		T29	15		T59	114
valid_sources[0x5e]	56810	1			T29	8		T59	104		T108	84
valid_sources[0x5f]	77590	1			T29	4		T70	2		T59	100
valid_sources[0x60]	55214	1			T28	2		T59	113		T108	89
valid_sources[0x61]	147201	1			T29	7		T59	109		T108	66
valid_sources[0x62]	54863	1			T28	1		T29	4		T70	1
valid_sources[0x63]	56094	1			T2	2		T28	2		T29	2
valid_sources[0x64]	54851	1			T20	1		T29	2		T30	1
valid_sources[0x65]	136771	1			T20	2		T59	107		T108	57
valid_sources[0x66]	60493	1			T20	2		T28	1		T59	100
valid_sources[0x67]	55565	1			T29	1		T59	80		T108	97
valid_sources[0x68]	56459	1			T29	4		T70	1		T59	118
valid_sources[0x69]	65991	1			T17	1		T29	8		T30	1
valid_sources[0x6a]	57299	1			T20	1		T29	9		T59	115
valid_sources[0x6b]	56448	1			T29	16		T30	2		T59	111
valid_sources[0x6c]	55185	1			T59	114		T108	83		T43	2
valid_sources[0x6d]	55501	1			T16	1		T28	2		T29	2
valid_sources[0x6e]	55027	1			T19	1		T28	1		T29	16
valid_sources[0x6f]	57050	1			T20	1		T24	1		T59	92
valid_sources[0x70]	55752	1			T2	1		T28	1		T59	97
valid_sources[0x71]	71053	1			T20	1		T29	9		T59	111
valid_sources[0x72]	55661	1			T2	1		T29	10		T59	97
valid_sources[0x73]	56083	1			T20	1		T24	7		T28	2
valid_sources[0x74]	55520	1			T17	1		T29	5		T59	126
valid_sources[0x75]	74327	1			T20	1		T59	105		T108	81
valid_sources[0x76]	56446	1			T3	10		T59	109		T108	61
valid_sources[0x77]	104918	1			T3	2		T20	1		T24	5
valid_sources[0x78]	85271	1			T28	10		T70	1		T59	127
valid_sources[0x79]	95146	1			T3	21		T16	1		T20	1
valid_sources[0x7a]	162983	1			T29	15		T30	2		T59	106
valid_sources[0x7b]	70395	1			T17	3		T29	1		T59	103
valid_sources[0x7c]	56257	1			T24	1		T28	2		T29	6
valid_sources[0x7d]	66255	1			T29	18		T59	105		T108	95
valid_sources[0x7e]	123824	1			T28	1		T70	1		T59	106
valid_sources[0x7f]	55042	1			T29	7		T30	1		T32	1
valid_sources[0x80]	67433	1			T28	2		T29	6		T59	115

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9281160

1

T1

7

T2

1

T3

2

values[0x0]

all_enables

biggest_size

273414

1

T1

2

T2

2

T3

6

values[0x1]

all_enables

biggest_size

255725

1

T2

1

T3

2

T16

1