Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

9193377

1

T1

5

T2

16

T3

417

full_word

9811299

1

T1

9

T2

4

T3

10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	19004386	1			T1	14		T2	20		T3	427
auto[TlIntgErrCmd]	91	1			T223	5		T262	2		T265	3
auto[TlIntgErrData]	95	1			T223	2		T262	4		T265	9
auto[TlIntgErrBoth]	104	1			T223	3		T262	4		T265	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18332882

1

T1

7

T2

10

T3

414

auto[1]

671794

1

T1

7

T2

10

T3

13

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9051437	1			T2	9		T3	412		T16	3
auto[TlIntgErrNone]	partial	auto[1]	141679	1			T1	5		T2	7		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	9281320	1			T1	7		T2	1		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	529950	1			T1	2		T2	3		T3	8
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T223	2		T590	1		T593	4
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T223	3		T262	1		T265	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T594	1		T595	1		T596	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T262	1		T265	1		T590	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T262	3		T265	3		T589	4
auto[TlIntgErrData]	partial	auto[1]	33	1			T223	1		T265	6		T592	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T594	2		T597	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	8	1			T223	1		T262	1		T592	2
auto[TlIntgErrBoth]	partial	auto[0]	28	1			T223	1		T265	4		T590	1
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T223	2		T262	3		T265	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T598	1		T599	1		T600	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T262	1		T589	1		T593	2