Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	584828014	10560	0	0
ep_in_enable_rd_A	584828014	3903	0	0
ep_out_enable_rd_A	584828014	4167	0	0
in_iso_rd_A	584828014	4308	0	0
intr_enable_rd_A	584828014	5655	0	0
out_iso_rd_A	584828014	4508	0	0
phy_config_rd_A	584828014	2891	0	0
phy_pins_drive_rd_A	584828014	3990	0	0
rxenable_setup_rd_A	584828014	4493	0	0
set_nak_out_rd_A	584828014	4519	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	10560	0	0
T222	3801	622	0	0
T223	45738	3	0	0
T224	3466	569	0	0
T256	7071	16	0	0
T262	36265	2	0	0
T265	31315	5	0	0
T266	7799	16	0	0
T270	12687	527	0	0
T271	8647	291	0	0
T280	3020	8	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	3903	0	0
T223	45738	92	0	0
T262	36265	203	0	0
T270	12687	5	0	0
T275	9629	57	0	0
T300	4305	16	0	0
T303	3021	17	0	0
T307	4096	12	0	0
T309	4311	6	0	0
T313	11108	49	0	0
T324	3419	49	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	4167	0	0
T223	45738	180	0	0
T262	36265	253	0	0
T275	9629	86	0	0
T300	4305	66	0	0
T303	3021	17	0	0
T307	4096	10	0	0
T309	4311	5	0	0
T311	65553	300	0	0
T313	11108	21	0	0
T324	3419	3	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	4308	0	0
T223	45738	187	0	0
T262	36265	203	0	0
T275	9629	8	0	0
T300	4305	40	0	0
T303	3021	10	0	0
T307	4096	1	0	0
T309	4311	6	0	0
T311	65553	230	0	0
T313	11108	16	0	0
T324	3419	48	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	5655	0	0
T223	45738	490	0	0
T262	36265	236	0	0
T275	9629	94	0	0
T300	4305	12	0	0
T307	4096	2	0	0
T309	4311	48	0	0
T311	65553	287	0	0
T313	11108	37	0	0
T324	3419	2	0	0
T325	2223	17	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	4508	0	0
T223	45738	252	0	0
T262	36265	295	0	0
T275	9629	95	0	0
T300	4305	55	0	0
T303	3021	20	0	0
T307	4096	14	0	0
T309	4311	27	0	0
T311	65553	313	0	0
T313	11108	41	0	0
T324	3419	43	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	2891	0	0
T223	45738	112	0	0
T262	36265	185	0	0
T275	9629	56	0	0
T281	9252	52	0	0
T300	4305	10	0	0
T307	4096	3	0	0
T309	4311	16	0	0
T311	65553	243	0	0
T313	11108	38	0	0
T324	3419	26	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	3990	0	0
T223	45738	131	0	0
T262	36265	282	0	0
T275	9629	38	0	0
T300	4305	4	0	0
T303	3021	20	0	0
T307	4096	2	0	0
T309	4311	19	0	0
T311	65553	246	0	0
T313	11108	24	0	0
T324	3419	52	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	4493	0	0
T223	45738	218	0	0
T262	36265	211	0	0
T275	9629	116	0	0
T300	4305	55	0	0
T303	3021	19	0	0
T307	4096	4	0	0
T309	4311	31	0	0
T311	65553	297	0	0
T313	11108	35	0	0
T324	3419	58	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	4519	0	0
T223	45738	290	0	0
T262	36265	321	0	0
T275	9629	85	0	0
T300	4305	97	0	0
T303	3021	4	0	0
T307	4096	8	0	0
T309	4311	48	0	0
T311	65553	278	0	0
T313	11108	8	0	0
T324	3419	41	0	0