Line Coverage for Module :
usb_fs_tx
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 184 | 184 | 100.00 |
| ALWAYS | 87 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 102 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 103 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 107 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 14 | 14 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| ALWAYS | 140 | 70 | 70 | 100.00 |
| ALWAYS | 270 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 278 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
| ALWAYS | 284 | 5 | 5 | 100.00 |
| ALWAYS | 300 | 32 | 32 | 100.00 |
| ALWAYS | 344 | 10 | 10 | 100.00 |
| ALWAYS | 374 | 19 | 19 | 100.00 |
| ALWAYS | 415 | 8 | 8 | 100.00 |
| ALWAYS | 458 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 506 | 1 | 1 | 100.00 |
86 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_pid
87 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
88 1/1 pid_q <= 0;
Tests: T1 T2 T3
89 end else begin
90 1/1 if (link_reset_i) begin
Tests: T1 T2 T3
91 1/1 pid_q <= 0;
Tests: T1 T2 T3
92 end else begin
93 1/1 pid_q <= pid_d;
Tests: T1 T2 T3
94 end
95 end
96 end
97
98 1/1 assign pid_d = pkt_start_i ? pid_i : pid_q;
Tests: T1 T2 T3
99
100
101 1/1 assign serial_tx_data = data_shift_reg_q[0];
Tests: T1 T2 T3
102 1/1 assign serial_tx_oe = oe_shift_reg_q[0];
Tests: T1 T2 T3
103 1/1 assign serial_tx_se0 = se0_shift_reg_q[0];
Tests: T1 T2 T3
104
105
106 // serialize sync, pid_i, data payload, and crc16
107 1/1 assign bit_history = {serial_tx_data, bit_history_q};
Tests: T1 T2 T3
108 1/1 assign bitstuff = bit_history == 6'b111111;
Tests: T1 T2 T3
109
110 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_bitstuff
111 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
112 1/1 bitstuff_q <= 0;
Tests: T1 T2 T3
113 1/1 bitstuff_q2 <= 0;
Tests: T1 T2 T3
114 1/1 bitstuff_q3 <= 0;
Tests: T1 T2 T3
115 1/1 bitstuff_q4 <= 0;
Tests: T1 T2 T3
116 end else begin
117 1/1 if (link_reset_i) begin
Tests: T1 T2 T3
118 1/1 bitstuff_q <= 0;
Tests: T1 T2 T3
119 1/1 bitstuff_q2 <= 0;
Tests: T1 T2 T3
120 1/1 bitstuff_q3 <= 0;
Tests: T1 T2 T3
121 1/1 bitstuff_q4 <= 0;
Tests: T1 T2 T3
122 end else begin
123 1/1 bitstuff_q <= bitstuff;
Tests: T1 T2 T3
124 1/1 bitstuff_q2 <= bitstuff_q;
Tests: T1 T2 T3
125 1/1 bitstuff_q3 <= bitstuff_q2;
Tests: T1 T2 T3
126 1/1 bitstuff_q4 <= bitstuff_q3;
Tests: T1 T2 T3
127 end
128 end
129 end
130
131 1/1 assign pkt_end = bit_strobe_i && se0_shift_reg_q[1:0] == 2'b01;
Tests: T1 T2 T3
132 1/1 assign pkt_end_o = pkt_end;
Tests: T1 T2 T3
133
134
135 /////////
136 // FSM //
137 /////////
138 always_comb begin : proc_fsm
139 // Default assignments
140 1/1 state_d = state_q;
Tests: T1 T2 T3
141 1/1 data_shift_reg_d = data_shift_reg_q;
Tests: T1 T2 T3
142 1/1 oe_shift_reg_d = oe_shift_reg_q;
Tests: T1 T2 T3
143 1/1 se0_shift_reg_d = se0_shift_reg_q;
Tests: T1 T2 T3
144 1/1 data_payload_d = data_payload_q;
Tests: T1 T2 T3
145 1/1 tx_data_get_d = tx_data_get_q;
Tests: T1 T2 T3
146 1/1 bit_history_d = bit_history_q;
Tests: T1 T2 T3
147 1/1 bit_count_d = bit_count_q;
Tests: T1 T2 T3
148 1/1 test_mode_start = 0;
Tests: T1 T2 T3
149
150 1/1 unique case (state_q)
Tests: T1 T2 T3
151 Idle : begin
152 1/1 if (tx_osc_test_mode_i) begin
Tests: T1 T2 T3
153 1/1 state_d = OscTest;
Tests: T201
154 1/1 test_mode_start = 1;
Tests: T201
155 1/1 end else if (pkt_start_i) begin
Tests: T1 T2 T3
156 1/1 state_d = Sync;
Tests: T1 T2 T18
157 end
MISSING_ELSE
158 end
159
160 Sync : begin
161 1/1 if (byte_strobe_q) begin
Tests: T1 T2 T18
162 1/1 state_d = Pid;
Tests: T1 T2 T18
163 1/1 data_shift_reg_d = 8'b10000000;
Tests: T1 T2 T18
164 1/1 oe_shift_reg_d = 8'b11111111;
Tests: T1 T2 T18
165 1/1 se0_shift_reg_d = 8'b00000000;
Tests: T1 T2 T18
166 end
MISSING_ELSE
167 end
168
169 Pid : begin
170 1/1 if (byte_strobe_q) begin
Tests: T1 T2 T18
171 1/1 if (pid_q[1:0] == 2'b11) begin
Tests: T1 T2 T18
172 1/1 state_d = DataOrCrc160;
Tests: T18 T21 T28
173 end else begin
174 1/1 state_d = Eop;
Tests: T1 T2 T18
175 end
176
177 1/1 data_shift_reg_d = {~pid_q, pid_q};
Tests: T1 T2 T18
178 1/1 oe_shift_reg_d = 8'b11111111;
Tests: T1 T2 T18
179 1/1 se0_shift_reg_d = 8'b00000000;
Tests: T1 T2 T18
180 end
MISSING_ELSE
181 end
182
183 DataOrCrc160 : begin
184 1/1 if (byte_strobe_q) begin
Tests: T18 T21 T28
185 1/1 if (tx_data_avail_i) begin
Tests: T18 T21 T28
186 1/1 state_d = DataOrCrc160;
Tests: T21 T28 T7
187 1/1 data_payload_d = 1;
Tests: T21 T28 T7
188 1/1 tx_data_get_d = 1;
Tests: T21 T28 T7
189 1/1 data_shift_reg_d = tx_data_i;
Tests: T21 T28 T7
190 1/1 oe_shift_reg_d = 8'b11111111;
Tests: T21 T28 T7
191 1/1 se0_shift_reg_d = 8'b00000000;
Tests: T21 T28 T7
192 end else begin
193 1/1 state_d = Crc161;
Tests: T18 T21 T28
194 1/1 data_payload_d = 0;
Tests: T18 T21 T28
195 1/1 tx_data_get_d = 0;
Tests: T18 T21 T28
196 1/1 data_shift_reg_d = ~{crc16_q[8], crc16_q[9], crc16_q[10], crc16_q[11],
Tests: T18 T21 T28
197 crc16_q[12], crc16_q[13], crc16_q[14], crc16_q[15]};
198 1/1 oe_shift_reg_d = 8'b11111111;
Tests: T18 T21 T28
199 1/1 se0_shift_reg_d = 8'b00000000;
Tests: T18 T21 T28
200 end
201 end else begin
202 1/1 tx_data_get_d = 0;
Tests: T18 T21 T28
203 end
204 end
205
206 Crc161 : begin
207 1/1 if (byte_strobe_q) begin
Tests: T18 T21 T28
208 1/1 state_d = Eop;
Tests: T18 T21 T28
209 1/1 data_shift_reg_d = ~{crc16_q[0], crc16_q[1], crc16_q[2], crc16_q[3],
Tests: T18 T21 T28
210 crc16_q[4], crc16_q[5], crc16_q[6], crc16_q[7]};
211 1/1 oe_shift_reg_d = 8'b11111111;
Tests: T18 T21 T28
212 1/1 se0_shift_reg_d = 8'b00000000;
Tests: T18 T21 T28
213 end
MISSING_ELSE
214 end
215
216 Eop : begin
217 1/1 if (byte_strobe_q) begin
Tests: T1 T2 T18
218 1/1 state_d = Idle;
Tests: T1 T2 T18
219 1/1 oe_shift_reg_d = 8'b00000111;
Tests: T1 T2 T18
220 1/1 se0_shift_reg_d = 8'b00000111;
Tests: T1 T2 T18
221 end
MISSING_ELSE
222 end
223
224 OscTest: begin
225 // Oscillator test mode: toggle constantly
226 1/1 if (!tx_osc_test_mode_i && byte_strobe_q) begin
Tests: T201
227 1/1 oe_shift_reg_d = 8'b00000000;
Tests: T201
228 1/1 state_d = Idle;
Tests: T201
229 1/1 end else if (byte_strobe_q) begin
Tests: T201
230 1/1 data_shift_reg_d = 8'b00000000;
Tests: T201
231 1/1 oe_shift_reg_d = 8'b11111111;
Tests: T201
232 1/1 se0_shift_reg_d = 8'b00000000;
Tests: T201
233 end
MISSING_ELSE
234 end
235
236 default: state_d = Idle;
237 endcase
238
239 // Logic closely coupled to the FSM
240 1/1 if (pkt_start_i) begin
Tests: T1 T2 T3
241 // We need to have an inter-packet delay between
242 // 2 and 6.5 bit times (see USB 2.0 spec / 7.1.18.1)
243 // The latency in the rest of the system is approximately (measured)
244 // 3.68 bit-times, so we only introduce 1 bit-time here
245 1/1 bit_count_d = 7; // 8-7 = 1
Tests: T1 T2 T18
246 1/1 bit_history_d = 0;
Tests: T1 T2 T18
247
248 1/1 end else if (bit_strobe_i) begin
Tests: T1 T2 T3
249 // bitstuff
250 1/1 if (bitstuff /* && !serial_tx_se0*/) begin
Tests: T1 T2 T3
251 1/1 bit_history_d = bit_history[5:1];
Tests: T21 T28 T7
252 1/1 data_shift_reg_d[0] = 0;
Tests: T21 T28 T7
253
254 // normal deserialize
255 end else begin
256 1/1 bit_count_d = bit_count_q + 1;
Tests: T1 T2 T3
257
258 1/1 data_shift_reg_d = (data_shift_reg_q >> 1);
Tests: T1 T2 T3
259 1/1 oe_shift_reg_d = (oe_shift_reg_q >> 1);
Tests: T1 T2 T3
260 1/1 se0_shift_reg_d = (se0_shift_reg_q >> 1);
Tests: T1 T2 T3
261
262 1/1 bit_history_d = bit_history[5:1];
Tests: T1 T2 T3
263 end
264 end
MISSING_ELSE
265 end
266
267 `ASSERT(StateValid_A, state_q inside {Idle, Sync, Pid, DataOrCrc160, Crc161, Eop, OscTest})
268
269 always_comb begin : proc_byte_str
270 1/1 if (bit_strobe_i && !bitstuff && !pkt_start_i) begin
Tests: T1 T2 T3
271 1/1 byte_strobe_d = (bit_count_q == 3'b000);
Tests: T1 T2 T3
272 end else begin
273 1/1 byte_strobe_d = 0;
Tests: T1 T2 T3
274 end
275
276 end
277
278 1/1 assign tx_data_get_o = tx_data_get_q;
Tests: T1 T2 T3
279
280 // calculate crc16
281 1/1 assign crc16_invert = serial_tx_data ^ crc16_q[15];
Tests: T1 T2 T3
282
283 always_comb begin : proc_crc16
284 1/1 crc16_d = crc16_q; // default assignment
Tests: T1 T2 T3
285
286 1/1 if (pkt_start_i) begin
Tests: T1 T2 T3
287 1/1 crc16_d = 16'b1111111111111111;
Tests: T1 T2 T18
288 end
MISSING_ELSE
289
290 1/1 if (bit_strobe_i && data_payload_q && !bitstuff_q4 && !pkt_start_i) begin
Tests: T1 T2 T3
291 1/1 crc16_d = {crc16_q[14:0], 1'b0} ^ ({16{crc16_invert}} & 16'b1000000000000101);
Tests: T21 T28 T7
292 end
MISSING_ELSE
293 end
294
295 ///////////////////////
296 // Regular Registers //
297 ///////////////////////
298
299 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_reg
300 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
301 1/1 state_q <= Idle;
Tests: T1 T2 T3
302 1/1 data_payload_q <= 0;
Tests: T1 T2 T3
303 1/1 data_shift_reg_q <= 0;
Tests: T1 T2 T3
304 1/1 oe_shift_reg_q <= 0;
Tests: T1 T2 T3
305 1/1 se0_shift_reg_q <= 0;
Tests: T1 T2 T3
306 1/1 tx_data_get_q <= 0;
Tests: T1 T2 T3
307 1/1 byte_strobe_q <= 0;
Tests: T1 T2 T3
308 1/1 bit_history_q <= 0;
Tests: T1 T2 T3
309 1/1 bit_count_q <= 0;
Tests: T1 T2 T3
310 1/1 crc16_q <= 0;
Tests: T1 T2 T3
311 end else begin
312 1/1 if (link_reset_i) begin
Tests: T1 T2 T3
313 1/1 state_q <= Idle;
Tests: T1 T2 T3
314 1/1 data_payload_q <= 0;
Tests: T1 T2 T3
315 1/1 data_shift_reg_q <= 0;
Tests: T1 T2 T3
316 1/1 oe_shift_reg_q <= 0;
Tests: T1 T2 T3
317 1/1 se0_shift_reg_q <= 0;
Tests: T1 T2 T3
318 1/1 tx_data_get_q <= 0;
Tests: T1 T2 T3
319 1/1 byte_strobe_q <= 0;
Tests: T1 T2 T3
320 1/1 bit_history_q <= 0;
Tests: T1 T2 T3
321 1/1 bit_count_q <= 0;
Tests: T1 T2 T3
322 1/1 crc16_q <= 0;
Tests: T1 T2 T3
323 end else begin
324 1/1 state_q <= state_d;
Tests: T1 T2 T3
325 1/1 data_payload_q <= data_payload_d;
Tests: T1 T2 T3
326 1/1 data_shift_reg_q <= data_shift_reg_d;
Tests: T1 T2 T3
327 1/1 oe_shift_reg_q <= oe_shift_reg_d;
Tests: T1 T2 T3
328 1/1 se0_shift_reg_q <= se0_shift_reg_d;
Tests: T1 T2 T3
329 1/1 tx_data_get_q <= tx_data_get_d;
Tests: T1 T2 T3
330 1/1 byte_strobe_q <= byte_strobe_d;
Tests: T1 T2 T3
331 1/1 bit_history_q <= bit_history_d;
Tests: T1 T2 T3
332 1/1 bit_count_q <= bit_count_d;
Tests: T1 T2 T3
333 1/1 crc16_q <= crc16_d;
Tests: T1 T2 T3
334 end
335 end
336 end
337
338 ///////////////////////////////////
339 // nrzi and differential driving //
340 ///////////////////////////////////
341
342 // Output FSM
343 always_comb begin : proc_out_fsm
344 1/1 out_state_d = out_state_q;
Tests: T1 T2 T3
345 1/1 out_nrzi_en = 1'b0;
Tests: T1 T2 T3
346
347 1/1 unique case (out_state_q)
Tests: T1 T2 T3
348 OsIdle: begin
349 1/1 if (pkt_start_i || test_mode_start) begin
Tests: T1 T2 T3
350 1/1 out_state_d = OsWaitByte;
Tests: T1 T2 T18
351 end
MISSING_ELSE
352 end
353
354 OsWaitByte: begin
355 1/1 if (byte_strobe_q) begin
Tests: T1 T2 T18
356 1/1 out_state_d = OsTransmit;
Tests: T1 T2 T18
357 end
MISSING_ELSE
358 end
359
360 OsTransmit: begin
361 1/1 out_nrzi_en = 1'b1;
Tests: T1 T2 T18
362 1/1 if ((bit_strobe_i && !serial_tx_oe)) begin
Tests: T1 T2 T18
363 1/1 out_state_d = OsIdle;
Tests: T1 T2 T18
364 end
MISSING_ELSE
365 end
366
367 default : out_state_d = OsIdle;
368 endcase
369 end
370
371 `ASSERT(OutStateValid_A, out_state_q inside {OsIdle, OsWaitByte, OsTransmit})
372
373 always_comb begin : proc_diff
374 1/1 usb_d_d = usb_d_q;
Tests: T1 T2 T3
375 1/1 usb_se0_d = usb_se0_q;
Tests: T1 T2 T3
376 1/1 oe_d = oe_q;
Tests: T1 T2 T3
377 1/1 dp_eop_d = dp_eop_q;
Tests: T1 T2 T3
378
379 1/1 if (pkt_start_i) begin
Tests: T1 T2 T3
380 1/1 usb_d_d = 1; // J -> first bit will be K (start of sync)
Tests: T1 T2 T18
381 1/1 dp_eop_d = 3'b100; // Eop: {SE0, SE0, J}
Tests: T1 T2 T18
382
383 1/1 end else if (bit_strobe_i && out_nrzi_en) begin
Tests: T1 T2 T3
384 1/1 oe_d = serial_tx_oe;
Tests: T1 T2 T18
385
386 1/1 if (serial_tx_se0) begin
Tests: T1 T2 T18
387 // Eop
388 1/1 dp_eop_d = dp_eop_q >> 1;
Tests: T1 T2 T18
389
390 1/1 if (dp_eop_q[0]) begin
Tests: T1 T2 T18
391 // last bit of Eop: J
392 1/1 usb_d_d = 1;
Tests: T1 T2 T18
393 1/1 usb_se0_d = 0;
Tests: T1 T2 T18
394 end else begin
395 // first two bits of Eop: SE0
396 1/1 usb_se0_d = 1;
Tests: T1 T2 T18
397 end
398
399 1/1 end else if (serial_tx_data) begin
Tests: T1 T2 T18
400 // value should stay the same, do nothing
401
402 end else begin
403 1/1 usb_d_d = !usb_d_q;
Tests: T1 T2 T18
404 end
405 end
MISSING_ELSE
406
407 // Set to J state when OE=0 to avoid
408 // glitches
409 1/1 if (!oe_d) begin
Tests: T1 T2 T3
410 1/1 usb_d_d = 1;
Tests: T1 T2 T3
411 end
MISSING_ELSE
412 end
413
414 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_diff_reg
415 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
416 1/1 dp_eop_q <= 0;
Tests: T1 T2 T3
417 1/1 out_state_q <= OsIdle;
Tests: T1 T2 T3
418 end else begin
419 1/1 if (link_reset_i) begin
Tests: T1 T2 T3
420 1/1 dp_eop_q <= 0;
Tests: T1 T2 T3
421 1/1 out_state_q <= OsIdle;
Tests: T1 T2 T3
422 end else begin
423 1/1 dp_eop_q <= dp_eop_d;
Tests: T1 T2 T3
424 1/1 out_state_q <= out_state_d;
Tests: T1 T2 T3
425 end
426 end
427 end
428
429
430 prim_flop u_oe_flop (
431 .clk_i,
432 .rst_ni,
433 .d_i(link_reset_i ? 1'b0 : oe_d),
434 .q_o(oe_q)
435 );
436
437 prim_flop #(
438 .ResetValue(1) // J state = idle state
439 ) u_usb_d_flop (
440 .clk_i,
441 .rst_ni,
442 .d_i(link_reset_i ? 1'b1 : usb_d_d),
443 .q_o(usb_d_q)
444 );
445
446 prim_flop u_usb_se0_flop (
447 .clk_i,
448 .rst_ni,
449 .d_i(link_reset_i ? 1'b0 : usb_se0_d),
450 .q_o(usb_se0_q)
451 );
452
453 // Handle the D+ / D- pin flip on the USB side, and provide both the
454 // dp/dn and d/se0 interfaces, for compatibility with multiple driver types.
455 logic usb_se0_flipped, usb_dp_flipped, usb_dn_flipped;
456
457 always_comb begin
458 1/1 if (link_reset_i) begin
Tests: T1 T2 T3
459 1/1 usb_se0_flipped = 1'b0;
Tests: T1 T2 T3
460 1/1 usb_dp_flipped = !cfg_pinflip_i;
Tests: T1 T2 T3
461 1/1 usb_dn_flipped = cfg_pinflip_i;
Tests: T1 T2 T3
462 end else begin
463 1/1 usb_se0_flipped = usb_se0_d;
Tests: T1 T2 T3
464 1/1 usb_dp_flipped = (cfg_pinflip_i ? ~usb_d_d : usb_d_d) & ~usb_se0_d;
Tests: T1 T2 T3
465 1/1 usb_dn_flipped = (cfg_pinflip_i ? usb_d_d : ~usb_d_d) & ~usb_se0_d;
Tests: T1 T2 T3
466 end
467 end
468
469 // Use registered outputs for the I/Os
470 prim_flop #(
471 .ResetValue(1) // J state = idle state
472 ) u_usb_d_o_flop (
473 .clk_i,
474 .rst_ni,
475 .d_i(usb_dp_flipped), // Note: single-ended 'D' output mirrors D+
476 .q_o(usb_d_o)
477 );
478
479 prim_flop #(
480 .ResetValue(0) // J state = idle state
481 ) u_usb_se0_o_flop (
482 .clk_i,
483 .rst_ni,
484 .d_i(usb_se0_flipped),
485 .q_o(usb_se0_o)
486 );
487
488 prim_flop #(
489 .ResetValue(1) // J state = idle state
490 ) u_usb_dp_o_flop (
491 .clk_i,
492 .rst_ni,
493 .d_i(usb_dp_flipped),
494 .q_o(usb_dp_o)
495 );
496
497 prim_flop #(
498 .ResetValue(0) // J state = idle state
499 ) u_usb_dn_o_flop (
500 .clk_i,
501 .rst_ni,
502 .d_i(usb_dn_flipped),
503 .q_o(usb_dn_o)
504 );
505
506 1/1 assign usb_oe_o = oe_q;
Tests: T1 T2 T3
Cond Coverage for Module :
usb_fs_tx
| Total | Covered | Percent |
|---|
| Conditions | 54 | 53 | 98.15 |
| Logical | 54 | 53 | 98.15 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 98
EXPRESSION (pkt_start_i ? pid_i : pid_q)
-----1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T18 |
LINE 108
EXPRESSION (bit_history == 6'b111111)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T21,T28,T7 |
LINE 131
EXPRESSION (bit_strobe_i && (se0_shift_reg_q[1:0] == 2'b1))
------1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T18 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T18 |
LINE 131
SUB-EXPRESSION (se0_shift_reg_q[1:0] == 2'b1)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T18 |
LINE 171
EXPRESSION (pid_q[1:0] == 2'b11)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T18 |
| 1 | Covered | T18,T21,T28 |
LINE 226
EXPRESSION (((!tx_osc_test_mode_i)) && byte_strobe_q)
-----------1----------- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T201 |
| 1 | 0 | Covered | T201 |
| 1 | 1 | Covered | T201 |
LINE 270
EXPRESSION (bit_strobe_i && ((!bitstuff)) && ((!pkt_start_i)))
------1----- ------2------ --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T21,T28,T7 |
| 1 | 1 | 0 | Covered | T1,T2,T18 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 271
EXPRESSION (bit_count_q == 3'b0)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 281
EXPRESSION (serial_tx_data ^ crc16_q[15])
-------1------ -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T18 |
| 1 | 0 | Covered | T21,T28,T7 |
| 1 | 1 | Covered | T1,T2,T18 |
LINE 290
EXPRESSION (bit_strobe_i && data_payload_q && ((!bitstuff_q4)) && ((!pkt_start_i)))
------1----- -------2------ --------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T21,T28,T7 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T21,T28,T7 |
| 1 | 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | 1 | Covered | T21,T28,T7 |
LINE 349
EXPRESSION (pkt_start_i || test_mode_start)
-----1----- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T201 |
| 1 | 0 | Covered | T1,T2,T18 |
LINE 362
EXPRESSION (bit_strobe_i && ((!serial_tx_oe)))
------1----- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T18 |
| 1 | 0 | Covered | T1,T2,T18 |
| 1 | 1 | Covered | T1,T2,T18 |
LINE 383
EXPRESSION (bit_strobe_i && out_nrzi_en)
------1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T18 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T18 |
LINE 430
EXPRESSION (link_reset_i ? 1'b0 : oe_d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 439
EXPRESSION (link_reset_i ? 1'b1 : usb_d_d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 446
EXPRESSION (link_reset_i ? 1'b0 : usb_se0_d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 464
EXPRESSION ((cfg_pinflip_i ? ((~usb_d_d)) : usb_d_d) & ((~usb_se0_d)))
--------------------1------------------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T18 |
| 1 | 0 | Covered | T21,T28,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 464
SUB-EXPRESSION (cfg_pinflip_i ? ((~usb_d_d)) : usb_d_d)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T44,T45,T202 |
LINE 465
EXPRESSION ((cfg_pinflip_i ? usb_d_d : ((~usb_d_d))) & ((~usb_se0_d)))
--------------------1------------------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T18 |
| 1 | 1 | Covered | T1,T2,T18 |
LINE 465
SUB-EXPRESSION (cfg_pinflip_i ? usb_d_d : ((~usb_d_d)))
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T44,T45,T202 |
FSM Coverage for Module :
usb_fs_tx
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
7 |
7 |
100.00 |
(Not included in score) |
| Transitions |
13 |
11 |
84.62 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| Crc161 |
193 |
Covered |
T18,T21,T28 |
| DataOrCrc160 |
172 |
Covered |
T18,T21,T28 |
| Eop |
174 |
Covered |
T1,T2,T18 |
| Idle |
313 |
Covered |
T1,T2,T3 |
| OscTest |
153 |
Covered |
T201 |
| Pid |
162 |
Covered |
T1,T2,T18 |
| Sync |
156 |
Covered |
T1,T2,T18 |
| transitions | Line No. | Covered | Tests |
| Crc161->Eop |
208 |
Covered |
T18,T21,T28 |
| Crc161->Idle |
313 |
Not Covered |
|
| DataOrCrc160->Crc161 |
193 |
Covered |
T18,T21,T28 |
| DataOrCrc160->Idle |
313 |
Covered |
T203,T204,T205 |
| Eop->Idle |
313 |
Covered |
T1,T2,T18 |
| Idle->OscTest |
153 |
Covered |
T201 |
| Idle->Sync |
156 |
Covered |
T1,T2,T18 |
| OscTest->Idle |
313 |
Covered |
T201 |
| Pid->DataOrCrc160 |
172 |
Covered |
T18,T21,T28 |
| Pid->Eop |
174 |
Covered |
T1,T2,T18 |
| Pid->Idle |
313 |
Covered |
T206,T207,T208 |
| Sync->Idle |
313 |
Not Covered |
|
| Sync->Pid |
162 |
Covered |
T1,T2,T18 |
Summary for FSM :: out_state_q
| Total | Covered | Percent | |
| States |
3 |
3 |
100.00 |
(Not included in score) |
| Transitions |
4 |
3 |
75.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: out_state_q
| states | Line No. | Covered | Tests |
| OsIdle |
421 |
Covered |
T1,T2,T3 |
| OsTransmit |
356 |
Covered |
T1,T2,T18 |
| OsWaitByte |
350 |
Covered |
T1,T2,T18 |
| transitions | Line No. | Covered | Tests |
| OsIdle->OsWaitByte |
350 |
Covered |
T1,T2,T18 |
| OsTransmit->OsIdle |
421 |
Covered |
T1,T2,T18 |
| OsWaitByte->OsIdle |
421 |
Not Covered |
|
| OsWaitByte->OsTransmit |
356 |
Covered |
T1,T2,T18 |
Branch Coverage for Module :
usb_fs_tx
| Line No. | Total | Covered | Percent |
| Branches |
|
66 |
64 |
96.97 |
| TERNARY |
98 |
2 |
2 |
100.00 |
| TERNARY |
430 |
2 |
2 |
100.00 |
| TERNARY |
439 |
2 |
2 |
100.00 |
| TERNARY |
446 |
2 |
2 |
100.00 |
| IF |
87 |
3 |
3 |
100.00 |
| IF |
111 |
3 |
3 |
100.00 |
| CASE |
150 |
19 |
18 |
94.74 |
| IF |
240 |
4 |
4 |
100.00 |
| IF |
270 |
2 |
2 |
100.00 |
| IF |
286 |
2 |
2 |
100.00 |
| IF |
290 |
2 |
2 |
100.00 |
| IF |
300 |
3 |
3 |
100.00 |
| CASE |
347 |
7 |
6 |
85.71 |
| IF |
379 |
6 |
6 |
100.00 |
| IF |
409 |
2 |
2 |
100.00 |
| IF |
415 |
3 |
3 |
100.00 |
| IF |
458 |
2 |
2 |
100.00 |
98 assign pid_d = pkt_start_i ? pid_i : pid_q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T18 |
| 0 |
Covered |
T1,T2,T3 |
430 prim_flop u_oe_flop (
431 .clk_i,
432 .rst_ni,
433 .d_i(link_reset_i ? 1'b0 : oe_d),
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
439 ) u_usb_d_flop (
440 .clk_i,
441 .rst_ni,
442 .d_i(link_reset_i ? 1'b1 : usb_d_d),
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
446 prim_flop u_usb_se0_flop (
447 .clk_i,
448 .rst_ni,
449 .d_i(link_reset_i ? 1'b0 : usb_se0_d),
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
87 if (!rst_ni) begin
-1-
88 pid_q <= 0;
==>
89 end else begin
90 if (link_reset_i) begin
-2-
91 pid_q <= 0;
==>
92 end else begin
93 pid_q <= pid_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (!rst_ni) begin
-1-
112 bitstuff_q <= 0;
==>
113 bitstuff_q2 <= 0;
114 bitstuff_q3 <= 0;
115 bitstuff_q4 <= 0;
116 end else begin
117 if (link_reset_i) begin
-2-
118 bitstuff_q <= 0;
==>
119 bitstuff_q2 <= 0;
120 bitstuff_q3 <= 0;
121 bitstuff_q4 <= 0;
122 end else begin
123 bitstuff_q <= bitstuff;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
150 unique case (state_q)
-1-
151 Idle : begin
152 if (tx_osc_test_mode_i) begin
-2-
153 state_d = OscTest;
==>
154 test_mode_start = 1;
155 end else if (pkt_start_i) begin
-3-
156 state_d = Sync;
==>
157 end
MISSING_ELSE
==>
158 end
159
160 Sync : begin
161 if (byte_strobe_q) begin
-4-
162 state_d = Pid;
==>
163 data_shift_reg_d = 8'b10000000;
164 oe_shift_reg_d = 8'b11111111;
165 se0_shift_reg_d = 8'b00000000;
166 end
MISSING_ELSE
==>
167 end
168
169 Pid : begin
170 if (byte_strobe_q) begin
-5-
171 if (pid_q[1:0] == 2'b11) begin
-6-
172 state_d = DataOrCrc160;
==>
173 end else begin
174 state_d = Eop;
==>
175 end
176
177 data_shift_reg_d = {~pid_q, pid_q};
178 oe_shift_reg_d = 8'b11111111;
179 se0_shift_reg_d = 8'b00000000;
180 end
MISSING_ELSE
==>
181 end
182
183 DataOrCrc160 : begin
184 if (byte_strobe_q) begin
-7-
185 if (tx_data_avail_i) begin
-8-
186 state_d = DataOrCrc160;
==>
187 data_payload_d = 1;
188 tx_data_get_d = 1;
189 data_shift_reg_d = tx_data_i;
190 oe_shift_reg_d = 8'b11111111;
191 se0_shift_reg_d = 8'b00000000;
192 end else begin
193 state_d = Crc161;
==>
194 data_payload_d = 0;
195 tx_data_get_d = 0;
196 data_shift_reg_d = ~{crc16_q[8], crc16_q[9], crc16_q[10], crc16_q[11],
197 crc16_q[12], crc16_q[13], crc16_q[14], crc16_q[15]};
198 oe_shift_reg_d = 8'b11111111;
199 se0_shift_reg_d = 8'b00000000;
200 end
201 end else begin
202 tx_data_get_d = 0;
==>
203 end
204 end
205
206 Crc161 : begin
207 if (byte_strobe_q) begin
-9-
208 state_d = Eop;
==>
209 data_shift_reg_d = ~{crc16_q[0], crc16_q[1], crc16_q[2], crc16_q[3],
210 crc16_q[4], crc16_q[5], crc16_q[6], crc16_q[7]};
211 oe_shift_reg_d = 8'b11111111;
212 se0_shift_reg_d = 8'b00000000;
213 end
MISSING_ELSE
==>
214 end
215
216 Eop : begin
217 if (byte_strobe_q) begin
-10-
218 state_d = Idle;
==>
219 oe_shift_reg_d = 8'b00000111;
220 se0_shift_reg_d = 8'b00000111;
221 end
MISSING_ELSE
==>
222 end
223
224 OscTest: begin
225 // Oscillator test mode: toggle constantly
226 if (!tx_osc_test_mode_i && byte_strobe_q) begin
-11-
227 oe_shift_reg_d = 8'b00000000;
==>
228 state_d = Idle;
229 end else if (byte_strobe_q) begin
-12-
230 data_shift_reg_d = 8'b00000000;
==>
231 oe_shift_reg_d = 8'b11111111;
232 se0_shift_reg_d = 8'b00000000;
233 end
MISSING_ELSE
==>
234 end
235
236 default: state_d = Idle;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | Status | Tests |
| Idle |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T201 |
| Idle |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T18 |
| Idle |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| Sync |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T18 |
| Sync |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T18 |
| Pid |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T18,T21,T28 |
| Pid |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T18 |
| Pid |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T18 |
| DataOrCrc160 |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
Covered |
T21,T28,T7 |
| DataOrCrc160 |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
Covered |
T18,T21,T28 |
| DataOrCrc160 |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T18,T21,T28 |
| Crc161 |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T18,T21,T28 |
| Crc161 |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T18,T21,T28 |
| Eop |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T1,T2,T18 |
| Eop |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
Covered |
T1,T2,T18 |
| OscTest |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T201 |
| OscTest |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
Covered |
T201 |
| OscTest |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
Covered |
T201 |
| default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
240 if (pkt_start_i) begin
-1-
241 // We need to have an inter-packet delay between
242 // 2 and 6.5 bit times (see USB 2.0 spec / 7.1.18.1)
243 // The latency in the rest of the system is approximately (measured)
244 // 3.68 bit-times, so we only introduce 1 bit-time here
245 bit_count_d = 7; // 8-7 = 1
==>
246 bit_history_d = 0;
247
248 end else if (bit_strobe_i) begin
-2-
249 // bitstuff
250 if (bitstuff /* && !serial_tx_se0*/) begin
-3-
251 bit_history_d = bit_history[5:1];
==>
252 data_shift_reg_d[0] = 0;
253
254 // normal deserialize
255 end else begin
256 bit_count_d = bit_count_q + 1;
==>
257
258 data_shift_reg_d = (data_shift_reg_q >> 1);
259 oe_shift_reg_d = (oe_shift_reg_q >> 1);
260 se0_shift_reg_d = (se0_shift_reg_q >> 1);
261
262 bit_history_d = bit_history[5:1];
263 end
264 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T18 |
| 0 |
1 |
1 |
Covered |
T21,T28,T7 |
| 0 |
1 |
0 |
Covered |
T1,T2,T3 |
| 0 |
0 |
- |
Covered |
T1,T2,T3 |
270 if (bit_strobe_i && !bitstuff && !pkt_start_i) begin
-1-
271 byte_strobe_d = (bit_count_q == 3'b000);
==>
272 end else begin
273 byte_strobe_d = 0;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
286 if (pkt_start_i) begin
-1-
287 crc16_d = 16'b1111111111111111;
==>
288 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T18 |
| 0 |
Covered |
T1,T2,T3 |
290 if (bit_strobe_i && data_payload_q && !bitstuff_q4 && !pkt_start_i) begin
-1-
291 crc16_d = {crc16_q[14:0], 1'b0} ^ ({16{crc16_invert}} & 16'b1000000000000101);
==>
292 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T21,T28,T7 |
| 0 |
Covered |
T1,T2,T3 |
300 if (!rst_ni) begin
-1-
301 state_q <= Idle;
==>
302 data_payload_q <= 0;
303 data_shift_reg_q <= 0;
304 oe_shift_reg_q <= 0;
305 se0_shift_reg_q <= 0;
306 tx_data_get_q <= 0;
307 byte_strobe_q <= 0;
308 bit_history_q <= 0;
309 bit_count_q <= 0;
310 crc16_q <= 0;
311 end else begin
312 if (link_reset_i) begin
-2-
313 state_q <= Idle;
==>
314 data_payload_q <= 0;
315 data_shift_reg_q <= 0;
316 oe_shift_reg_q <= 0;
317 se0_shift_reg_q <= 0;
318 tx_data_get_q <= 0;
319 byte_strobe_q <= 0;
320 bit_history_q <= 0;
321 bit_count_q <= 0;
322 crc16_q <= 0;
323 end else begin
324 state_q <= state_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
347 unique case (out_state_q)
-1-
348 OsIdle: begin
349 if (pkt_start_i || test_mode_start) begin
-2-
350 out_state_d = OsWaitByte;
==>
351 end
MISSING_ELSE
==>
352 end
353
354 OsWaitByte: begin
355 if (byte_strobe_q) begin
-3-
356 out_state_d = OsTransmit;
==>
357 end
MISSING_ELSE
==>
358 end
359
360 OsTransmit: begin
361 out_nrzi_en = 1'b1;
362 if ((bit_strobe_i && !serial_tx_oe)) begin
-4-
363 out_state_d = OsIdle;
==>
364 end
MISSING_ELSE
==>
365 end
366
367 default : out_state_d = OsIdle;
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| OsIdle |
1 |
- |
- |
Covered |
T1,T2,T18 |
| OsIdle |
0 |
- |
- |
Covered |
T1,T2,T3 |
| OsWaitByte |
- |
1 |
- |
Covered |
T1,T2,T18 |
| OsWaitByte |
- |
0 |
- |
Covered |
T1,T2,T18 |
| OsTransmit |
- |
- |
1 |
Covered |
T1,T2,T18 |
| OsTransmit |
- |
- |
0 |
Covered |
T1,T2,T18 |
| default |
- |
- |
- |
Not Covered |
|
379 if (pkt_start_i) begin
-1-
380 usb_d_d = 1; // J -> first bit will be K (start of sync)
==>
381 dp_eop_d = 3'b100; // Eop: {SE0, SE0, J}
382
383 end else if (bit_strobe_i && out_nrzi_en) begin
-2-
384 oe_d = serial_tx_oe;
385
386 if (serial_tx_se0) begin
-3-
387 // Eop
388 dp_eop_d = dp_eop_q >> 1;
389
390 if (dp_eop_q[0]) begin
-4-
391 // last bit of Eop: J
392 usb_d_d = 1;
==>
393 usb_se0_d = 0;
394 end else begin
395 // first two bits of Eop: SE0
396 usb_se0_d = 1;
==>
397 end
398
399 end else if (serial_tx_data) begin
-5-
==>
400 // value should stay the same, do nothing
401
402 end else begin
403 usb_d_d = !usb_d_q;
==>
404 end
405 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | Status | Tests |
| 1 |
- |
- |
- |
- |
Covered |
T1,T2,T18 |
| 0 |
1 |
1 |
1 |
- |
Covered |
T1,T2,T18 |
| 0 |
1 |
1 |
0 |
- |
Covered |
T1,T2,T18 |
| 0 |
1 |
0 |
- |
1 |
Covered |
T1,T2,T18 |
| 0 |
1 |
0 |
- |
0 |
Covered |
T1,T2,T18 |
| 0 |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
409 if (!oe_d) begin
-1-
410 usb_d_d = 1;
==>
411 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T18 |
415 if (!rst_ni) begin
-1-
416 dp_eop_q <= 0;
==>
417 out_state_q <= OsIdle;
418 end else begin
419 if (link_reset_i) begin
-2-
420 dp_eop_q <= 0;
==>
421 out_state_q <= OsIdle;
422 end else begin
423 dp_eop_q <= dp_eop_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
458 if (link_reset_i) begin
-1-
459 usb_se0_flipped = 1'b0;
==>
460 usb_dp_flipped = !cfg_pinflip_i;
461 usb_dn_flipped = cfg_pinflip_i;
462 end else begin
463 usb_se0_flipped = usb_se0_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
usb_fs_tx
Assertion Details
OutStateValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
582830002 |
582531406 |
0 |
0 |
| T1 |
7336 |
7239 |
0 |
0 |
| T2 |
8639 |
8540 |
0 |
0 |
| T3 |
192249 |
192153 |
0 |
0 |
| T16 |
7026 |
6947 |
0 |
0 |
| T17 |
7470 |
7397 |
0 |
0 |
| T18 |
18808 |
18754 |
0 |
0 |
| T19 |
7109 |
7043 |
0 |
0 |
| T20 |
23009 |
22951 |
0 |
0 |
| T21 |
51767 |
51684 |
0 |
0 |
| T22 |
2047 |
1954 |
0 |
0 |
StateValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
582830002 |
582531406 |
0 |
0 |
| T1 |
7336 |
7239 |
0 |
0 |
| T2 |
8639 |
8540 |
0 |
0 |
| T3 |
192249 |
192153 |
0 |
0 |
| T16 |
7026 |
6947 |
0 |
0 |
| T17 |
7470 |
7397 |
0 |
0 |
| T18 |
18808 |
18754 |
0 |
0 |
| T19 |
7109 |
7043 |
0 |
0 |
| T20 |
23009 |
22951 |
0 |
0 |
| T21 |
51767 |
51684 |
0 |
0 |
| T22 |
2047 |
1954 |
0 |
0 |
Line Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 184 | 184 | 100.00 |
| ALWAYS | 87 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 102 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 103 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 107 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
| ALWAYS | 111 | 14 | 14 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| ALWAYS | 140 | 70 | 70 | 100.00 |
| ALWAYS | 270 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 278 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
| ALWAYS | 284 | 5 | 5 | 100.00 |
| ALWAYS | 300 | 32 | 32 | 100.00 |
| ALWAYS | 344 | 10 | 10 | 100.00 |
| ALWAYS | 374 | 19 | 19 | 100.00 |
| ALWAYS | 415 | 8 | 8 | 100.00 |
| ALWAYS | 458 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 506 | 1 | 1 | 100.00 |
86 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_pid
87 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
88 1/1 pid_q <= 0;
Tests: T1 T2 T3
89 end else begin
90 1/1 if (link_reset_i) begin
Tests: T1 T2 T3
91 1/1 pid_q <= 0;
Tests: T1 T2 T3
92 end else begin
93 1/1 pid_q <= pid_d;
Tests: T1 T2 T3
94 end
95 end
96 end
97
98 1/1 assign pid_d = pkt_start_i ? pid_i : pid_q;
Tests: T1 T2 T3
99
100
101 1/1 assign serial_tx_data = data_shift_reg_q[0];
Tests: T1 T2 T3
102 1/1 assign serial_tx_oe = oe_shift_reg_q[0];
Tests: T1 T2 T3
103 1/1 assign serial_tx_se0 = se0_shift_reg_q[0];
Tests: T1 T2 T3
104
105
106 // serialize sync, pid_i, data payload, and crc16
107 1/1 assign bit_history = {serial_tx_data, bit_history_q};
Tests: T1 T2 T3
108 1/1 assign bitstuff = bit_history == 6'b111111;
Tests: T1 T2 T3
109
110 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_bitstuff
111 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
112 1/1 bitstuff_q <= 0;
Tests: T1 T2 T3
113 1/1 bitstuff_q2 <= 0;
Tests: T1 T2 T3
114 1/1 bitstuff_q3 <= 0;
Tests: T1 T2 T3
115 1/1 bitstuff_q4 <= 0;
Tests: T1 T2 T3
116 end else begin
117 1/1 if (link_reset_i) begin
Tests: T1 T2 T3
118 1/1 bitstuff_q <= 0;
Tests: T1 T2 T3
119 1/1 bitstuff_q2 <= 0;
Tests: T1 T2 T3
120 1/1 bitstuff_q3 <= 0;
Tests: T1 T2 T3
121 1/1 bitstuff_q4 <= 0;
Tests: T1 T2 T3
122 end else begin
123 1/1 bitstuff_q <= bitstuff;
Tests: T1 T2 T3
124 1/1 bitstuff_q2 <= bitstuff_q;
Tests: T1 T2 T3
125 1/1 bitstuff_q3 <= bitstuff_q2;
Tests: T1 T2 T3
126 1/1 bitstuff_q4 <= bitstuff_q3;
Tests: T1 T2 T3
127 end
128 end
129 end
130
131 1/1 assign pkt_end = bit_strobe_i && se0_shift_reg_q[1:0] == 2'b01;
Tests: T1 T2 T3
132 1/1 assign pkt_end_o = pkt_end;
Tests: T1 T2 T3
133
134
135 /////////
136 // FSM //
137 /////////
138 always_comb begin : proc_fsm
139 // Default assignments
140 1/1 state_d = state_q;
Tests: T1 T2 T3
141 1/1 data_shift_reg_d = data_shift_reg_q;
Tests: T1 T2 T3
142 1/1 oe_shift_reg_d = oe_shift_reg_q;
Tests: T1 T2 T3
143 1/1 se0_shift_reg_d = se0_shift_reg_q;
Tests: T1 T2 T3
144 1/1 data_payload_d = data_payload_q;
Tests: T1 T2 T3
145 1/1 tx_data_get_d = tx_data_get_q;
Tests: T1 T2 T3
146 1/1 bit_history_d = bit_history_q;
Tests: T1 T2 T3
147 1/1 bit_count_d = bit_count_q;
Tests: T1 T2 T3
148 1/1 test_mode_start = 0;
Tests: T1 T2 T3
149
150 1/1 unique case (state_q)
Tests: T1 T2 T3
151 Idle : begin
152 1/1 if (tx_osc_test_mode_i) begin
Tests: T1 T2 T3
153 1/1 state_d = OscTest;
Tests: T201
154 1/1 test_mode_start = 1;
Tests: T201
155 1/1 end else if (pkt_start_i) begin
Tests: T1 T2 T3
156 1/1 state_d = Sync;
Tests: T1 T2 T18
157 end
MISSING_ELSE
158 end
159
160 Sync : begin
161 1/1 if (byte_strobe_q) begin
Tests: T1 T2 T18
162 1/1 state_d = Pid;
Tests: T1 T2 T18
163 1/1 data_shift_reg_d = 8'b10000000;
Tests: T1 T2 T18
164 1/1 oe_shift_reg_d = 8'b11111111;
Tests: T1 T2 T18
165 1/1 se0_shift_reg_d = 8'b00000000;
Tests: T1 T2 T18
166 end
MISSING_ELSE
167 end
168
169 Pid : begin
170 1/1 if (byte_strobe_q) begin
Tests: T1 T2 T18
171 1/1 if (pid_q[1:0] == 2'b11) begin
Tests: T1 T2 T18
172 1/1 state_d = DataOrCrc160;
Tests: T18 T21 T28
173 end else begin
174 1/1 state_d = Eop;
Tests: T1 T2 T18
175 end
176
177 1/1 data_shift_reg_d = {~pid_q, pid_q};
Tests: T1 T2 T18
178 1/1 oe_shift_reg_d = 8'b11111111;
Tests: T1 T2 T18
179 1/1 se0_shift_reg_d = 8'b00000000;
Tests: T1 T2 T18
180 end
MISSING_ELSE
181 end
182
183 DataOrCrc160 : begin
184 1/1 if (byte_strobe_q) begin
Tests: T18 T21 T28
185 1/1 if (tx_data_avail_i) begin
Tests: T18 T21 T28
186 1/1 state_d = DataOrCrc160;
Tests: T21 T28 T7
187 1/1 data_payload_d = 1;
Tests: T21 T28 T7
188 1/1 tx_data_get_d = 1;
Tests: T21 T28 T7
189 1/1 data_shift_reg_d = tx_data_i;
Tests: T21 T28 T7
190 1/1 oe_shift_reg_d = 8'b11111111;
Tests: T21 T28 T7
191 1/1 se0_shift_reg_d = 8'b00000000;
Tests: T21 T28 T7
192 end else begin
193 1/1 state_d = Crc161;
Tests: T18 T21 T28
194 1/1 data_payload_d = 0;
Tests: T18 T21 T28
195 1/1 tx_data_get_d = 0;
Tests: T18 T21 T28
196 1/1 data_shift_reg_d = ~{crc16_q[8], crc16_q[9], crc16_q[10], crc16_q[11],
Tests: T18 T21 T28
197 crc16_q[12], crc16_q[13], crc16_q[14], crc16_q[15]};
198 1/1 oe_shift_reg_d = 8'b11111111;
Tests: T18 T21 T28
199 1/1 se0_shift_reg_d = 8'b00000000;
Tests: T18 T21 T28
200 end
201 end else begin
202 1/1 tx_data_get_d = 0;
Tests: T18 T21 T28
203 end
204 end
205
206 Crc161 : begin
207 1/1 if (byte_strobe_q) begin
Tests: T18 T21 T28
208 1/1 state_d = Eop;
Tests: T18 T21 T28
209 1/1 data_shift_reg_d = ~{crc16_q[0], crc16_q[1], crc16_q[2], crc16_q[3],
Tests: T18 T21 T28
210 crc16_q[4], crc16_q[5], crc16_q[6], crc16_q[7]};
211 1/1 oe_shift_reg_d = 8'b11111111;
Tests: T18 T21 T28
212 1/1 se0_shift_reg_d = 8'b00000000;
Tests: T18 T21 T28
213 end
MISSING_ELSE
214 end
215
216 Eop : begin
217 1/1 if (byte_strobe_q) begin
Tests: T1 T2 T18
218 1/1 state_d = Idle;
Tests: T1 T2 T18
219 1/1 oe_shift_reg_d = 8'b00000111;
Tests: T1 T2 T18
220 1/1 se0_shift_reg_d = 8'b00000111;
Tests: T1 T2 T18
221 end
MISSING_ELSE
222 end
223
224 OscTest: begin
225 // Oscillator test mode: toggle constantly
226 1/1 if (!tx_osc_test_mode_i && byte_strobe_q) begin
Tests: T201
227 1/1 oe_shift_reg_d = 8'b00000000;
Tests: T201
228 1/1 state_d = Idle;
Tests: T201
229 1/1 end else if (byte_strobe_q) begin
Tests: T201
230 1/1 data_shift_reg_d = 8'b00000000;
Tests: T201
231 1/1 oe_shift_reg_d = 8'b11111111;
Tests: T201
232 1/1 se0_shift_reg_d = 8'b00000000;
Tests: T201
233 end
MISSING_ELSE
234 end
235
236 default: state_d = Idle;
Exclude Annotation: VC_COV_UNR
237 endcase
238
239 // Logic closely coupled to the FSM
240 1/1 if (pkt_start_i) begin
Tests: T1 T2 T3
241 // We need to have an inter-packet delay between
242 // 2 and 6.5 bit times (see USB 2.0 spec / 7.1.18.1)
243 // The latency in the rest of the system is approximately (measured)
244 // 3.68 bit-times, so we only introduce 1 bit-time here
245 1/1 bit_count_d = 7; // 8-7 = 1
Tests: T1 T2 T18
246 1/1 bit_history_d = 0;
Tests: T1 T2 T18
247
248 1/1 end else if (bit_strobe_i) begin
Tests: T1 T2 T3
249 // bitstuff
250 1/1 if (bitstuff /* && !serial_tx_se0*/) begin
Tests: T1 T2 T3
251 1/1 bit_history_d = bit_history[5:1];
Tests: T21 T28 T7
252 1/1 data_shift_reg_d[0] = 0;
Tests: T21 T28 T7
253
254 // normal deserialize
255 end else begin
256 1/1 bit_count_d = bit_count_q + 1;
Tests: T1 T2 T3
257
258 1/1 data_shift_reg_d = (data_shift_reg_q >> 1);
Tests: T1 T2 T3
259 1/1 oe_shift_reg_d = (oe_shift_reg_q >> 1);
Tests: T1 T2 T3
260 1/1 se0_shift_reg_d = (se0_shift_reg_q >> 1);
Tests: T1 T2 T3
261
262 1/1 bit_history_d = bit_history[5:1];
Tests: T1 T2 T3
263 end
264 end
MISSING_ELSE
265 end
266
267 `ASSERT(StateValid_A, state_q inside {Idle, Sync, Pid, DataOrCrc160, Crc161, Eop, OscTest})
268
269 always_comb begin : proc_byte_str
270 1/1 if (bit_strobe_i && !bitstuff && !pkt_start_i) begin
Tests: T1 T2 T3
271 1/1 byte_strobe_d = (bit_count_q == 3'b000);
Tests: T1 T2 T3
272 end else begin
273 1/1 byte_strobe_d = 0;
Tests: T1 T2 T3
274 end
275
276 end
277
278 1/1 assign tx_data_get_o = tx_data_get_q;
Tests: T1 T2 T3
279
280 // calculate crc16
281 1/1 assign crc16_invert = serial_tx_data ^ crc16_q[15];
Tests: T1 T2 T3
282
283 always_comb begin : proc_crc16
284 1/1 crc16_d = crc16_q; // default assignment
Tests: T1 T2 T3
285
286 1/1 if (pkt_start_i) begin
Tests: T1 T2 T3
287 1/1 crc16_d = 16'b1111111111111111;
Tests: T1 T2 T18
288 end
MISSING_ELSE
289
290 1/1 if (bit_strobe_i && data_payload_q && !bitstuff_q4 && !pkt_start_i) begin
Tests: T1 T2 T3
291 1/1 crc16_d = {crc16_q[14:0], 1'b0} ^ ({16{crc16_invert}} & 16'b1000000000000101);
Tests: T21 T28 T7
292 end
MISSING_ELSE
293 end
294
295 ///////////////////////
296 // Regular Registers //
297 ///////////////////////
298
299 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_reg
300 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
301 1/1 state_q <= Idle;
Tests: T1 T2 T3
302 1/1 data_payload_q <= 0;
Tests: T1 T2 T3
303 1/1 data_shift_reg_q <= 0;
Tests: T1 T2 T3
304 1/1 oe_shift_reg_q <= 0;
Tests: T1 T2 T3
305 1/1 se0_shift_reg_q <= 0;
Tests: T1 T2 T3
306 1/1 tx_data_get_q <= 0;
Tests: T1 T2 T3
307 1/1 byte_strobe_q <= 0;
Tests: T1 T2 T3
308 1/1 bit_history_q <= 0;
Tests: T1 T2 T3
309 1/1 bit_count_q <= 0;
Tests: T1 T2 T3
310 1/1 crc16_q <= 0;
Tests: T1 T2 T3
311 end else begin
312 1/1 if (link_reset_i) begin
Tests: T1 T2 T3
313 1/1 state_q <= Idle;
Tests: T1 T2 T3
314 1/1 data_payload_q <= 0;
Tests: T1 T2 T3
315 1/1 data_shift_reg_q <= 0;
Tests: T1 T2 T3
316 1/1 oe_shift_reg_q <= 0;
Tests: T1 T2 T3
317 1/1 se0_shift_reg_q <= 0;
Tests: T1 T2 T3
318 1/1 tx_data_get_q <= 0;
Tests: T1 T2 T3
319 1/1 byte_strobe_q <= 0;
Tests: T1 T2 T3
320 1/1 bit_history_q <= 0;
Tests: T1 T2 T3
321 1/1 bit_count_q <= 0;
Tests: T1 T2 T3
322 1/1 crc16_q <= 0;
Tests: T1 T2 T3
323 end else begin
324 1/1 state_q <= state_d;
Tests: T1 T2 T3
325 1/1 data_payload_q <= data_payload_d;
Tests: T1 T2 T3
326 1/1 data_shift_reg_q <= data_shift_reg_d;
Tests: T1 T2 T3
327 1/1 oe_shift_reg_q <= oe_shift_reg_d;
Tests: T1 T2 T3
328 1/1 se0_shift_reg_q <= se0_shift_reg_d;
Tests: T1 T2 T3
329 1/1 tx_data_get_q <= tx_data_get_d;
Tests: T1 T2 T3
330 1/1 byte_strobe_q <= byte_strobe_d;
Tests: T1 T2 T3
331 1/1 bit_history_q <= bit_history_d;
Tests: T1 T2 T3
332 1/1 bit_count_q <= bit_count_d;
Tests: T1 T2 T3
333 1/1 crc16_q <= crc16_d;
Tests: T1 T2 T3
334 end
335 end
336 end
337
338 ///////////////////////////////////
339 // nrzi and differential driving //
340 ///////////////////////////////////
341
342 // Output FSM
343 always_comb begin : proc_out_fsm
344 1/1 out_state_d = out_state_q;
Tests: T1 T2 T3
345 1/1 out_nrzi_en = 1'b0;
Tests: T1 T2 T3
346
347 1/1 unique case (out_state_q)
Tests: T1 T2 T3
348 OsIdle: begin
349 1/1 if (pkt_start_i || test_mode_start) begin
Tests: T1 T2 T3
350 1/1 out_state_d = OsWaitByte;
Tests: T1 T2 T18
351 end
MISSING_ELSE
352 end
353
354 OsWaitByte: begin
355 1/1 if (byte_strobe_q) begin
Tests: T1 T2 T18
356 1/1 out_state_d = OsTransmit;
Tests: T1 T2 T18
357 end
MISSING_ELSE
358 end
359
360 OsTransmit: begin
361 1/1 out_nrzi_en = 1'b1;
Tests: T1 T2 T18
362 1/1 if ((bit_strobe_i && !serial_tx_oe)) begin
Tests: T1 T2 T18
363 1/1 out_state_d = OsIdle;
Tests: T1 T2 T18
364 end
MISSING_ELSE
365 end
366
367 default : out_state_d = OsIdle;
Exclude Annotation: VC_COV_UNR
368 endcase
369 end
370
371 `ASSERT(OutStateValid_A, out_state_q inside {OsIdle, OsWaitByte, OsTransmit})
372
373 always_comb begin : proc_diff
374 1/1 usb_d_d = usb_d_q;
Tests: T1 T2 T3
375 1/1 usb_se0_d = usb_se0_q;
Tests: T1 T2 T3
376 1/1 oe_d = oe_q;
Tests: T1 T2 T3
377 1/1 dp_eop_d = dp_eop_q;
Tests: T1 T2 T3
378
379 1/1 if (pkt_start_i) begin
Tests: T1 T2 T3
380 1/1 usb_d_d = 1; // J -> first bit will be K (start of sync)
Tests: T1 T2 T18
381 1/1 dp_eop_d = 3'b100; // Eop: {SE0, SE0, J}
Tests: T1 T2 T18
382
383 1/1 end else if (bit_strobe_i && out_nrzi_en) begin
Tests: T1 T2 T3
384 1/1 oe_d = serial_tx_oe;
Tests: T1 T2 T18
385
386 1/1 if (serial_tx_se0) begin
Tests: T1 T2 T18
387 // Eop
388 1/1 dp_eop_d = dp_eop_q >> 1;
Tests: T1 T2 T18
389
390 1/1 if (dp_eop_q[0]) begin
Tests: T1 T2 T18
391 // last bit of Eop: J
392 1/1 usb_d_d = 1;
Tests: T1 T2 T18
393 1/1 usb_se0_d = 0;
Tests: T1 T2 T18
394 end else begin
395 // first two bits of Eop: SE0
396 1/1 usb_se0_d = 1;
Tests: T1 T2 T18
397 end
398
399 1/1 end else if (serial_tx_data) begin
Tests: T1 T2 T18
400 // value should stay the same, do nothing
401
402 end else begin
403 1/1 usb_d_d = !usb_d_q;
Tests: T1 T2 T18
404 end
405 end
MISSING_ELSE
406
407 // Set to J state when OE=0 to avoid
408 // glitches
409 1/1 if (!oe_d) begin
Tests: T1 T2 T3
410 1/1 usb_d_d = 1;
Tests: T1 T2 T3
411 end
MISSING_ELSE
412 end
413
414 always_ff @(posedge clk_i or negedge rst_ni) begin : proc_diff_reg
415 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
416 1/1 dp_eop_q <= 0;
Tests: T1 T2 T3
417 1/1 out_state_q <= OsIdle;
Tests: T1 T2 T3
418 end else begin
419 1/1 if (link_reset_i) begin
Tests: T1 T2 T3
420 1/1 dp_eop_q <= 0;
Tests: T1 T2 T3
421 1/1 out_state_q <= OsIdle;
Tests: T1 T2 T3
422 end else begin
423 1/1 dp_eop_q <= dp_eop_d;
Tests: T1 T2 T3
424 1/1 out_state_q <= out_state_d;
Tests: T1 T2 T3
425 end
426 end
427 end
428
429
430 prim_flop u_oe_flop (
431 .clk_i,
432 .rst_ni,
433 .d_i(link_reset_i ? 1'b0 : oe_d),
434 .q_o(oe_q)
435 );
436
437 prim_flop #(
438 .ResetValue(1) // J state = idle state
439 ) u_usb_d_flop (
440 .clk_i,
441 .rst_ni,
442 .d_i(link_reset_i ? 1'b1 : usb_d_d),
443 .q_o(usb_d_q)
444 );
445
446 prim_flop u_usb_se0_flop (
447 .clk_i,
448 .rst_ni,
449 .d_i(link_reset_i ? 1'b0 : usb_se0_d),
450 .q_o(usb_se0_q)
451 );
452
453 // Handle the D+ / D- pin flip on the USB side, and provide both the
454 // dp/dn and d/se0 interfaces, for compatibility with multiple driver types.
455 logic usb_se0_flipped, usb_dp_flipped, usb_dn_flipped;
456
457 always_comb begin
458 1/1 if (link_reset_i) begin
Tests: T1 T2 T3
459 1/1 usb_se0_flipped = 1'b0;
Tests: T1 T2 T3
460 1/1 usb_dp_flipped = !cfg_pinflip_i;
Tests: T1 T2 T3
461 1/1 usb_dn_flipped = cfg_pinflip_i;
Tests: T1 T2 T3
462 end else begin
463 1/1 usb_se0_flipped = usb_se0_d;
Tests: T1 T2 T3
464 1/1 usb_dp_flipped = (cfg_pinflip_i ? ~usb_d_d : usb_d_d) & ~usb_se0_d;
Tests: T1 T2 T3
465 1/1 usb_dn_flipped = (cfg_pinflip_i ? usb_d_d : ~usb_d_d) & ~usb_se0_d;
Tests: T1 T2 T3
466 end
467 end
468
469 // Use registered outputs for the I/Os
470 prim_flop #(
471 .ResetValue(1) // J state = idle state
472 ) u_usb_d_o_flop (
473 .clk_i,
474 .rst_ni,
475 .d_i(usb_dp_flipped), // Note: single-ended 'D' output mirrors D+
476 .q_o(usb_d_o)
477 );
478
479 prim_flop #(
480 .ResetValue(0) // J state = idle state
481 ) u_usb_se0_o_flop (
482 .clk_i,
483 .rst_ni,
484 .d_i(usb_se0_flipped),
485 .q_o(usb_se0_o)
486 );
487
488 prim_flop #(
489 .ResetValue(1) // J state = idle state
490 ) u_usb_dp_o_flop (
491 .clk_i,
492 .rst_ni,
493 .d_i(usb_dp_flipped),
494 .q_o(usb_dp_o)
495 );
496
497 prim_flop #(
498 .ResetValue(0) // J state = idle state
499 ) u_usb_dn_o_flop (
500 .clk_i,
501 .rst_ni,
502 .d_i(usb_dn_flipped),
503 .q_o(usb_dn_o)
504 );
505
506 1/1 assign usb_oe_o = oe_q;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx
| Total | Covered | Percent |
|---|
| Conditions | 54 | 53 | 98.15 |
| Logical | 54 | 53 | 98.15 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 98
EXPRESSION (pkt_start_i ? pid_i : pid_q)
-----1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T18 |
LINE 108
EXPRESSION (bit_history == 6'b111111)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T21,T28,T7 |
LINE 131
EXPRESSION (bit_strobe_i && (se0_shift_reg_q[1:0] == 2'b1))
------1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T18 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T18 |
LINE 131
SUB-EXPRESSION (se0_shift_reg_q[1:0] == 2'b1)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T18 |
LINE 171
EXPRESSION (pid_q[1:0] == 2'b11)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T18 |
| 1 | Covered | T18,T21,T28 |
LINE 226
EXPRESSION (((!tx_osc_test_mode_i)) && byte_strobe_q)
-----------1----------- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T201 |
| 1 | 0 | Covered | T201 |
| 1 | 1 | Covered | T201 |
LINE 270
EXPRESSION (bit_strobe_i && ((!bitstuff)) && ((!pkt_start_i)))
------1----- ------2------ --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T21,T28,T7 |
| 1 | 1 | 0 | Covered | T1,T2,T18 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 271
EXPRESSION (bit_count_q == 3'b0)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 281
EXPRESSION (serial_tx_data ^ crc16_q[15])
-------1------ -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T18 |
| 1 | 0 | Covered | T21,T28,T7 |
| 1 | 1 | Covered | T1,T2,T18 |
LINE 290
EXPRESSION (bit_strobe_i && data_payload_q && ((!bitstuff_q4)) && ((!pkt_start_i)))
------1----- -------2------ --------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T21,T28,T7 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T21,T28,T7 |
| 1 | 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | 1 | Covered | T21,T28,T7 |
LINE 349
EXPRESSION (pkt_start_i || test_mode_start)
-----1----- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T201 |
| 1 | 0 | Covered | T1,T2,T18 |
LINE 362
EXPRESSION (bit_strobe_i && ((!serial_tx_oe)))
------1----- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T18 |
| 1 | 0 | Covered | T1,T2,T18 |
| 1 | 1 | Covered | T1,T2,T18 |
LINE 383
EXPRESSION (bit_strobe_i && out_nrzi_en)
------1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T18 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T18 |
LINE 430
EXPRESSION (link_reset_i ? 1'b0 : oe_d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 439
EXPRESSION (link_reset_i ? 1'b1 : usb_d_d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 446
EXPRESSION (link_reset_i ? 1'b0 : usb_se0_d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 464
EXPRESSION ((cfg_pinflip_i ? ((~usb_d_d)) : usb_d_d) & ((~usb_se0_d)))
--------------------1------------------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T18 |
| 1 | 0 | Covered | T21,T28,T7 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 464
SUB-EXPRESSION (cfg_pinflip_i ? ((~usb_d_d)) : usb_d_d)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T44,T45,T202 |
LINE 465
EXPRESSION ((cfg_pinflip_i ? usb_d_d : ((~usb_d_d))) & ((~usb_se0_d)))
--------------------1------------------- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T18 |
| 1 | 1 | Covered | T1,T2,T18 |
LINE 465
SUB-EXPRESSION (cfg_pinflip_i ? usb_d_d : ((~usb_d_d)))
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T44,T45,T202 |
FSM Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
7 |
7 |
100.00 |
(Not included in score) |
| Transitions |
12 |
11 |
91.67 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| Crc161 |
193 |
Covered |
T18,T21,T28 |
| DataOrCrc160 |
172 |
Covered |
T18,T21,T28 |
| Eop |
174 |
Covered |
T1,T2,T18 |
| Idle |
313 |
Covered |
T1,T2,T3 |
| OscTest |
153 |
Covered |
T201 |
| Pid |
162 |
Covered |
T1,T2,T18 |
| Sync |
156 |
Covered |
T1,T2,T18 |
| transitions | Line No. | Covered | Tests | Exclude Annotation |
| Crc161->Eop |
208 |
Covered |
T18,T21,T28 |
|
| Crc161->Idle |
313 |
Not Covered |
|
|
| DataOrCrc160->Crc161 |
193 |
Covered |
T18,T21,T28 |
|
| DataOrCrc160->Idle |
313 |
Covered |
T203,T204,T205 |
|
| Eop->Idle |
313 |
Covered |
T1,T2,T18 |
|
| Idle->OscTest |
153 |
Covered |
T201 |
|
| Idle->Sync |
156 |
Covered |
T1,T2,T18 |
|
| OscTest->Idle |
313 |
Covered |
T201 |
|
| Pid->DataOrCrc160 |
172 |
Covered |
T18,T21,T28 |
|
| Pid->Eop |
174 |
Covered |
T1,T2,T18 |
|
| Pid->Idle |
313 |
Covered |
T206,T207,T208 |
|
| Sync->Idle |
313 |
Excluded |
|
Link reset will not be detected whilst the DUT is transmitting. |
| Sync->Pid |
162 |
Covered |
T1,T2,T18 |
|
Summary for FSM :: out_state_q
| Total | Covered | Percent | |
| States |
3 |
3 |
100.00 |
(Not included in score) |
| Transitions |
3 |
3 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: out_state_q
| states | Line No. | Covered | Tests |
| OsIdle |
421 |
Covered |
T1,T2,T3 |
| OsTransmit |
356 |
Covered |
T1,T2,T18 |
| OsWaitByte |
350 |
Covered |
T1,T2,T18 |
| transitions | Line No. | Covered | Tests | Exclude Annotation |
| OsIdle->OsWaitByte |
350 |
Covered |
T1,T2,T18 |
|
| OsTransmit->OsIdle |
421 |
Covered |
T1,T2,T18 |
|
| OsWaitByte->OsIdle |
421 |
Excluded |
|
Link reset will not be detected whilst the DUT is transmitting. |
| OsWaitByte->OsTransmit |
356 |
Covered |
T1,T2,T18 |
|
Branch Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx
| Line No. | Total | Covered | Percent |
| Branches |
|
64 |
64 |
100.00 |
| TERNARY |
98 |
2 |
2 |
100.00 |
| TERNARY |
430 |
2 |
2 |
100.00 |
| TERNARY |
439 |
2 |
2 |
100.00 |
| TERNARY |
446 |
2 |
2 |
100.00 |
| IF |
87 |
3 |
3 |
100.00 |
| IF |
111 |
3 |
3 |
100.00 |
| CASE |
150 |
18 |
18 |
100.00 |
| IF |
240 |
4 |
4 |
100.00 |
| IF |
270 |
2 |
2 |
100.00 |
| IF |
286 |
2 |
2 |
100.00 |
| IF |
290 |
2 |
2 |
100.00 |
| IF |
300 |
3 |
3 |
100.00 |
| CASE |
347 |
6 |
6 |
100.00 |
| IF |
379 |
6 |
6 |
100.00 |
| IF |
409 |
2 |
2 |
100.00 |
| IF |
415 |
3 |
3 |
100.00 |
| IF |
458 |
2 |
2 |
100.00 |
98 assign pid_d = pkt_start_i ? pid_i : pid_q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T18 |
| 0 |
Covered |
T1,T2,T3 |
430 prim_flop u_oe_flop (
431 .clk_i,
432 .rst_ni,
433 .d_i(link_reset_i ? 1'b0 : oe_d),
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
439 ) u_usb_d_flop (
440 .clk_i,
441 .rst_ni,
442 .d_i(link_reset_i ? 1'b1 : usb_d_d),
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
446 prim_flop u_usb_se0_flop (
447 .clk_i,
448 .rst_ni,
449 .d_i(link_reset_i ? 1'b0 : usb_se0_d),
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
87 if (!rst_ni) begin
-1-
88 pid_q <= 0;
==>
89 end else begin
90 if (link_reset_i) begin
-2-
91 pid_q <= 0;
==>
92 end else begin
93 pid_q <= pid_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
111 if (!rst_ni) begin
-1-
112 bitstuff_q <= 0;
==>
113 bitstuff_q2 <= 0;
114 bitstuff_q3 <= 0;
115 bitstuff_q4 <= 0;
116 end else begin
117 if (link_reset_i) begin
-2-
118 bitstuff_q <= 0;
==>
119 bitstuff_q2 <= 0;
120 bitstuff_q3 <= 0;
121 bitstuff_q4 <= 0;
122 end else begin
123 bitstuff_q <= bitstuff;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
150 unique case (state_q)
-1-
151 Idle : begin
152 if (tx_osc_test_mode_i) begin
-2-
153 state_d = OscTest;
==>
154 test_mode_start = 1;
155 end else if (pkt_start_i) begin
-3-
156 state_d = Sync;
==>
157 end
MISSING_ELSE
==>
158 end
159
160 Sync : begin
161 if (byte_strobe_q) begin
-4-
162 state_d = Pid;
==>
163 data_shift_reg_d = 8'b10000000;
164 oe_shift_reg_d = 8'b11111111;
165 se0_shift_reg_d = 8'b00000000;
166 end
MISSING_ELSE
==>
167 end
168
169 Pid : begin
170 if (byte_strobe_q) begin
-5-
171 if (pid_q[1:0] == 2'b11) begin
-6-
172 state_d = DataOrCrc160;
==>
173 end else begin
174 state_d = Eop;
==>
175 end
176
177 data_shift_reg_d = {~pid_q, pid_q};
178 oe_shift_reg_d = 8'b11111111;
179 se0_shift_reg_d = 8'b00000000;
180 end
MISSING_ELSE
==>
181 end
182
183 DataOrCrc160 : begin
184 if (byte_strobe_q) begin
-7-
185 if (tx_data_avail_i) begin
-8-
186 state_d = DataOrCrc160;
==>
187 data_payload_d = 1;
188 tx_data_get_d = 1;
189 data_shift_reg_d = tx_data_i;
190 oe_shift_reg_d = 8'b11111111;
191 se0_shift_reg_d = 8'b00000000;
192 end else begin
193 state_d = Crc161;
==>
194 data_payload_d = 0;
195 tx_data_get_d = 0;
196 data_shift_reg_d = ~{crc16_q[8], crc16_q[9], crc16_q[10], crc16_q[11],
197 crc16_q[12], crc16_q[13], crc16_q[14], crc16_q[15]};
198 oe_shift_reg_d = 8'b11111111;
199 se0_shift_reg_d = 8'b00000000;
200 end
201 end else begin
202 tx_data_get_d = 0;
==>
203 end
204 end
205
206 Crc161 : begin
207 if (byte_strobe_q) begin
-9-
208 state_d = Eop;
==>
209 data_shift_reg_d = ~{crc16_q[0], crc16_q[1], crc16_q[2], crc16_q[3],
210 crc16_q[4], crc16_q[5], crc16_q[6], crc16_q[7]};
211 oe_shift_reg_d = 8'b11111111;
212 se0_shift_reg_d = 8'b00000000;
213 end
MISSING_ELSE
==>
214 end
215
216 Eop : begin
217 if (byte_strobe_q) begin
-10-
218 state_d = Idle;
==>
219 oe_shift_reg_d = 8'b00000111;
220 se0_shift_reg_d = 8'b00000111;
221 end
MISSING_ELSE
==>
222 end
223
224 OscTest: begin
225 // Oscillator test mode: toggle constantly
226 if (!tx_osc_test_mode_i && byte_strobe_q) begin
-11-
227 oe_shift_reg_d = 8'b00000000;
==>
228 state_d = Idle;
229 end else if (byte_strobe_q) begin
-12-
230 data_shift_reg_d = 8'b00000000;
==>
231 oe_shift_reg_d = 8'b11111111;
232 se0_shift_reg_d = 8'b00000000;
233 end
MISSING_ELSE
==>
234 end
235
236 default: state_d = Idle;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | Status | Tests | Exclude Annotation |
| Idle |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T201 |
|
| Idle |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T18 |
|
| Idle |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| Sync |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T18 |
|
| Sync |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T18 |
|
| Pid |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T18,T21,T28 |
|
| Pid |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T18 |
|
| Pid |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T18 |
|
| DataOrCrc160 |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
Covered |
T21,T28,T7 |
|
| DataOrCrc160 |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
Covered |
T18,T21,T28 |
|
| DataOrCrc160 |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T18,T21,T28 |
|
| Crc161 |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T18,T21,T28 |
|
| Crc161 |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T18,T21,T28 |
|
| Eop |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T1,T2,T18 |
|
| Eop |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
Covered |
T1,T2,T18 |
|
| OscTest |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T201 |
|
| OscTest |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
Covered |
T201 |
|
| OscTest |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
Covered |
T201 |
|
| default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
240 if (pkt_start_i) begin
-1-
241 // We need to have an inter-packet delay between
242 // 2 and 6.5 bit times (see USB 2.0 spec / 7.1.18.1)
243 // The latency in the rest of the system is approximately (measured)
244 // 3.68 bit-times, so we only introduce 1 bit-time here
245 bit_count_d = 7; // 8-7 = 1
==>
246 bit_history_d = 0;
247
248 end else if (bit_strobe_i) begin
-2-
249 // bitstuff
250 if (bitstuff /* && !serial_tx_se0*/) begin
-3-
251 bit_history_d = bit_history[5:1];
==>
252 data_shift_reg_d[0] = 0;
253
254 // normal deserialize
255 end else begin
256 bit_count_d = bit_count_q + 1;
==>
257
258 data_shift_reg_d = (data_shift_reg_q >> 1);
259 oe_shift_reg_d = (oe_shift_reg_q >> 1);
260 se0_shift_reg_d = (se0_shift_reg_q >> 1);
261
262 bit_history_d = bit_history[5:1];
263 end
264 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T18 |
| 0 |
1 |
1 |
Covered |
T21,T28,T7 |
| 0 |
1 |
0 |
Covered |
T1,T2,T3 |
| 0 |
0 |
- |
Covered |
T1,T2,T3 |
270 if (bit_strobe_i && !bitstuff && !pkt_start_i) begin
-1-
271 byte_strobe_d = (bit_count_q == 3'b000);
==>
272 end else begin
273 byte_strobe_d = 0;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
286 if (pkt_start_i) begin
-1-
287 crc16_d = 16'b1111111111111111;
==>
288 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T18 |
| 0 |
Covered |
T1,T2,T3 |
290 if (bit_strobe_i && data_payload_q && !bitstuff_q4 && !pkt_start_i) begin
-1-
291 crc16_d = {crc16_q[14:0], 1'b0} ^ ({16{crc16_invert}} & 16'b1000000000000101);
==>
292 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T21,T28,T7 |
| 0 |
Covered |
T1,T2,T3 |
300 if (!rst_ni) begin
-1-
301 state_q <= Idle;
==>
302 data_payload_q <= 0;
303 data_shift_reg_q <= 0;
304 oe_shift_reg_q <= 0;
305 se0_shift_reg_q <= 0;
306 tx_data_get_q <= 0;
307 byte_strobe_q <= 0;
308 bit_history_q <= 0;
309 bit_count_q <= 0;
310 crc16_q <= 0;
311 end else begin
312 if (link_reset_i) begin
-2-
313 state_q <= Idle;
==>
314 data_payload_q <= 0;
315 data_shift_reg_q <= 0;
316 oe_shift_reg_q <= 0;
317 se0_shift_reg_q <= 0;
318 tx_data_get_q <= 0;
319 byte_strobe_q <= 0;
320 bit_history_q <= 0;
321 bit_count_q <= 0;
322 crc16_q <= 0;
323 end else begin
324 state_q <= state_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
347 unique case (out_state_q)
-1-
348 OsIdle: begin
349 if (pkt_start_i || test_mode_start) begin
-2-
350 out_state_d = OsWaitByte;
==>
351 end
MISSING_ELSE
==>
352 end
353
354 OsWaitByte: begin
355 if (byte_strobe_q) begin
-3-
356 out_state_d = OsTransmit;
==>
357 end
MISSING_ELSE
==>
358 end
359
360 OsTransmit: begin
361 out_nrzi_en = 1'b1;
362 if ((bit_strobe_i && !serial_tx_oe)) begin
-4-
363 out_state_d = OsIdle;
==>
364 end
MISSING_ELSE
==>
365 end
366
367 default : out_state_d = OsIdle;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
Branches:
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
| OsIdle |
1 |
- |
- |
Covered |
T1,T2,T18 |
|
| OsIdle |
0 |
- |
- |
Covered |
T1,T2,T3 |
|
| OsWaitByte |
- |
1 |
- |
Covered |
T1,T2,T18 |
|
| OsWaitByte |
- |
0 |
- |
Covered |
T1,T2,T18 |
|
| OsTransmit |
- |
- |
1 |
Covered |
T1,T2,T18 |
|
| OsTransmit |
- |
- |
0 |
Covered |
T1,T2,T18 |
|
| default |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
379 if (pkt_start_i) begin
-1-
380 usb_d_d = 1; // J -> first bit will be K (start of sync)
==>
381 dp_eop_d = 3'b100; // Eop: {SE0, SE0, J}
382
383 end else if (bit_strobe_i && out_nrzi_en) begin
-2-
384 oe_d = serial_tx_oe;
385
386 if (serial_tx_se0) begin
-3-
387 // Eop
388 dp_eop_d = dp_eop_q >> 1;
389
390 if (dp_eop_q[0]) begin
-4-
391 // last bit of Eop: J
392 usb_d_d = 1;
==>
393 usb_se0_d = 0;
394 end else begin
395 // first two bits of Eop: SE0
396 usb_se0_d = 1;
==>
397 end
398
399 end else if (serial_tx_data) begin
-5-
==>
400 // value should stay the same, do nothing
401
402 end else begin
403 usb_d_d = !usb_d_q;
==>
404 end
405 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | Status | Tests |
| 1 |
- |
- |
- |
- |
Covered |
T1,T2,T18 |
| 0 |
1 |
1 |
1 |
- |
Covered |
T1,T2,T18 |
| 0 |
1 |
1 |
0 |
- |
Covered |
T1,T2,T18 |
| 0 |
1 |
0 |
- |
1 |
Covered |
T1,T2,T18 |
| 0 |
1 |
0 |
- |
0 |
Covered |
T1,T2,T18 |
| 0 |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
409 if (!oe_d) begin
-1-
410 usb_d_d = 1;
==>
411 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T18 |
415 if (!rst_ni) begin
-1-
416 dp_eop_q <= 0;
==>
417 out_state_q <= OsIdle;
418 end else begin
419 if (link_reset_i) begin
-2-
420 dp_eop_q <= 0;
==>
421 out_state_q <= OsIdle;
422 end else begin
423 dp_eop_q <= dp_eop_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
458 if (link_reset_i) begin
-1-
459 usb_se0_flipped = 1'b0;
==>
460 usb_dp_flipped = !cfg_pinflip_i;
461 usb_dn_flipped = cfg_pinflip_i;
462 end else begin
463 usb_se0_flipped = usb_se0_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx
Assertion Details
OutStateValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
582830002 |
582531406 |
0 |
0 |
| T1 |
7336 |
7239 |
0 |
0 |
| T2 |
8639 |
8540 |
0 |
0 |
| T3 |
192249 |
192153 |
0 |
0 |
| T16 |
7026 |
6947 |
0 |
0 |
| T17 |
7470 |
7397 |
0 |
0 |
| T18 |
18808 |
18754 |
0 |
0 |
| T19 |
7109 |
7043 |
0 |
0 |
| T20 |
23009 |
22951 |
0 |
0 |
| T21 |
51767 |
51684 |
0 |
0 |
| T22 |
2047 |
1954 |
0 |
0 |
StateValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
582830002 |
582531406 |
0 |
0 |
| T1 |
7336 |
7239 |
0 |
0 |
| T2 |
8639 |
8540 |
0 |
0 |
| T3 |
192249 |
192153 |
0 |
0 |
| T16 |
7026 |
6947 |
0 |
0 |
| T17 |
7470 |
7397 |
0 |
0 |
| T18 |
18808 |
18754 |
0 |
0 |
| T19 |
7109 |
7043 |
0 |
0 |
| T20 |
23009 |
22951 |
0 |
0 |
| T21 |
51767 |
51684 |
0 |
0 |
| T22 |
2047 |
1954 |
0 |
0 |