Unified Coverage Report :: Module Instance :: tb.dut.usbdev_avsetupfifo

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	98.59	88.57			96.00	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	98.59	88.57			96.00	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	98.59	88.57			96.00	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T1 T16 T20 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T1 T16 T20 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T1 T16 T20 

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T23,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T16,T20

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T16,T60
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T16,T20

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		DUT shall not read from empty FIFO
1	0	1	Covered	T1,T16,T20
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T23,T29

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T20
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	582830002	140534089	0	0
DepthKnown_A	582830002	582531406	0	0
RvalidKnown_A	582830002	582531406	0	0
WreadyKnown_A	582830002	582531406	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	582830002	140534089	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	140534089	0	0
T1	7336	568	0	0
T2	8639	0	0	0
T3	192249	0	0	0
T4	0	136938	0	0
T16	7026	762	0	0
T17	7470	0	0	0
T18	18808	0	0	0
T19	7109	0	0	0
T20	23009	16896	0	0
T21	51767	0	0	0
T22	2047	0	0	0
T23	0	5416	0	0
T24	0	13062	0	0
T29	0	17461	0	0
T44	0	568	0	0
T45	0	582	0	0
T88	0	596	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	582531406	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	582531406	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	582531406	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	140534089	0	0
T1	7336	568	0	0
T2	8639	0	0	0
T3	192249	0	0	0
T4	0	136938	0	0
T16	7026	762	0	0
T17	7470	0	0	0
T18	18808	0	0	0
T19	7109	0	0	0
T20	23009	16896	0	0
T21	51767	0	0	0
T22	2047	0	0	0
T23	0	5416	0	0
T24	0	13062	0	0
T29	0	17461	0	0
T44	0	568	0	0
T45	0	582	0	0
T88	0	596	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T2 T17 T18 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T2 T17 T18 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T2 T17 T18 

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T29,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T17,T18

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T61,T89,T90
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T17,T18

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		DUT shall not read from empty FIFO
1	0	1	Covered	T2,T17,T18
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T18,T21

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T17,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	582830002	285550601	0	0
DepthKnown_A	582830002	582531406	0	0
RvalidKnown_A	582830002	582531406	0	0
WreadyKnown_A	582830002	582531406	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	582830002	285550601	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	285550601	0	0
T2	8639	2041	0	0
T3	192249	0	0	0
T7	0	485	0	0
T16	7026	0	0	0
T17	7470	1149	0	0
T18	18808	7924	0	0
T19	7109	1180	0	0
T20	23009	16282	0	0
T21	51767	23115	0	0
T22	2047	0	0	0
T23	14978	0	0	0
T24	0	13688	0	0
T28	0	16468	0	0
T29	0	11414	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	582531406	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	582531406	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	582531406	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	285550601	0	0
T2	8639	2041	0	0
T3	192249	0	0	0
T7	0	485	0	0
T16	7026	0	0	0
T17	7470	1149	0	0
T18	18808	7924	0	0
T19	7109	1180	0	0
T20	23009	16282	0	0
T21	51767	23115	0	0
T22	2047	0	0	0
T23	14978	0	0	0
T24	0	13688	0	0
T28	0	16468	0	0
T29	0	11414	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T1 T2 T18 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T1 T2 T18 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T23,T49,T50
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T18

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T18

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T18
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T18,T21

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T18

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	582830002	48681712	0	0
DepthKnown_A	582830002	582531406	0	0
RvalidKnown_A	582830002	582531406	0	0
WreadyKnown_A	582830002	582531406	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	582830002	48681712	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	48681712	0	0
T1	7336	98	0	0
T2	8639	922	0	0
T3	192249	0	0	0
T7	0	111	0	0
T16	7026	0	0	0
T17	7470	0	0	0
T18	18808	567	0	0
T19	7109	0	0	0
T20	23009	0	0	0
T21	51767	728	0	0
T22	2047	0	0	0
T23	0	5549	0	0
T28	0	1142	0	0
T29	0	17682	0	0
T30	0	10902	0	0
T32	0	2668	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	582531406	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	582531406	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	582531406	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	48681712	0	0
T1	7336	98	0	0
T2	8639	922	0	0
T3	192249	0	0	0
T7	0	111	0	0
T16	7026	0	0	0
T17	7470	0	0	0
T18	18808	567	0	0
T19	7109	0	0	0
T20	23009	0	0	0
T21	51767	728	0	0
T22	2047	0	0	0
T23	0	5549	0	0
T28	0	1142	0	0
T29	0	17682	0	0
T30	0	10902	0	0
T32	0	2668	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584828014	19334642	0	0
DepthKnown_A	584828014	584489739	0	0
RvalidKnown_A	584828014	584489739	0	0
WreadyKnown_A	584828014	584489739	0	0
gen_passthru_fifo.paramCheckPass	3905	3905	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	19334642	0	0
T1	7336	14	0	0
T2	8639	20	0	0
T3	192249	427	0	0
T16	7026	18	0	0
T17	7470	12	0	0
T18	18808	120	0	0
T19	7109	11	0	0
T20	23009	83	0	0
T21	51767	337	0	0
T22	2047	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	584489739	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	584489739	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	584489739	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3905	3905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584828014	28251127	0	0
DepthKnown_A	584828014	584489739	0	0
RvalidKnown_A	584828014	584489739	0	0
WreadyKnown_A	584828014	584489739	0	0
gen_passthru_fifo.paramCheckPass	3905	3905	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	28251127	0	0
T1	7336	14	0	0
T2	8639	76	0	0
T3	192249	427	0	0
T16	7026	18	0	0
T17	7470	28	0	0
T18	18808	120	0	0
T19	7109	11	0	0
T20	23009	83	0	0
T21	51767	337	0	0
T22	2047	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	584489739	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	584489739	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	584489739	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3905	3905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584828014	942048	0	0
DepthKnown_A	584828014	584489739	0	0
RvalidKnown_A	584828014	584489739	0	0
WreadyKnown_A	584828014	584489739	0	0
gen_passthru_fifo.paramCheckPass	3905	3905	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	942048	0	0
T1	7336	2	0	0
T2	8639	0	0	0
T3	192249	0	0	0
T16	7026	0	0	0
T17	7470	0	0	0
T18	18808	48	0	0
T19	7109	0	0	0
T20	23009	14	0	0
T21	51767	77	0	0
T22	2047	0	0	0
T24	0	10	0	0
T28	0	102	0	0
T33	0	13	0	0
T85	0	16	0	0
T86	0	5	0	0
T87	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	584489739	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	584489739	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	584489739	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3905	3905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584828014	1802725	0	0
DepthKnown_A	584828014	584489739	0	0
RvalidKnown_A	584828014	584489739	0	0
WreadyKnown_A	584828014	584489739	0	0
gen_passthru_fifo.paramCheckPass	3905	3905	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	1802725	0	0
T1	7336	2	0	0
T2	8639	0	0	0
T3	192249	0	0	0
T16	7026	0	0	0
T17	7470	0	0	0
T18	18808	48	0	0
T19	7109	0	0	0
T20	23009	14	0	0
T21	51767	77	0	0
T22	2047	0	0	0
T24	0	45	0	0
T28	0	500	0	0
T33	0	53	0	0
T85	0	16	0	0
T86	0	5	0	0
T87	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	584489739	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	584489739	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	584489739	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3905	3905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584828014	18331787	0	0
DepthKnown_A	584828014	584489739	0	0
RvalidKnown_A	584828014	584489739	0	0
WreadyKnown_A	584828014	584489739	0	0
gen_passthru_fifo.paramCheckPass	3905	3905	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	18331787	0	0
T1	7336	12	0	0
T2	8639	20	0	0
T3	192249	427	0	0
T16	7026	18	0	0
T17	7470	12	0	0
T18	18808	72	0	0
T19	7109	11	0	0
T20	23009	69	0	0
T21	51767	260	0	0
T22	2047	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	584489739	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	584489739	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	584489739	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3905	3905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	584828014	26448402	0	0
DepthKnown_A	584828014	584489739	0	0
RvalidKnown_A	584828014	584489739	0	0
WreadyKnown_A	584828014	584489739	0	0
gen_passthru_fifo.paramCheckPass	3905	3905	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	26448402	0	0
T1	7336	12	0	0
T2	8639	76	0	0
T3	192249	427	0	0
T16	7026	18	0	0
T17	7470	28	0	0
T18	18808	72	0	0
T19	7109	11	0	0
T20	23009	69	0	0
T21	51767	260	0	0
T22	2047	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	584489739	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	584489739	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584828014	584489739	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3905	3905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T1 T18 T20 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T1 T18 T20 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T1 T18 T20 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T18,T20

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T18,T20

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T1,T18,T21
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T18,T20

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T18,T20
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T18,T20

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T20
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	582830002	1753063	0	0
DepthKnown_A	582830002	582531406	0	0
RvalidKnown_A	582830002	582531406	0	0
WreadyKnown_A	582830002	582531406	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	582830002	1753063	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	1753063	0	0
T1	7336	2	0	0
T2	8639	0	0	0
T3	192249	0	0	0
T16	7026	0	0	0
T17	7470	0	0	0
T18	18808	48	0	0
T19	7109	0	0	0
T20	23009	14	0	0
T21	51767	77	0	0
T22	2047	0	0	0
T24	0	45	0	0
T28	0	500	0	0
T33	0	53	0	0
T85	0	16	0	0
T86	0	5	0	0
T87	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	582531406	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	582531406	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	582531406	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	1753063	0	0
T1	7336	2	0	0
T2	8639	0	0	0
T3	192249	0	0	0
T16	7026	0	0	0
T17	7470	0	0	0
T18	18808	48	0	0
T19	7109	0	0	0
T20	23009	14	0	0
T21	51767	77	0	0
T22	2047	0	0	0
T24	0	45	0	0
T28	0	500	0	0
T33	0	53	0	0
T85	0	16	0	0
T86	0	5	0	0
T87	0	12	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T1 T18 T21 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T1 T18 T21 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T1 T18 T21 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T18,T21

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T18,T21

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T18,T21

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T18,T21
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T18,T21

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T21
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	582830002	599561	0	0
DepthKnown_A	582830002	582531406	0	0
RvalidKnown_A	582830002	582531406	0	0
WreadyKnown_A	582830002	582531406	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	582830002	599561	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	599561	0	0
T1	7336	2	0	0
T2	8639	0	0	0
T3	192249	0	0	0
T16	7026	0	0	0
T17	7470	0	0	0
T18	18808	48	0	0
T19	7109	0	0	0
T20	23009	0	0	0
T21	51767	77	0	0
T22	2047	0	0	0
T28	0	102	0	0
T33	0	13	0	0
T44	0	15	0	0
T45	0	15	0	0
T85	0	16	0	0
T86	0	5	0	0
T87	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	582531406	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	582531406	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	582531406	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	599561	0	0
T1	7336	2	0	0
T2	8639	0	0	0
T3	192249	0	0	0
T16	7026	0	0	0
T17	7470	0	0	0
T18	18808	48	0	0
T19	7109	0	0	0
T20	23009	0	0	0
T21	51767	77	0	0
T22	2047	0	0	0
T28	0	102	0	0
T33	0	13	0	0
T44	0	15	0	0
T45	0	15	0	0
T85	0	16	0	0
T86	0	5	0	0
T87	0	12	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T1 T18 T21 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T1 T18 T21 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130        1/1                assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
           Tests:       T1 T2 T3 
131        1/1                assign empty = fifo_empty & ~wvalid_i;
           Tests:       T1 T2 T3 
132                         end else begin : gen_nopass
133                           assign rdata_int = storage_rdata;
134                           assign empty = fifo_empty;
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	18	18	100.00
Logical	18	18	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T28,T33,T45
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T18,T21

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T18,T21

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T1,T18,T21
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T18,T21

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T21

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T18,T21

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T28,T33,T45
1	0	Covered	T1,T18,T21
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T18,T21
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

130              assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T21
0	Covered	T1,T2,T3

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T18,T21

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T21
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	582830002	1181781	0	0
DepthKnown_A	582830002	582531406	0	0
RvalidKnown_A	582830002	582531406	0	0
WreadyKnown_A	582830002	582531406	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	582830002	1181781	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	1181781	0	0
T1	7336	2	0	0
T2	8639	0	0	0
T3	192249	0	0	0
T16	7026	0	0	0
T17	7470	0	0	0
T18	18808	48	0	0
T19	7109	0	0	0
T20	23009	0	0	0
T21	51767	77	0	0
T22	2047	0	0	0
T28	0	500	0	0
T33	0	53	0	0
T44	0	15	0	0
T45	0	43	0	0
T85	0	16	0	0
T86	0	5	0	0
T87	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	582531406	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	582531406	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	582531406	0	0
T1	7336	7239	0	0
T2	8639	8540	0	0
T3	192249	192153	0	0
T16	7026	6947	0	0
T17	7470	7397	0	0
T18	18808	18754	0	0
T19	7109	7043	0	0
T20	23009	22951	0	0
T21	51767	51684	0	0
T22	2047	1954	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	582830002	1181781	0	0
T1	7336	2	0	0
T2	8639	0	0	0
T3	192249	0	0	0
T16	7026	0	0	0
T17	7470	0	0	0
T18	18808	48	0	0
T19	7109	0	0	0
T20	23009	0	0	0
T21	51767	77	0	0
T22	2047	0	0	0
T28	0	500	0	0
T33	0	53	0	0
T44	0	15	0	0
T45	0	43	0	0
T85	0	16	0	0
T86	0	5	0	0
T87	0	12	0	0