Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9860360	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10471114

1

T1

7

T2

6

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19661692	1			T1	7		T2	3		T3	7
values[0x0]	334180	1			T1	3		T2	5		T3	5
values[0x1]	335602	1			T1	8		T2	4		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7837217	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

12494257

1

T1

12

T2

6

T3

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	134274	1			T32	1		T38	8		T8	1
valid_sources[0x01]	60297	1			T32	1		T38	6		T8	1
valid_sources[0x02]	61170	1			T32	1		T37	1		T38	4
valid_sources[0x03]	103793	1			T41	2		T38	10		T8	2
valid_sources[0x04]	83996	1			T32	2		T37	1		T38	7
valid_sources[0x05]	119322	1			T32	1		T38	4		T8	1
valid_sources[0x06]	59855	1			T38	12		T8	1		T20	5
valid_sources[0x07]	76405	1			T38	8		T8	3		T20	2
valid_sources[0x08]	89217	1			T32	1		T38	7		T20	11
valid_sources[0x09]	339804	1			T32	2		T38	3		T8	2
valid_sources[0x0a]	59487	1			T37	1		T38	12		T161	1
valid_sources[0x0b]	61042	1			T37	1		T38	5		T39	2
valid_sources[0x0c]	77260	1			T32	1		T34	13		T38	10
valid_sources[0x0d]	60635	1			T38	4		T20	6		T60	102
valid_sources[0x0e]	121617	1			T38	3		T8	1		T20	4
valid_sources[0x0f]	60298	1			T32	1		T38	5		T20	3
valid_sources[0x10]	61098	1			T32	1		T38	5		T8	2
valid_sources[0x11]	61965	1			T43	5		T32	1		T38	2
valid_sources[0x12]	189470	1			T32	1		T38	5		T20	5
valid_sources[0x13]	124002	1			T38	12		T82	1		T91	1
valid_sources[0x14]	61559	1			T37	1		T38	10		T39	3
valid_sources[0x15]	60742	1			T38	7		T8	1		T20	2
valid_sources[0x16]	79272	1			T37	1		T38	3		T8	2
valid_sources[0x17]	77587	1			T38	7		T20	7		T60	127
valid_sources[0x18]	134314	1			T2	12		T38	10		T20	1
valid_sources[0x19]	90770	1			T37	1		T38	7		T39	4
valid_sources[0x1a]	60856	1			T32	2		T38	9		T8	1
valid_sources[0x1b]	61295	1			T37	1		T38	1		T8	1
valid_sources[0x1c]	61464	1			T32	1		T38	6		T52	47
valid_sources[0x1d]	128994	1			T38	2		T49	48		T162	6
valid_sources[0x1e]	63179	1			T32	1		T38	6		T20	3
valid_sources[0x1f]	112834	1			T38	3		T164	2		T82	1
valid_sources[0x20]	61921	1			T38	2		T20	6		T60	34
valid_sources[0x21]	61758	1			T32	2		T38	4		T8	1
valid_sources[0x22]	220614	1			T32	1		T33	1		T36	1
valid_sources[0x23]	61468	1			T32	1		T36	1		T38	7
valid_sources[0x24]	107559	1			T38	6		T20	3		T60	64
valid_sources[0x25]	61399	1			T41	1		T36	1		T38	9
valid_sources[0x26]	123173	1			T38	5		T566	1		T7	4
valid_sources[0x27]	58984	1			T38	9		T8	3		T20	2
valid_sources[0x28]	60377	1			T38	9		T162	1		T400	2
valid_sources[0x29]	61280	1			T32	2		T38	4		T8	1
valid_sources[0x2a]	146584	1			T36	1		T38	5		T162	2
valid_sources[0x2b]	60577	1			T38	5		T400	1		T163	1
valid_sources[0x2c]	61032	1			T32	1		T38	8		T566	1
valid_sources[0x2d]	62805	1			T3	2		T32	1		T38	2
valid_sources[0x2e]	149537	1			T37	1		T38	6		T82	1
valid_sources[0x2f]	102490	1			T32	1		T38	5		T400	4
valid_sources[0x30]	157744	1			T33	1		T37	1		T38	3
valid_sources[0x31]	60928	1			T38	4		T20	7		T60	94
valid_sources[0x32]	81988	1			T40	2		T32	2		T36	1
valid_sources[0x33]	60710	1			T43	2		T38	4		T163	1
valid_sources[0x34]	77626	1			T43	1		T32	1		T38	2
valid_sources[0x35]	111361	1			T1	18		T38	14		T20	4
valid_sources[0x36]	62641	1			T32	1		T38	4		T20	4
valid_sources[0x37]	73386	1			T32	1		T37	1		T38	10
valid_sources[0x38]	77111	1			T32	2		T38	2		T8	2
valid_sources[0x39]	111750	1			T33	1		T38	2		T39	2
valid_sources[0x3a]	60080	1			T32	1		T38	8		T83	28
valid_sources[0x3b]	60144	1			T32	1		T38	3		T39	1
valid_sources[0x3c]	62011	1			T41	1		T32	2		T36	1
valid_sources[0x3d]	73096	1			T38	10		T39	3		T8	3
valid_sources[0x3e]	61441	1			T32	1		T38	9		T82	1
valid_sources[0x3f]	173940	1			T33	2		T38	3		T72	1
valid_sources[0x40]	86946	1			T3	1		T32	2		T33	1
valid_sources[0x41]	85878	1			T32	1		T38	8		T72	1
valid_sources[0x42]	86787	1			T38	5		T163	3		T18	1
valid_sources[0x43]	80905	1			T32	1		T38	1		T84	1
valid_sources[0x44]	61097	1			T32	2		T38	4		T8	1
valid_sources[0x45]	85346	1			T38	7		T20	7		T60	60
valid_sources[0x46]	60343	1			T38	6		T39	1		T566	1
valid_sources[0x47]	74093	1			T32	3		T37	1		T38	7
valid_sources[0x48]	61271	1			T32	1		T38	9		T161	1
valid_sources[0x49]	62687	1			T38	9		T39	2		T20	4
valid_sources[0x4a]	60759	1			T38	5		T566	1		T400	3
valid_sources[0x4b]	60860	1			T37	1		T38	9		T20	8
valid_sources[0x4c]	61093	1			T30	35		T38	7		T20	4
valid_sources[0x4d]	60301	1			T38	9		T39	1		T51	37
valid_sources[0x4e]	60676	1			T38	4		T71	58		T8	1
valid_sources[0x4f]	61123	1			T50	12		T8	1		T60	54
valid_sources[0x50]	61282	1			T38	7		T91	2		T8	1
valid_sources[0x51]	61119	1			T32	3		T38	9		T61	3
valid_sources[0x52]	113894	1			T32	1		T33	2		T38	1
valid_sources[0x53]	61962	1			T32	1		T38	7		T18	1
valid_sources[0x54]	62332	1			T36	1		T38	13		T20	7
valid_sources[0x55]	62059	1			T28	6		T38	2		T20	8
valid_sources[0x56]	80627	1			T32	1		T38	9		T8	1
valid_sources[0x57]	60970	1			T32	2		T38	7		T20	4
valid_sources[0x58]	173705	1			T32	2		T38	7		T8	1
valid_sources[0x59]	60374	1			T43	3		T37	1		T38	8
valid_sources[0x5a]	61665	1			T38	7		T8	1		T20	4
valid_sources[0x5b]	62141	1			T37	3		T38	6		T20	6
valid_sources[0x5c]	63358	1			T38	5		T49	1		T20	2
valid_sources[0x5d]	61358	1			T38	5		T8	1		T20	1
valid_sources[0x5e]	60428	1			T32	1		T38	2		T20	3
valid_sources[0x5f]	66577	1			T37	1		T38	3		T162	1
valid_sources[0x60]	76722	1			T32	2		T38	6		T162	3
valid_sources[0x61]	81316	1			T32	1		T38	7		T400	1
valid_sources[0x62]	61538	1			T32	1		T38	5		T72	1
valid_sources[0x63]	125762	1			T32	1		T38	9		T161	1
valid_sources[0x64]	132580	1			T38	6		T20	3		T60	25
valid_sources[0x65]	61740	1			T32	1		T36	1		T37	1
valid_sources[0x66]	62291	1			T32	3		T37	1		T38	5
valid_sources[0x67]	63324	1			T32	3		T38	11		T39	1
valid_sources[0x68]	65324	1			T43	12		T32	2		T38	8
valid_sources[0x69]	99350	1			T43	5		T38	3		T8	2
valid_sources[0x6a]	71028	1			T3	1		T37	1		T38	2
valid_sources[0x6b]	81614	1			T32	2		T38	4		T39	1
valid_sources[0x6c]	61219	1			T32	1		T38	2		T8	2
valid_sources[0x6d]	69171	1			T32	1		T38	4		T82	1
valid_sources[0x6e]	61597	1			T32	1		T37	1		T38	5
valid_sources[0x6f]	61091	1			T38	9		T163	2		T8	2
valid_sources[0x70]	60587	1			T32	1		T38	2		T72	1
valid_sources[0x71]	60439	1			T43	15		T38	9		T7	4
valid_sources[0x72]	93363	1			T32	3		T38	4		T39	3
valid_sources[0x73]	65905	1			T38	12		T8	3		T20	4
valid_sources[0x74]	60457	1			T43	9		T36	1		T38	4
valid_sources[0x75]	61110	1			T32	1		T38	7		T8	1
valid_sources[0x76]	76675	1			T32	1		T37	1		T38	7
valid_sources[0x77]	112433	1			T38	4		T39	1		T230	1
valid_sources[0x78]	80141	1			T38	6		T8	4		T20	9
valid_sources[0x79]	61435	1			T38	7		T20	2		T60	11
valid_sources[0x7a]	60677	1			T38	1		T8	1		T20	3
valid_sources[0x7b]	60051	1			T32	2		T37	2		T38	7
valid_sources[0x7c]	61064	1			T32	1		T38	2		T25	2
valid_sources[0x7d]	85884	1			T38	10		T18	1		T20	3
valid_sources[0x7e]	61152	1			T32	2		T37	1		T38	9
valid_sources[0x7f]	60548	1			T33	1		T38	10		T20	8
valid_sources[0x80]	60770	1			T38	5		T82	1		T8	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9930033

1

T1

4

T2

1

T3

3

values[0x0]

all_enables

biggest_size

279468

1

T1

2

T2

3

T3

4

values[0x1]

all_enables

biggest_size

261613

1

T1

1

T2

2

T28

1