Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

9875182

1

T1

11

T2

6

T3

7

full_word

10472145

1

T1

7

T2

6

T3

7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	20347047	1			T1	18		T2	12		T3	14
auto[TlIntgErrCmd]	97	1			T235	3		T245	8		T246	9
auto[TlIntgErrData]	105	1			T235	3		T245	5		T246	7
auto[TlIntgErrBoth]	78	1			T235	4		T245	7		T246	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19663569

1

T1

7

T2

3

T3

7

auto[1]

683758

1

T1

11

T2

9

T3

7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9733217	1			T1	3		T2	2		T3	4
auto[TlIntgErrNone]	partial	auto[1]	141709	1			T1	8		T2	4		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	9930229	1			T1	4		T2	1		T3	3
auto[TlIntgErrNone]	full_word	auto[1]	541892	1			T1	3		T2	5		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T245	3		T246	5		T260	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T235	2		T245	4		T246	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T245	1		T559	1		T560	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T235	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	49	1			T235	3		T245	1		T246	6
auto[TlIntgErrData]	partial	auto[1]	48	1			T245	2		T246	1		T260	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T245	2		T561	1		T562	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T556	1		T559	1		T563	1
auto[TlIntgErrBoth]	partial	auto[0]	23	1			T245	2		T246	1		T260	1
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T235	4		T245	5		T246	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T246	1		T257	1		T560	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T564	1		T563	1		T565	1