Line Coverage for Module :
prim_generic_ram_1p
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 6 | 85.71 |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
41 logic unused_cfg;
42 0/1 ==> assign unused_cfg = ^cfg_i;
43
44 // Width of internal write mask. Note wmask_i input into the module is always assumed
45 // to be the full bit mask
46 localparam int MaskWidth = Width / DataBitsPerMask;
47
48 logic [Width-1:0] mem [Depth];
49 logic [MaskWidth-1:0] wmask;
50
51 for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
52 unreachable assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
53
54 // Ensure that all mask bits within a group have the same value for a write
55 `ASSERT(MaskCheck_A, req_i && write_i |->
56 wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
57 clk_i, '0)
58 end
59
60 // using always instead of always_ff to avoid 'ICPD - illegal combination of drivers' error
61 // thrown when using $readmemh system task to backdoor load an image
62 always @(posedge clk_i) begin
63 1/1 if (req_i) begin
Tests: T1 T2 T3
64 1/1 if (write_i) begin
Tests: T3 T28 T29
65 1/1 for (int i=0; i < MaskWidth; i = i + 1) begin
Tests: T3 T28 T29
66 1/1 if (wmask[i]) begin
Tests: T3 T28 T29
67 1/1 mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
Tests: T3 T28 T29
68 wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69 end
==> MISSING_ELSE
70 end
71 end else begin
72 1/1 rdata_o <= mem[addr_i];
Tests: T3 T29 T31
73 end
74 end
MISSING_ELSE
Branch Coverage for Module :
prim_generic_ram_1p
| Line No. | Total | Covered | Percent |
Branches |
|
3 |
3 |
100.00 |
IF |
63 |
3 |
3 |
100.00 |
63 if (req_i) begin
-1-
64 if (write_i) begin
-2-
65 for (int i=0; i < MaskWidth; i = i + 1) begin
==>
66 if (wmask[i]) begin
67 mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
68 wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69 end
70 end
71 end else begin
72 rdata_o <= mem[addr_i];
==>
73 end
74 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T3,T28,T29 |
1 |
0 |
Covered |
T3,T29,T31 |
0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_generic_ram_1p
Assertion Details
DataBitsPerMaskCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3730 |
3730 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T40 |
1 |
1 |
0 |
0 |
T41 |
1 |
1 |
0 |
0 |
T42 |
1 |
1 |
0 |
0 |
T43 |
1 |
1 |
0 |
0 |
gen_wmask[0].MaskCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
586533067 |
1024328 |
0 |
0 |
T3 |
10220 |
3 |
0 |
0 |
T28 |
8434 |
3 |
0 |
0 |
T29 |
19184 |
63 |
0 |
0 |
T30 |
12616 |
21 |
0 |
0 |
T31 |
8856 |
0 |
0 |
0 |
T32 |
35444 |
85 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T34 |
0 |
15 |
0 |
0 |
T35 |
0 |
87 |
0 |
0 |
T36 |
0 |
10 |
0 |
0 |
T40 |
2350 |
0 |
0 |
0 |
T41 |
6622 |
0 |
0 |
0 |
T42 |
16481 |
0 |
0 |
0 |
T43 |
55030 |
12 |
0 |
0 |
gen_wmask[1].MaskCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
586533067 |
1024328 |
0 |
0 |
T3 |
10220 |
3 |
0 |
0 |
T28 |
8434 |
3 |
0 |
0 |
T29 |
19184 |
63 |
0 |
0 |
T30 |
12616 |
21 |
0 |
0 |
T31 |
8856 |
0 |
0 |
0 |
T32 |
35444 |
85 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T34 |
0 |
15 |
0 |
0 |
T35 |
0 |
87 |
0 |
0 |
T36 |
0 |
10 |
0 |
0 |
T40 |
2350 |
0 |
0 |
0 |
T41 |
6622 |
0 |
0 |
0 |
T42 |
16481 |
0 |
0 |
0 |
T43 |
55030 |
12 |
0 |
0 |
gen_wmask[2].MaskCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
586533067 |
1024328 |
0 |
0 |
T3 |
10220 |
3 |
0 |
0 |
T28 |
8434 |
3 |
0 |
0 |
T29 |
19184 |
63 |
0 |
0 |
T30 |
12616 |
21 |
0 |
0 |
T31 |
8856 |
0 |
0 |
0 |
T32 |
35444 |
85 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T34 |
0 |
15 |
0 |
0 |
T35 |
0 |
87 |
0 |
0 |
T36 |
0 |
10 |
0 |
0 |
T40 |
2350 |
0 |
0 |
0 |
T41 |
6622 |
0 |
0 |
0 |
T42 |
16481 |
0 |
0 |
0 |
T43 |
55030 |
12 |
0 |
0 |
gen_wmask[3].MaskCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
586533067 |
1024328 |
0 |
0 |
T3 |
10220 |
3 |
0 |
0 |
T28 |
8434 |
3 |
0 |
0 |
T29 |
19184 |
63 |
0 |
0 |
T30 |
12616 |
21 |
0 |
0 |
T31 |
8856 |
0 |
0 |
0 |
T32 |
35444 |
85 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T34 |
0 |
15 |
0 |
0 |
T35 |
0 |
87 |
0 |
0 |
T36 |
0 |
10 |
0 |
0 |
T40 |
2350 |
0 |
0 |
0 |
T41 |
6622 |
0 |
0 |
0 |
T42 |
16481 |
0 |
0 |
0 |
T43 |
55030 |
12 |
0 |
0 |