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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.39 98.22 96.08 97.44 94.92 98.38 98.17 98.55


Total test records in report: 3905
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T3224 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_max_inter_pkt_delay.2655846867 Sep 01 01:16:17 PM UTC 24 Sep 01 01:17:06 PM UTC 24 2067726666 ps
T3225 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_iso_retraction.1574125578 Sep 01 01:16:17 PM UTC 24 Sep 01 01:17:12 PM UTC 24 5609133702 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/65.usbdev_endpoint_types.2871590545 Sep 01 01:18:28 PM UTC 24 Sep 01 01:18:31 PM UTC 24 215125683 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/65.usbdev_fifo_levels.1715047208 Sep 01 01:18:28 PM UTC 24 Sep 01 01:18:31 PM UTC 24 260662530 ps
T3226 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/67.usbdev_fifo_levels.767678323 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:31 PM UTC 24 253086929 ps
T3227 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_phy_config_usb_ref_disable.1740111180 Sep 01 01:17:18 PM UTC 24 Sep 01 01:17:20 PM UTC 24 146346084 ps
T3228 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_phy_pins_sense.2815788905 Sep 01 01:17:18 PM UTC 24 Sep 01 01:17:20 PM UTC 24 49560649 ps
T3229 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/62.usbdev_tx_rx_disruption.3732202625 Sep 01 01:18:28 PM UTC 24 Sep 01 01:18:31 PM UTC 24 636229545 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/66.usbdev_fifo_levels.1200186625 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:31 PM UTC 24 284231651 ps
T3230 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_pkt_received.2524268163 Sep 01 01:17:18 PM UTC 24 Sep 01 01:17:20 PM UTC 24 176083969 ps
T3231 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_rx_crc_err.370683812 Sep 01 01:17:18 PM UTC 24 Sep 01 01:17:20 PM UTC 24 153995987 ps
T3232 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_random_length_out_transaction.695388616 Sep 01 01:17:18 PM UTC 24 Sep 01 01:17:20 PM UTC 24 184192745 ps
T3233 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_setup_stage.1004717285 Sep 01 01:17:18 PM UTC 24 Sep 01 01:17:20 PM UTC 24 166068763 ps
T3234 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_random_length_in_transaction.352074251 Sep 01 01:17:18 PM UTC 24 Sep 01 01:17:20 PM UTC 24 221033689 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/67.usbdev_endpoint_types.660426324 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:31 PM UTC 24 421047878 ps
T3235 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_pkt_sent.2931911329 Sep 01 01:17:18 PM UTC 24 Sep 01 01:17:20 PM UTC 24 164795678 ps
T3236 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_phy_config_pinflip.3773358885 Sep 01 01:17:18 PM UTC 24 Sep 01 01:17:21 PM UTC 24 213287451 ps
T3237 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/68.usbdev_fifo_levels.2653094148 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:31 PM UTC 24 250595023 ps
T3238 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/69.usbdev_fifo_levels.3404630698 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:31 PM UTC 24 290930252 ps
T3239 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_stall_priority_over_nak.2305854032 Sep 01 01:17:18 PM UTC 24 Sep 01 01:17:21 PM UTC 24 203926226 ps
T3240 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_setup_trans_ignored.1218655706 Sep 01 01:17:18 PM UTC 24 Sep 01 01:17:21 PM UTC 24 175632585 ps
T3241 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_stall_trans.2844076683 Sep 01 01:17:18 PM UTC 24 Sep 01 01:17:21 PM UTC 24 156904155 ps
T3242 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_alert_test.2636475993 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:21 PM UTC 24 36109897 ps
T3243 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_smoke.3787451316 Sep 01 01:17:18 PM UTC 24 Sep 01 01:17:21 PM UTC 24 209553467 ps
T3244 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_rx_full.2918119871 Sep 01 01:17:18 PM UTC 24 Sep 01 01:17:21 PM UTC 24 396980661 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/51.usbdev_fifo_levels.294151959 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:21 PM UTC 24 273778911 ps
T506 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/51.usbdev_endpoint_types.552004102 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:21 PM UTC 24 207542738 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/50.usbdev_fifo_levels.2937206056 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:21 PM UTC 24 260081120 ps
T3245 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/53.usbdev_fifo_levels.694967843 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:21 PM UTC 24 149107394 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/52.usbdev_fifo_levels.3550874274 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:21 PM UTC 24 277457082 ps
T3246 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_tx_rx_disruption.1269308784 Sep 01 01:17:18 PM UTC 24 Sep 01 01:17:21 PM UTC 24 553065812 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/54.usbdev_fifo_levels.217670635 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 263123018 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/52.usbdev_endpoint_types.2079522607 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 579920218 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/50.usbdev_endpoint_types.8407449 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 666888884 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/56.usbdev_fifo_levels.1926607497 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 284918551 ps
T3247 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/50.usbdev_tx_rx_disruption.57302392 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 613188505 ps
T534 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/56.usbdev_endpoint_types.3585883028 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 356313849 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/59.usbdev_fifo_levels.3661409441 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 247835695 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/52.usbdev_tx_rx_disruption.3115863865 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 605951020 ps
T3248 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_stream_len_max.2968999290 Sep 01 01:17:18 PM UTC 24 Sep 01 01:17:22 PM UTC 24 824090612 ps
T529 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/59.usbdev_endpoint_types.1367139209 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 190653708 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/57.usbdev_endpoint_types.3915675578 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 436439944 ps
T3249 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/51.usbdev_tx_rx_disruption.2710976274 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 523680694 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/57.usbdev_fifo_levels.1495995652 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 278823300 ps
T3250 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/60.usbdev_fifo_levels.2796452119 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 241455632 ps
T3251 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/54.usbdev_tx_rx_disruption.2726418378 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 433299801 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/61.usbdev_fifo_levels.1749287260 Sep 01 01:17:20 PM UTC 24 Sep 01 01:17:22 PM UTC 24 262702717 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/58.usbdev_fifo_levels.4253497682 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 271644178 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/55.usbdev_fifo_levels.4086721623 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 274995664 ps
T3252 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/53.usbdev_tx_rx_disruption.2265474343 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 543313654 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/53.usbdev_endpoint_types.475177895 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 582155244 ps
T505 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/54.usbdev_endpoint_types.4269522048 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 600778143 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/62.usbdev_endpoint_types.527497619 Sep 01 01:17:20 PM UTC 24 Sep 01 01:17:22 PM UTC 24 265817469 ps
T3253 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/57.usbdev_tx_rx_disruption.2116978726 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 472798436 ps
T3254 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/55.usbdev_tx_rx_disruption.1356201268 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 538386405 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/61.usbdev_endpoint_types.2432695655 Sep 01 01:17:20 PM UTC 24 Sep 01 01:17:22 PM UTC 24 430636308 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/55.usbdev_endpoint_types.4172228530 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 377934581 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/60.usbdev_endpoint_types.3677658391 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 546594691 ps
T3255 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/56.usbdev_tx_rx_disruption.776862547 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 570678572 ps
T3256 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/58.usbdev_tx_rx_disruption.3484902338 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:22 PM UTC 24 543264717 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/58.usbdev_endpoint_types.3760347395 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:23 PM UTC 24 687473671 ps
T3257 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/60.usbdev_tx_rx_disruption.3539397654 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:23 PM UTC 24 601179854 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/59.usbdev_tx_rx_disruption.2728811770 Sep 01 01:17:19 PM UTC 24 Sep 01 01:17:23 PM UTC 24 601723786 ps
T3258 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/61.usbdev_tx_rx_disruption.2050371405 Sep 01 01:17:20 PM UTC 24 Sep 01 01:17:23 PM UTC 24 617989156 ps
T3259 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_streaming_out.3268592065 Sep 01 01:17:18 PM UTC 24 Sep 01 01:17:40 PM UTC 24 2987184304 ps
T3260 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_low_speed_traffic.4086808571 Sep 01 01:16:17 PM UTC 24 Sep 01 01:18:01 PM UTC 24 4210675906 ps
T3261 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_spurious_pids_ignored.1682910837 Sep 01 01:17:18 PM UTC 24 Sep 01 01:18:07 PM UTC 24 2168454191 ps
T3262 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_pkt_buffer.4186712936 Sep 01 01:17:18 PM UTC 24 Sep 01 01:18:09 PM UTC 24 22077068432 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/63.usbdev_fifo_levels.322661858 Sep 01 01:18:28 PM UTC 24 Sep 01 01:18:30 PM UTC 24 191547604 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/64.usbdev_fifo_levels.2454880682 Sep 01 01:18:28 PM UTC 24 Sep 01 01:18:30 PM UTC 24 162660758 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/64.usbdev_endpoint_types.752987684 Sep 01 01:18:28 PM UTC 24 Sep 01 01:18:30 PM UTC 24 167428675 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/63.usbdev_endpoint_types.2542773660 Sep 01 01:18:28 PM UTC 24 Sep 01 01:18:31 PM UTC 24 388804050 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/62.usbdev_fifo_levels.2000460546 Sep 01 01:18:28 PM UTC 24 Sep 01 01:18:31 PM UTC 24 325231213 ps
T513 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/66.usbdev_endpoint_types.2002184862 Sep 01 01:18:28 PM UTC 24 Sep 01 01:18:31 PM UTC 24 236298869 ps
T530 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/68.usbdev_endpoint_types.2398002467 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:31 PM UTC 24 168096439 ps
T3263 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/66.usbdev_tx_rx_disruption.1010252743 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:31 PM UTC 24 637338586 ps
T3264 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/68.usbdev_tx_rx_disruption.2072402205 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:31 PM UTC 24 443256480 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/67.usbdev_tx_rx_disruption.638336510 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:31 PM UTC 24 599719543 ps
T3265 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/71.usbdev_fifo_levels.989793382 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:31 PM UTC 24 278435048 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/70.usbdev_fifo_levels.2222624006 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 252457944 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/71.usbdev_endpoint_types.176575922 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 334031847 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/70.usbdev_endpoint_types.2487310386 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 513926886 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/72.usbdev_fifo_levels.1933455995 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 259011368 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/69.usbdev_endpoint_types.3039182460 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 507969305 ps
T3266 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/69.usbdev_tx_rx_disruption.2681783883 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 476706130 ps
T3267 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/119.usbdev_endpoint_types.312382716 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:01 PM UTC 24 405907770 ps
T3268 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/73.usbdev_fifo_levels.2326978874 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 260029048 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/73.usbdev_endpoint_types.1224081707 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 330301321 ps
T3269 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/71.usbdev_tx_rx_disruption.1189721174 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 498625180 ps
T3270 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/76.usbdev_fifo_levels.3718129990 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 196740223 ps
T3271 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/78.usbdev_endpoint_types.1920224247 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 164670572 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/77.usbdev_fifo_levels.1472712966 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 275159172 ps
T3272 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/75.usbdev_fifo_levels.2359150972 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 147541832 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/80.usbdev_fifo_levels.890812977 Sep 01 01:18:30 PM UTC 24 Sep 01 01:18:32 PM UTC 24 173658685 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/72.usbdev_endpoint_types.217314551 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 495924316 ps
T3273 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/70.usbdev_tx_rx_disruption.3389409590 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 541057155 ps
T3274 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/80.usbdev_endpoint_types.2428631848 Sep 01 01:18:30 PM UTC 24 Sep 01 01:18:32 PM UTC 24 165659880 ps
T526 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/77.usbdev_endpoint_types.1594457432 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 243866868 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/74.usbdev_fifo_levels.411604168 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 313523745 ps
T3275 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/73.usbdev_tx_rx_disruption.4123742569 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 479881120 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/81.usbdev_endpoint_types.2770505032 Sep 01 01:18:30 PM UTC 24 Sep 01 01:18:32 PM UTC 24 413528391 ps
T3276 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/72.usbdev_tx_rx_disruption.2383284232 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 579020866 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/76.usbdev_endpoint_types.2169124588 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 325918885 ps
T3277 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/74.usbdev_tx_rx_disruption.2224083070 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 428350496 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/74.usbdev_endpoint_types.3609466326 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:32 PM UTC 24 394394570 ps
T3278 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/79.usbdev_fifo_levels.3115237474 Sep 01 01:18:30 PM UTC 24 Sep 01 01:18:32 PM UTC 24 242924961 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/82.usbdev_endpoint_types.3948362530 Sep 01 01:18:30 PM UTC 24 Sep 01 01:18:32 PM UTC 24 290726242 ps
T523 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/79.usbdev_endpoint_types.3906524566 Sep 01 01:18:30 PM UTC 24 Sep 01 01:18:32 PM UTC 24 306117947 ps
T3279 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/84.usbdev_endpoint_types.765093882 Sep 01 01:18:30 PM UTC 24 Sep 01 01:18:32 PM UTC 24 179236516 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/83.usbdev_fifo_levels.2684507960 Sep 01 01:18:30 PM UTC 24 Sep 01 01:18:32 PM UTC 24 242196362 ps
T535 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/83.usbdev_endpoint_types.238292835 Sep 01 01:18:30 PM UTC 24 Sep 01 01:18:32 PM UTC 24 260589702 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/78.usbdev_fifo_levels.684671936 Sep 01 01:18:30 PM UTC 24 Sep 01 01:18:32 PM UTC 24 260081869 ps
T3280 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/81.usbdev_fifo_levels.3908824165 Sep 01 01:18:30 PM UTC 24 Sep 01 01:18:33 PM UTC 24 277668435 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/75.usbdev_endpoint_types.436770502 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:33 PM UTC 24 735815823 ps
T3281 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/77.usbdev_tx_rx_disruption.300981367 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:33 PM UTC 24 468957550 ps
T3282 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/75.usbdev_tx_rx_disruption.2384389761 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:33 PM UTC 24 590882193 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/82.usbdev_fifo_levels.1502840626 Sep 01 01:18:30 PM UTC 24 Sep 01 01:18:33 PM UTC 24 312213822 ps
T3283 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/79.usbdev_tx_rx_disruption.85563693 Sep 01 01:18:30 PM UTC 24 Sep 01 01:18:33 PM UTC 24 473164050 ps
T3284 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/81.usbdev_tx_rx_disruption.642198087 Sep 01 01:18:30 PM UTC 24 Sep 01 01:18:33 PM UTC 24 536584547 ps
T3285 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/78.usbdev_tx_rx_disruption.2931290422 Sep 01 01:18:30 PM UTC 24 Sep 01 01:18:33 PM UTC 24 617697469 ps
T3286 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/76.usbdev_tx_rx_disruption.1663879248 Sep 01 01:18:29 PM UTC 24 Sep 01 01:18:33 PM UTC 24 607869083 ps
T3287 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/83.usbdev_tx_rx_disruption.767283007 Sep 01 01:18:30 PM UTC 24 Sep 01 01:18:33 PM UTC 24 578073016 ps
T3288 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/82.usbdev_tx_rx_disruption.3562820368 Sep 01 01:18:30 PM UTC 24 Sep 01 01:18:33 PM UTC 24 569552421 ps
T3289 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/80.usbdev_tx_rx_disruption.2283295327 Sep 01 01:18:30 PM UTC 24 Sep 01 01:18:33 PM UTC 24 655082633 ps
T3290 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/85.usbdev_endpoint_types.2833760830 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:44 PM UTC 24 167084987 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/84.usbdev_fifo_levels.2382642285 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:44 PM UTC 24 268752680 ps
T3291 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/85.usbdev_fifo_levels.2360749499 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:44 PM UTC 24 300541293 ps
T3292 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/86.usbdev_fifo_levels.2561278954 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:44 PM UTC 24 179027372 ps
T3293 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/88.usbdev_fifo_levels.3042417667 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:44 PM UTC 24 167285551 ps
T3294 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/87.usbdev_fifo_levels.1186157562 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:44 PM UTC 24 171516285 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/86.usbdev_endpoint_types.3011004327 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:44 PM UTC 24 382761741 ps
T517 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/121.usbdev_endpoint_types.2725930240 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:01 PM UTC 24 344276703 ps
T503 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/89.usbdev_endpoint_types.2446054044 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:44 PM UTC 24 243026329 ps
T3295 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/87.usbdev_endpoint_types.2279989739 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:44 PM UTC 24 297230236 ps
T3296 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/84.usbdev_tx_rx_disruption.111109140 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:44 PM UTC 24 547266426 ps
T3297 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/92.usbdev_fifo_levels.1737357467 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:44 PM UTC 24 149855131 ps
T3298 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/90.usbdev_endpoint_types.3451607028 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:44 PM UTC 24 263677433 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/90.usbdev_fifo_levels.1520055389 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:45 PM UTC 24 196779627 ps
T3299 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/86.usbdev_tx_rx_disruption.1944643525 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:45 PM UTC 24 490485838 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/89.usbdev_fifo_levels.1449815139 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:45 PM UTC 24 271022949 ps
T3300 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/85.usbdev_tx_rx_disruption.1913825883 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:45 PM UTC 24 576805063 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/91.usbdev_fifo_levels.3470713336 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:45 PM UTC 24 251142657 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/93.usbdev_fifo_levels.3121441034 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:45 PM UTC 24 181759283 ps
T3301 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/89.usbdev_tx_rx_disruption.3043922467 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:45 PM UTC 24 552323517 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/88.usbdev_endpoint_types.980872158 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:45 PM UTC 24 529942316 ps
T3302 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/91.usbdev_tx_rx_disruption.3512742878 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:45 PM UTC 24 480827378 ps
T3303 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/116.usbdev_tx_rx_disruption.1511515961 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:01 PM UTC 24 609540898 ps
T3304 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/87.usbdev_tx_rx_disruption.3313051701 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:45 PM UTC 24 589003603 ps
T3305 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/92.usbdev_endpoint_types.3221741361 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:45 PM UTC 24 638309353 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/91.usbdev_endpoint_types.2562910665 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:45 PM UTC 24 480722871 ps
T3306 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/88.usbdev_tx_rx_disruption.2092549245 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:45 PM UTC 24 605308330 ps
T3307 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/97.usbdev_fifo_levels.2327054043 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:45 PM UTC 24 173987367 ps
T3308 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/90.usbdev_tx_rx_disruption.3325997465 Sep 01 01:19:42 PM UTC 24 Sep 01 01:19:45 PM UTC 24 610943297 ps
T3309 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/120.usbdev_fifo_levels.142184683 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:01 PM UTC 24 288978396 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/114.usbdev_endpoint_types.3606365356 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:01 PM UTC 24 611042530 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/94.usbdev_fifo_levels.3541610870 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:45 PM UTC 24 275344321 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/95.usbdev_fifo_levels.2056887551 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:45 PM UTC 24 271737006 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/96.usbdev_fifo_levels.1339704470 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:45 PM UTC 24 251365186 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/97.usbdev_endpoint_types.1494158985 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:45 PM UTC 24 402483108 ps
T3310 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/99.usbdev_fifo_levels.2449457687 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:45 PM UTC 24 334547330 ps
T3311 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/101.usbdev_fifo_levels.1586099252 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:45 PM UTC 24 195713644 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/94.usbdev_endpoint_types.3247854773 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:45 PM UTC 24 427210369 ps
T501 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/101.usbdev_endpoint_types.1732929584 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 276900059 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/100.usbdev_fifo_levels.1943992550 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 319250871 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/93.usbdev_endpoint_types.1400145544 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 634486242 ps
T3312 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/95.usbdev_endpoint_types.4011083396 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 602894508 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/104.usbdev_fifo_levels.2266280720 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 265061275 ps
T3313 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/96.usbdev_tx_rx_disruption.217316876 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 514348493 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/96.usbdev_endpoint_types.1006214298 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 440561537 ps
T508 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/99.usbdev_endpoint_types.873681940 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 308471349 ps
T3314 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/92.usbdev_tx_rx_disruption.3489393601 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 620999677 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/98.usbdev_endpoint_types.1223476865 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 412336700 ps
T3315 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/93.usbdev_tx_rx_disruption.1094359377 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 532444892 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/102.usbdev_fifo_levels.3182220242 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 279366677 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/105.usbdev_endpoint_types.443932467 Sep 01 01:19:44 PM UTC 24 Sep 01 01:19:46 PM UTC 24 305727168 ps
T3316 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/107.usbdev_endpoint_types.3917721582 Sep 01 01:19:44 PM UTC 24 Sep 01 01:19:46 PM UTC 24 258388030 ps
T3317 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/94.usbdev_tx_rx_disruption.1191491060 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 476731602 ps
T3318 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/98.usbdev_fifo_levels.545624971 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 270171816 ps
T3319 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/103.usbdev_fifo_levels.4165295150 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 261272529 ps
T3320 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/102.usbdev_endpoint_types.1230103241 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 305868476 ps
T3321 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/106.usbdev_endpoint_types.3138483894 Sep 01 01:19:44 PM UTC 24 Sep 01 01:19:46 PM UTC 24 479192948 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/103.usbdev_endpoint_types.3343650421 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 411253022 ps
T3322 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/100.usbdev_endpoint_types.895724764 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 318327340 ps
T3323 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/97.usbdev_tx_rx_disruption.614904145 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 506988015 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/104.usbdev_endpoint_types.3919403205 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 478384044 ps
T3324 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/95.usbdev_tx_rx_disruption.1862451286 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 645737526 ps
T3325 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/99.usbdev_tx_rx_disruption.1538106582 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 620372199 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/106.usbdev_fifo_levels.3795061822 Sep 01 01:19:44 PM UTC 24 Sep 01 01:19:46 PM UTC 24 254302377 ps
T3326 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/98.usbdev_tx_rx_disruption.1320352724 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 512138793 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/105.usbdev_fifo_levels.4066530445 Sep 01 01:19:44 PM UTC 24 Sep 01 01:19:46 PM UTC 24 294065476 ps
T3327 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/102.usbdev_tx_rx_disruption.3008383755 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 512862247 ps
T3328 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/100.usbdev_tx_rx_disruption.3384659301 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:46 PM UTC 24 681532731 ps
T3329 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/101.usbdev_tx_rx_disruption.2693098610 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:47 PM UTC 24 631503797 ps
T3330 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/105.usbdev_tx_rx_disruption.1625702121 Sep 01 01:19:44 PM UTC 24 Sep 01 01:19:47 PM UTC 24 568794277 ps
T3331 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/104.usbdev_tx_rx_disruption.1905477452 Sep 01 01:19:44 PM UTC 24 Sep 01 01:19:47 PM UTC 24 594791699 ps
T3332 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/103.usbdev_tx_rx_disruption.3129339296 Sep 01 01:19:43 PM UTC 24 Sep 01 01:19:47 PM UTC 24 549876768 ps
T3333 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/106.usbdev_tx_rx_disruption.416141156 Sep 01 01:19:44 PM UTC 24 Sep 01 01:19:47 PM UTC 24 623042843 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/108.usbdev_fifo_levels.4121085216 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:00 PM UTC 24 256580013 ps
T3334 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/110.usbdev_endpoint_types.2639958872 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:00 PM UTC 24 179289256 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/107.usbdev_fifo_levels.1218522837 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:00 PM UTC 24 282451473 ps
T3335 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/109.usbdev_fifo_levels.3635227829 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:00 PM UTC 24 262503957 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/110.usbdev_fifo_levels.3659788798 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:00 PM UTC 24 196428481 ps
T3336 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/112.usbdev_endpoint_types.927025585 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:00 PM UTC 24 274233120 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/112.usbdev_fifo_levels.4163371875 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:00 PM UTC 24 245024762 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/115.usbdev_endpoint_types.2044179817 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:01 PM UTC 24 763612435 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/111.usbdev_fifo_levels.371123781 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:00 PM UTC 24 271934058 ps
T3337 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/107.usbdev_tx_rx_disruption.3589357818 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:00 PM UTC 24 560684215 ps
T3338 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/108.usbdev_tx_rx_disruption.3130303365 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:00 PM UTC 24 501152847 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/109.usbdev_endpoint_types.593754118 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:00 PM UTC 24 718207880 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/108.usbdev_endpoint_types.3489554924 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:00 PM UTC 24 724808525 ps
T3339 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/114.usbdev_fifo_levels.707229399 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:00 PM UTC 24 270541317 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/111.usbdev_endpoint_types.201874752 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:00 PM UTC 24 585263244 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/115.usbdev_fifo_levels.3598284205 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:00 PM UTC 24 153921982 ps
T3340 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/121.usbdev_fifo_levels.560010846 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:01 PM UTC 24 185245713 ps
T3341 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/110.usbdev_tx_rx_disruption.2737729963 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:00 PM UTC 24 515822126 ps
T3342 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/109.usbdev_tx_rx_disruption.1335368090 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:00 PM UTC 24 538012288 ps
T521 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/118.usbdev_endpoint_types.109736306 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:01 PM UTC 24 226781624 ps
T532 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/117.usbdev_endpoint_types.2654592883 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:01 PM UTC 24 255563493 ps
T3343 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/116.usbdev_fifo_levels.144754011 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:01 PM UTC 24 156042130 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/113.usbdev_fifo_levels.2426116661 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:01 PM UTC 24 253055272 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/116.usbdev_endpoint_types.3410114332 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:01 PM UTC 24 501142334 ps
T3344 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/111.usbdev_tx_rx_disruption.1575358269 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:01 PM UTC 24 599371941 ps
T3345 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/112.usbdev_tx_rx_disruption.2672744252 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:01 PM UTC 24 568914700 ps
T3346 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/113.usbdev_endpoint_types.2778513202 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:01 PM UTC 24 400991524 ps
T3347 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/123.usbdev_endpoint_types.133645487 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:01 PM UTC 24 252295197 ps
T3348 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/120.usbdev_endpoint_types.2351397306 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:01 PM UTC 24 178729800 ps
T3349 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/114.usbdev_tx_rx_disruption.337977705 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:01 PM UTC 24 610448162 ps
T3350 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/113.usbdev_tx_rx_disruption.3996726605 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:01 PM UTC 24 676388667 ps
T3351 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/117.usbdev_fifo_levels.3915857820 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:01 PM UTC 24 278433065 ps
T3352 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/118.usbdev_fifo_levels.2487926369 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:01 PM UTC 24 256115364 ps
T3353 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/115.usbdev_tx_rx_disruption.3184068046 Sep 01 01:20:57 PM UTC 24 Sep 01 01:21:01 PM UTC 24 504123544 ps
T3354 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/117.usbdev_tx_rx_disruption.3197032290 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:01 PM UTC 24 569301219 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/119.usbdev_fifo_levels.2382429077 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:01 PM UTC 24 310668201 ps
T3355 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/118.usbdev_tx_rx_disruption.1302132644 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:01 PM UTC 24 600050335 ps
T3356 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/145.usbdev_fifo_levels.63944648 Sep 01 01:22:16 PM UTC 24 Sep 01 01:22:19 PM UTC 24 292489043 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/123.usbdev_fifo_levels.4231949736 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:02 PM UTC 24 250478867 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/122.usbdev_fifo_levels.959142437 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:02 PM UTC 24 269426814 ps
T3357 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/124.usbdev_endpoint_types.3661398555 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:02 PM UTC 24 341282287 ps
T3358 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/125.usbdev_endpoint_types.3845424053 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:02 PM UTC 24 171813082 ps
T3359 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/119.usbdev_tx_rx_disruption.3616202473 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:02 PM UTC 24 628844480 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/126.usbdev_fifo_levels.3661053724 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:02 PM UTC 24 166402481 ps
T3360 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/120.usbdev_tx_rx_disruption.599661914 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:02 PM UTC 24 632819270 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/122.usbdev_endpoint_types.4154277000 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:02 PM UTC 24 606930781 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/140.usbdev_endpoint_types.3823758255 Sep 01 01:22:16 PM UTC 24 Sep 01 01:22:19 PM UTC 24 787808362 ps
T3361 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/123.usbdev_tx_rx_disruption.1759548476 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:02 PM UTC 24 472187240 ps
T3362 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/128.usbdev_endpoint_types.3795650603 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:02 PM UTC 24 176322298 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/127.usbdev_fifo_levels.1786445413 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:02 PM UTC 24 253265759 ps
T3363 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/121.usbdev_tx_rx_disruption.800542856 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:02 PM UTC 24 483962794 ps
T3364 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/125.usbdev_tx_rx_disruption.501285222 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:02 PM UTC 24 548908202 ps
T3365 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/124.usbdev_fifo_levels.3562453348 Sep 01 01:20:58 PM UTC 24 Sep 01 01:21:02 PM UTC 24 289512642 ps
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