Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9737034	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10332277

1

T1

6

T2

8

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19430549	1			T1	3		T2	7		T3	7
values[0x0]	318813	1			T1	4		T2	3		T3	6
values[0x1]	319949	1			T1	5		T2	4		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7740566	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

12328745

1

T1

7

T2

10

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	154242	1			T41	1		T35	12		T37	2
valid_sources[0x01]	54587	1			T42	1		T32	3		T35	9
valid_sources[0x02]	119295	1			T41	2		T32	1		T35	10
valid_sources[0x03]	55108	1			T35	12		T37	4		T49	9
valid_sources[0x04]	53374	1			T1	1		T2	14		T32	2
valid_sources[0x05]	61090	1			T1	1		T32	6		T35	10
valid_sources[0x06]	109006	1			T30	1		T41	2		T35	19
valid_sources[0x07]	54193	1			T41	1		T35	13		T25	2
valid_sources[0x08]	53226	1			T30	1		T41	1		T32	1
valid_sources[0x09]	54279	1			T1	1		T35	14		T37	4
valid_sources[0x0a]	54718	1			T30	1		T32	1		T34	1
valid_sources[0x0b]	55389	1			T31	1		T32	1		T33	28
valid_sources[0x0c]	53239	1			T41	1		T32	3		T35	11
valid_sources[0x0d]	54293	1			T32	1		T35	13		T37	3
valid_sources[0x0e]	145798	1			T41	1		T42	1		T35	3
valid_sources[0x0f]	175310	1			T41	1		T32	2		T35	15
valid_sources[0x10]	99578	1			T29	1		T32	1		T35	6
valid_sources[0x11]	230499	1			T32	2		T35	9		T37	1
valid_sources[0x12]	53787	1			T32	3		T35	16		T37	3
valid_sources[0x13]	54838	1			T41	3		T35	9		T37	5
valid_sources[0x14]	53638	1			T32	1		T35	15		T49	5
valid_sources[0x15]	52710	1			T35	7		T37	2		T25	1
valid_sources[0x16]	53770	1			T41	1		T42	1		T32	1
valid_sources[0x17]	54935	1			T35	16		T37	3		T49	5
valid_sources[0x18]	103942	1			T32	1		T35	10		T37	1
valid_sources[0x19]	55558	1			T31	1		T39	7		T41	1
valid_sources[0x1a]	53842	1			T32	2		T35	16		T37	5
valid_sources[0x1b]	53913	1			T32	2		T35	12		T23	1
valid_sources[0x1c]	67070	1			T35	14		T37	5		T21	2
valid_sources[0x1d]	54773	1			T35	13		T37	10		T23	1
valid_sources[0x1e]	54603	1			T32	2		T35	12		T37	4
valid_sources[0x1f]	74864	1			T29	1		T35	5		T37	2
valid_sources[0x20]	54202	1			T41	1		T32	2		T35	21
valid_sources[0x21]	59743	1			T3	4		T31	1		T35	21
valid_sources[0x22]	54143	1			T41	1		T32	1		T35	19
valid_sources[0x23]	54245	1			T32	1		T35	16		T37	3
valid_sources[0x24]	64772	1			T32	1		T34	3		T35	10
valid_sources[0x25]	53558	1			T29	3		T35	19		T37	1
valid_sources[0x26]	101521	1			T41	1		T32	2		T34	3
valid_sources[0x27]	64230	1			T32	1		T35	12		T37	3
valid_sources[0x28]	54540	1			T41	3		T42	1		T32	5
valid_sources[0x29]	53727	1			T32	2		T35	10		T37	2
valid_sources[0x2a]	53049	1			T31	2		T32	2		T35	6
valid_sources[0x2b]	160089	1			T32	1		T35	9		T37	5
valid_sources[0x2c]	53157	1			T35	12		T37	2		T49	4
valid_sources[0x2d]	84338	1			T35	15		T37	2		T38	1
valid_sources[0x2e]	53090	1			T32	3		T35	13		T37	6
valid_sources[0x2f]	75622	1			T30	1		T35	14		T37	2
valid_sources[0x30]	57987	1			T35	9		T37	2		T38	1
valid_sources[0x31]	157645	1			T32	1		T34	3		T35	15
valid_sources[0x32]	163695	1			T31	1		T32	3		T35	8
valid_sources[0x33]	54255	1			T32	1		T35	8		T37	3
valid_sources[0x34]	53069	1			T42	1		T35	6		T37	3
valid_sources[0x35]	70545	1			T31	1		T41	1		T35	18
valid_sources[0x36]	53922	1			T41	1		T35	9		T37	2
valid_sources[0x37]	117747	1			T31	1		T41	2		T35	9
valid_sources[0x38]	53535	1			T1	1		T34	2		T35	10
valid_sources[0x39]	82343	1			T32	1		T35	9		T37	3
valid_sources[0x3a]	54225	1			T34	8		T35	9		T37	4
valid_sources[0x3b]	55096	1			T35	20		T37	2		T18	1
valid_sources[0x3c]	154652	1			T3	5		T42	1		T32	3
valid_sources[0x3d]	127001	1			T41	2		T35	16		T37	3
valid_sources[0x3e]	125560	1			T41	2		T35	9		T37	3
valid_sources[0x3f]	54222	1			T32	1		T35	17		T37	5
valid_sources[0x40]	52801	1			T34	28		T35	15		T37	2
valid_sources[0x41]	124882	1			T32	1		T35	14		T37	3
valid_sources[0x42]	53308	1			T32	2		T34	18		T35	12
valid_sources[0x43]	58300	1			T32	1		T35	14		T37	2
valid_sources[0x44]	68131	1			T42	1		T35	10		T37	2
valid_sources[0x45]	53475	1			T30	1		T32	1		T35	14
valid_sources[0x46]	79745	1			T32	2		T35	11		T37	1
valid_sources[0x47]	85316	1			T30	1		T35	17		T37	1
valid_sources[0x48]	65601	1			T41	1		T32	1		T35	16
valid_sources[0x49]	56988	1			T32	1		T35	6		T37	1
valid_sources[0x4a]	127019	1			T32	1		T35	14		T37	3
valid_sources[0x4b]	53064	1			T31	1		T41	1		T35	7
valid_sources[0x4c]	78491	1			T29	2		T41	1		T35	6
valid_sources[0x4d]	53537	1			T31	1		T41	1		T35	8
valid_sources[0x4e]	182924	1			T34	5		T35	11		T37	4
valid_sources[0x4f]	53566	1			T1	1		T35	11		T37	3
valid_sources[0x50]	55141	1			T32	1		T35	9		T37	3
valid_sources[0x51]	54314	1			T41	1		T32	3		T35	14
valid_sources[0x52]	53698	1			T42	1		T35	11		T37	1
valid_sources[0x53]	53262	1			T32	2		T35	9		T37	4
valid_sources[0x54]	53715	1			T32	1		T35	24		T37	1
valid_sources[0x55]	61001	1			T35	14		T37	5		T7	1
valid_sources[0x56]	68667	1			T32	3		T35	5		T49	4
valid_sources[0x57]	135505	1			T34	10		T35	25		T37	1
valid_sources[0x58]	54136	1			T35	10		T37	2		T49	11
valid_sources[0x59]	52786	1			T32	1		T35	13		T37	4
valid_sources[0x5a]	53805	1			T3	3		T31	1		T35	14
valid_sources[0x5b]	118228	1			T32	4		T35	10		T37	6
valid_sources[0x5c]	170391	1			T32	1		T35	18		T37	2
valid_sources[0x5d]	199007	1			T30	1		T41	2		T32	1
valid_sources[0x5e]	113827	1			T35	12		T37	3		T20	2
valid_sources[0x5f]	75595	1			T29	2		T34	13		T35	20
valid_sources[0x60]	54387	1			T30	1		T41	4		T42	1
valid_sources[0x61]	132950	1			T31	1		T35	14		T20	1
valid_sources[0x62]	95363	1			T35	18		T37	1		T23	1
valid_sources[0x63]	54335	1			T34	2		T35	9		T20	2
valid_sources[0x64]	53331	1			T34	7		T35	10		T49	6
valid_sources[0x65]	66044	1			T41	5		T34	7		T35	8
valid_sources[0x66]	135849	1			T31	1		T42	1		T32	1
valid_sources[0x67]	76469	1			T35	17		T37	3		T49	5
valid_sources[0x68]	53876	1			T29	1		T42	1		T32	1
valid_sources[0x69]	53720	1			T42	1		T32	3		T35	26
valid_sources[0x6a]	86490	1			T35	7		T37	1		T22	2
valid_sources[0x6b]	101504	1			T32	2		T35	20		T37	3
valid_sources[0x6c]	54097	1			T31	1		T32	7		T34	2
valid_sources[0x6d]	52904	1			T41	1		T35	12		T37	3
valid_sources[0x6e]	54016	1			T29	1		T32	1		T35	6
valid_sources[0x6f]	68177	1			T41	3		T32	1		T35	11
valid_sources[0x70]	74411	1			T32	1		T35	21		T37	4
valid_sources[0x71]	54572	1			T35	11		T37	3		T17	58
valid_sources[0x72]	54235	1			T32	1		T34	7		T35	9
valid_sources[0x73]	59517	1			T31	3		T41	1		T32	1
valid_sources[0x74]	53692	1			T32	1		T34	6		T35	11
valid_sources[0x75]	73725	1			T32	2		T35	16		T37	1
valid_sources[0x76]	53833	1			T41	1		T35	10		T37	1
valid_sources[0x77]	53343	1			T1	1		T41	2		T35	12
valid_sources[0x78]	62035	1			T41	2		T42	1		T32	1
valid_sources[0x79]	53988	1			T32	2		T35	8		T37	4
valid_sources[0x7a]	71653	1			T35	6		T37	3		T49	6
valid_sources[0x7b]	71934	1			T32	2		T35	13		T37	2
valid_sources[0x7c]	129830	1			T32	1		T34	5		T35	14
valid_sources[0x7d]	83165	1			T1	1		T35	9		T37	3
valid_sources[0x7e]	65439	1			T41	1		T35	9		T37	3
valid_sources[0x7f]	54855	1			T41	1		T35	10		T37	4
valid_sources[0x80]	137446	1			T35	11		T37	6		T49	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9821354

1

T1

1

T2

4

T3

3

values[0x0]

all_enables

biggest_size

264112

1

T1

3

T2

2

T3

5

values[0x1]

all_enables

biggest_size

246811

1

T1

2

T2

2

T3

2