Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

9751300

1

T1

6

T2

6

T3

8

full_word

10333311

1

T1

6

T2

8

T3

10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	20084311	1			T1	12		T2	14		T3	18
auto[TlIntgErrCmd]	100	1			T216	3		T217	2		T241	1
auto[TlIntgErrData]	101	1			T216	5		T217	2		T241	5
auto[TlIntgErrBoth]	99	1			T216	2		T217	6		T241	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19432573

1

T1

3

T2

7

T3

7

auto[1]

652038

1

T1

9

T2

7

T3

11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9610905	1			T1	2		T2	3		T3	4
auto[TlIntgErrNone]	partial	auto[1]	140119	1			T1	4		T2	3		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	9821536	1			T1	1		T2	4		T3	3
auto[TlIntgErrNone]	full_word	auto[1]	511751	1			T1	5		T2	4		T3	7
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T216	1		T241	1		T256	2
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T216	2		T217	2		T256	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T405	1		T406	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T285	1		T407	1		T408	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T216	2		T217	2		T241	2
auto[TlIntgErrData]	partial	auto[1]	44	1			T216	2		T241	2		T256	4
auto[TlIntgErrData]	full_word	auto[0]	8	1			T216	1		T241	1		T405	2
auto[TlIntgErrData]	full_word	auto[1]	2	1			T407	1		T402	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T216	1		T217	4		T241	1
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T216	1		T217	2		T241	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T404	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T241	1		T256	1		T407	1