Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	570622455	12095	0	0
ep_in_enable_rd_A	570622455	1691	0	0
ep_out_enable_rd_A	570622455	1832	0	0
in_iso_rd_A	570622455	1810	0	0
intr_enable_rd_A	570622455	2466	0	0
out_iso_rd_A	570622455	2010	0	0
phy_config_rd_A	570622455	1288	0	0
phy_pins_drive_rd_A	570622455	1685	0	0
rxenable_setup_rd_A	570622455	1730	0	0
set_nak_out_rd_A	570622455	1982	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	570622455	12095	0	0
T216	13972	2	0	0
T217	12420	1	0	0
T218	6398	20	0	0
T235	6342	288	0	0
T236	3978	397	0	0
T241	20528	3	0	0
T242	5024	284	0	0
T245	11337	489	0	0
T247	8858	14	0	0
T256	39749	3	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	570622455	1691	0	0
T223	4140	6	0	0
T247	8858	59	0	0
T257	6834	51	0	0
T270	3638	7	0	0
T276	3798	51	0	0
T278	10577	69	0	0
T280	9908	29	0	0
T281	64178	130	0	0
T282	5918	9	0	0
T283	9936	94	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	570622455	1832	0	0
T247	8858	12	0	0
T257	6834	17	0	0
T270	3638	42	0	0
T276	3798	7	0	0
T278	10577	22	0	0
T280	9908	47	0	0
T281	64178	132	0	0
T282	5918	7	0	0
T283	9936	90	0	0
T284	20053	148	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	570622455	1810	0	0
T247	8858	119	0	0
T257	6834	1	0	0
T276	3798	2	0	0
T278	10577	67	0	0
T280	9908	45	0	0
T281	64178	125	0	0
T282	5918	23	0	0
T283	9936	95	0	0
T284	20053	183	0	0
T285	18753	226	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	570622455	2466	0	0
T221	3342	16	0	0
T223	4140	10	0	0
T225	2041	16	0	0
T246	16602	3	0	0
T247	8858	69	0	0
T270	3638	60	0	0
T278	10577	35	0	0
T280	9908	28	0	0
T281	64178	128	0	0
T286	2469	14	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	570622455	2010	0	0
T223	4140	3	0	0
T247	8858	70	0	0
T257	6834	59	0	0
T270	3638	2	0	0
T276	3798	41	0	0
T278	10577	42	0	0
T280	9908	37	0	0
T281	64178	150	0	0
T282	5918	47	0	0
T283	9936	89	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	570622455	1288	0	0
T247	8858	16	0	0
T257	6834	32	0	0
T270	3638	26	0	0
T276	3798	5	0	0
T278	10577	56	0	0
T280	9908	34	0	0
T281	64178	142	0	0
T282	5918	14	0	0
T283	9936	86	0	0
T284	20053	50	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	570622455	1685	0	0
T223	4140	7	0	0
T247	8858	35	0	0
T257	6834	7	0	0
T276	3798	44	0	0
T278	10577	14	0	0
T280	9908	32	0	0
T281	64178	146	0	0
T282	5918	14	0	0
T283	9936	138	0	0
T284	20053	126	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	570622455	1730	0	0
T247	8858	18	0	0
T257	6834	51	0	0
T270	3638	50	0	0
T276	3798	52	0	0
T278	10577	39	0	0
T280	9908	12	0	0
T281	64178	125	0	0
T282	5918	20	0	0
T283	9936	95	0	0
T284	20053	153	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	570622455	1982	0	0
T223	4140	3	0	0
T247	8858	79	0	0
T257	6834	10	0	0
T270	3638	49	0	0
T276	3798	48	0	0
T278	10577	72	0	0
T280	9908	29	0	0
T281	64178	192	0	0
T282	5918	27	0	0
T283	9936	99	0	0