Module Definition
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Module : usb_fs_nb_pe
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_pe.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe 100.00 100.00 100.00 100.00



Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.20 99.55 96.37 91.18 98.90 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 98.78 100.00 100.00 usbdev_impl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_usb_fs_nb_in_pe 96.14 98.32 95.61 90.91 95.83 100.00
u_usb_fs_nb_out_pe 95.47 99.21 92.54 87.50 98.08 100.00
u_usb_fs_rx 99.51 100.00 98.54 100.00
u_usb_fs_tx 98.30 100.00 98.15 93.33 100.00 100.00
u_usb_fs_tx_mux 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : usb_fs_nb_pe
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17611100.00

165 // - SOF is detected and may be used for timing/synchronization purposes if the PID is valid. 166 1/1 assign sof_detected_o = rx_pkt_end & rx_pid_valid & (usb_pid_e'(rx_pid) == UsbPidSof); Tests: T1 T2 T3  167 // - The SOF packet is considered valid iff the packet is also free of bit stuffing violations 168 // and the CRC5 is correct. 169 1/1 assign sof_valid_o = rx_pkt_end & rx_pkt_valid & (usb_pid_e'(rx_pid) == UsbPidSof); Tests: T1 T2 T3  170 // - The frame number shall be used only if the SOF packet is valid. 171 1/1 assign frame_index_o = rx_frame_num; Tests: T1 T2 T3  172 1/1 assign usb_oe_o = usb_oe; Tests: T1 T2 T3  173 174 // IN ep type configuration 175 logic [NumInEps-1:0] in_ep_iso_not_control; 176 1/1 assign in_ep_iso_not_control = in_ep_iso_i & ~out_ep_control_i; Tests: T1 T2 T3 

Cond Coverage for Module : usb_fs_nb_pe
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       166
 EXPRESSION (rx_pkt_end & rx_pid_valid & (usb_pid_e'(rx_pid) == UsbPidSof))
             -----1----   ------2-----   ----------------3----------------
-1--2--3-StatusTests
011CoveredT30,T31,T40
101CoveredT80,T81,T117
110CoveredT1,T2,T29
111CoveredT40,T49,T102

 LINE       166
 SUB-EXPRESSION (usb_pid_e'(rx_pid) == UsbPidSof)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T40

 LINE       169
 EXPRESSION (rx_pkt_end & rx_pkt_valid & (usb_pid_e'(rx_pid) == UsbPidSof))
             -----1----   ------2-----   ----------------3----------------
-1--2--3-StatusTests
011CoveredT40,T49,T102
101CoveredT80,T81,T117
110CoveredT1,T2,T29
111CoveredT40,T49,T102

 LINE       169
 SUB-EXPRESSION (usb_pid_e'(rx_pid) == UsbPidSof)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31,T40

Assert Coverage for Module : usb_fs_nb_pe
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumOutEpsEqualsNumInEps_A 3730 3730 0 0
ParamMaxPktSizeByteValid 3730 3730 0 0
ParamNumEpsOutAndInEqual 3730 3730 0 0
ParamNumInEpsValid 3730 3730 0 0
ParamNumOutEpsValid 3730 3730 0 0


NumOutEpsEqualsNumInEps_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3730 3730 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T39 1 1 0 0
T40 1 1 0 0
T41 1 1 0 0
T42 1 1 0 0

ParamMaxPktSizeByteValid
NameAttemptsReal SuccessesFailuresIncomplete
Total 3730 3730 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T39 1 1 0 0
T40 1 1 0 0
T41 1 1 0 0
T42 1 1 0 0

ParamNumEpsOutAndInEqual
NameAttemptsReal SuccessesFailuresIncomplete
Total 3730 3730 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T39 1 1 0 0
T40 1 1 0 0
T41 1 1 0 0
T42 1 1 0 0

ParamNumInEpsValid
NameAttemptsReal SuccessesFailuresIncomplete
Total 3730 3730 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T39 1 1 0 0
T40 1 1 0 0
T41 1 1 0 0
T42 1 1 0 0

ParamNumOutEpsValid
NameAttemptsReal SuccessesFailuresIncomplete
Total 3730 3730 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T39 1 1 0 0
T40 1 1 0 0
T41 1 1 0 0
T42 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%