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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.64 98.22 96.10 97.44 96.61 98.38 98.17 98.55


Total test records in report: 3830
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T3573 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/342.usbdev_tx_rx_disruption.118068410 Sep 11 08:37:27 AM UTC 24 Sep 11 08:37:30 AM UTC 24 503764707 ps
T3574 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/344.usbdev_tx_rx_disruption.2021947720 Sep 11 08:37:27 AM UTC 24 Sep 11 08:37:31 AM UTC 24 545068994 ps
T3575 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/341.usbdev_tx_rx_disruption.1198028883 Sep 11 08:37:27 AM UTC 24 Sep 11 08:37:31 AM UTC 24 484618947 ps
T3576 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/345.usbdev_tx_rx_disruption.3895179510 Sep 11 08:37:27 AM UTC 24 Sep 11 08:37:31 AM UTC 24 534983602 ps
T3577 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/295.usbdev_tx_rx_disruption.1958694174 Sep 11 08:37:15 AM UTC 24 Sep 11 08:37:31 AM UTC 24 488502475 ps
T3578 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/317.usbdev_tx_rx_disruption.687064545 Sep 11 08:37:17 AM UTC 24 Sep 11 08:37:31 AM UTC 24 576342592 ps
T3579 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/297.usbdev_tx_rx_disruption.3327653236 Sep 11 08:37:15 AM UTC 24 Sep 11 08:37:31 AM UTC 24 576462245 ps
T3580 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/296.usbdev_tx_rx_disruption.482219883 Sep 11 08:37:15 AM UTC 24 Sep 11 08:37:31 AM UTC 24 555013045 ps
T3581 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/320.usbdev_tx_rx_disruption.90094317 Sep 11 08:37:18 AM UTC 24 Sep 11 08:37:31 AM UTC 24 626461178 ps
T3582 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/299.usbdev_tx_rx_disruption.1591254106 Sep 11 08:37:15 AM UTC 24 Sep 11 08:37:31 AM UTC 24 558300419 ps
T3583 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/300.usbdev_tx_rx_disruption.3427937985 Sep 11 08:37:15 AM UTC 24 Sep 11 08:37:31 AM UTC 24 504186806 ps
T3584 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/343.usbdev_tx_rx_disruption.821306075 Sep 11 08:37:27 AM UTC 24 Sep 11 08:37:31 AM UTC 24 682456600 ps
T3585 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/301.usbdev_tx_rx_disruption.1564537821 Sep 11 08:37:15 AM UTC 24 Sep 11 08:37:31 AM UTC 24 595141864 ps
T3586 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/298.usbdev_tx_rx_disruption.1981193418 Sep 11 08:37:15 AM UTC 24 Sep 11 08:37:31 AM UTC 24 513457559 ps
T3587 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/307.usbdev_tx_rx_disruption.1609484433 Sep 11 08:37:15 AM UTC 24 Sep 11 08:37:31 AM UTC 24 593130700 ps
T3588 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/302.usbdev_tx_rx_disruption.3958019424 Sep 11 08:37:15 AM UTC 24 Sep 11 08:37:31 AM UTC 24 542525546 ps
T3589 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/303.usbdev_tx_rx_disruption.2035598304 Sep 11 08:37:15 AM UTC 24 Sep 11 08:37:31 AM UTC 24 477137762 ps
T3590 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/304.usbdev_tx_rx_disruption.949436812 Sep 11 08:37:15 AM UTC 24 Sep 11 08:37:31 AM UTC 24 611170771 ps
T3591 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/305.usbdev_tx_rx_disruption.1974814204 Sep 11 08:37:15 AM UTC 24 Sep 11 08:37:31 AM UTC 24 637044614 ps
T3592 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/350.usbdev_tx_rx_disruption.1503655190 Sep 11 08:37:31 AM UTC 24 Sep 11 08:37:35 AM UTC 24 436337064 ps
T3593 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/351.usbdev_tx_rx_disruption.338845907 Sep 11 08:37:32 AM UTC 24 Sep 11 08:37:35 AM UTC 24 483809164 ps
T3594 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/348.usbdev_tx_rx_disruption.2143580824 Sep 11 08:37:31 AM UTC 24 Sep 11 08:37:35 AM UTC 24 566419649 ps
T3595 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/352.usbdev_tx_rx_disruption.3558832839 Sep 11 08:37:32 AM UTC 24 Sep 11 08:37:35 AM UTC 24 457349034 ps
T3596 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/353.usbdev_tx_rx_disruption.1593533483 Sep 11 08:37:32 AM UTC 24 Sep 11 08:37:35 AM UTC 24 482826964 ps
T3597 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/349.usbdev_tx_rx_disruption.2511124045 Sep 11 08:37:31 AM UTC 24 Sep 11 08:37:35 AM UTC 24 610312892 ps
T3598 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/355.usbdev_tx_rx_disruption.2231811481 Sep 11 08:37:32 AM UTC 24 Sep 11 08:37:35 AM UTC 24 509177477 ps
T3599 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/347.usbdev_tx_rx_disruption.318121047 Sep 11 08:37:31 AM UTC 24 Sep 11 08:37:35 AM UTC 24 680236155 ps
T3600 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/356.usbdev_tx_rx_disruption.3723444431 Sep 11 08:37:32 AM UTC 24 Sep 11 08:37:35 AM UTC 24 569125880 ps
T3601 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/354.usbdev_tx_rx_disruption.2040661296 Sep 11 08:37:32 AM UTC 24 Sep 11 08:37:35 AM UTC 24 659471044 ps
T3602 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/358.usbdev_tx_rx_disruption.813706539 Sep 11 08:37:32 AM UTC 24 Sep 11 08:37:35 AM UTC 24 571311473 ps
T3603 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/359.usbdev_tx_rx_disruption.4182403887 Sep 11 08:37:32 AM UTC 24 Sep 11 08:37:35 AM UTC 24 581564562 ps
T3604 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/357.usbdev_tx_rx_disruption.3501522438 Sep 11 08:37:32 AM UTC 24 Sep 11 08:37:35 AM UTC 24 530976993 ps
T3605 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/360.usbdev_tx_rx_disruption.3911693777 Sep 11 08:37:32 AM UTC 24 Sep 11 08:37:35 AM UTC 24 451353797 ps
T3606 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/361.usbdev_tx_rx_disruption.4024347173 Sep 11 08:37:32 AM UTC 24 Sep 11 08:37:36 AM UTC 24 561466811 ps
T3607 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/362.usbdev_tx_rx_disruption.1907813611 Sep 11 08:37:32 AM UTC 24 Sep 11 08:37:36 AM UTC 24 514628148 ps
T3608 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/377.usbdev_tx_rx_disruption.3314372923 Sep 11 08:37:36 AM UTC 24 Sep 11 08:37:40 AM UTC 24 501960772 ps
T3609 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/378.usbdev_tx_rx_disruption.2178803915 Sep 11 08:37:37 AM UTC 24 Sep 11 08:37:40 AM UTC 24 466979548 ps
T3610 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/380.usbdev_tx_rx_disruption.2054523484 Sep 11 08:37:37 AM UTC 24 Sep 11 08:37:40 AM UTC 24 563891550 ps
T3611 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/379.usbdev_tx_rx_disruption.729236539 Sep 11 08:37:37 AM UTC 24 Sep 11 08:37:40 AM UTC 24 504683478 ps
T3612 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/386.usbdev_tx_rx_disruption.1773398293 Sep 11 08:37:37 AM UTC 24 Sep 11 08:37:40 AM UTC 24 490038138 ps
T3613 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/382.usbdev_tx_rx_disruption.1534237581 Sep 11 08:37:37 AM UTC 24 Sep 11 08:37:40 AM UTC 24 552335075 ps
T3614 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/385.usbdev_tx_rx_disruption.3860880163 Sep 11 08:37:37 AM UTC 24 Sep 11 08:37:40 AM UTC 24 472394005 ps
T3615 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/387.usbdev_tx_rx_disruption.340425194 Sep 11 08:37:37 AM UTC 24 Sep 11 08:37:40 AM UTC 24 547457118 ps
T3616 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/383.usbdev_tx_rx_disruption.2220910882 Sep 11 08:37:37 AM UTC 24 Sep 11 08:37:40 AM UTC 24 458786035 ps
T3617 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/381.usbdev_tx_rx_disruption.1608938643 Sep 11 08:37:37 AM UTC 24 Sep 11 08:37:40 AM UTC 24 594502488 ps
T3618 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/390.usbdev_tx_rx_disruption.3077368896 Sep 11 08:37:37 AM UTC 24 Sep 11 08:37:40 AM UTC 24 514114255 ps
T3619 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/388.usbdev_tx_rx_disruption.88188759 Sep 11 08:37:37 AM UTC 24 Sep 11 08:37:40 AM UTC 24 587758481 ps
T3620 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/384.usbdev_tx_rx_disruption.70164100 Sep 11 08:37:37 AM UTC 24 Sep 11 08:37:40 AM UTC 24 668616082 ps
T3621 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/392.usbdev_tx_rx_disruption.2753715077 Sep 11 08:37:37 AM UTC 24 Sep 11 08:37:40 AM UTC 24 516312940 ps
T3622 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/389.usbdev_tx_rx_disruption.1700229829 Sep 11 08:37:37 AM UTC 24 Sep 11 08:37:40 AM UTC 24 566926848 ps
T3623 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/391.usbdev_tx_rx_disruption.3388932786 Sep 11 08:37:37 AM UTC 24 Sep 11 08:37:41 AM UTC 24 675823551 ps
T3624 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/394.usbdev_tx_rx_disruption.3815185525 Sep 11 08:37:40 AM UTC 24 Sep 11 08:37:42 AM UTC 24 429960486 ps
T3625 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/393.usbdev_tx_rx_disruption.4117033059 Sep 11 08:37:40 AM UTC 24 Sep 11 08:37:43 AM UTC 24 426316748 ps
T3626 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/395.usbdev_tx_rx_disruption.1402284114 Sep 11 08:37:40 AM UTC 24 Sep 11 08:37:43 AM UTC 24 531176018 ps
T3627 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/290.usbdev_tx_rx_disruption.862224844 Sep 11 08:37:13 AM UTC 24 Sep 11 08:37:43 AM UTC 24 502048388 ps
T3628 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/291.usbdev_tx_rx_disruption.1138213244 Sep 11 08:37:13 AM UTC 24 Sep 11 08:37:43 AM UTC 24 633821974 ps
T3629 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/264.usbdev_tx_rx_disruption.2902693895 Sep 11 08:37:10 AM UTC 24 Sep 11 08:37:43 AM UTC 24 542684642 ps
T3630 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/292.usbdev_tx_rx_disruption.1096943471 Sep 11 08:37:13 AM UTC 24 Sep 11 08:37:43 AM UTC 24 561644931 ps
T3631 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/329.usbdev_tx_rx_disruption.588299613 Sep 11 08:37:26 AM UTC 24 Sep 11 08:37:43 AM UTC 24 476377515 ps
T3632 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/321.usbdev_tx_rx_disruption.1184883735 Sep 11 08:37:20 AM UTC 24 Sep 11 08:37:43 AM UTC 24 560462732 ps
T3633 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/294.usbdev_tx_rx_disruption.3027814299 Sep 11 08:37:13 AM UTC 24 Sep 11 08:37:43 AM UTC 24 576030349 ps
T3634 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/293.usbdev_tx_rx_disruption.2366452170 Sep 11 08:37:13 AM UTC 24 Sep 11 08:37:43 AM UTC 24 501969876 ps
T3635 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/407.usbdev_tx_rx_disruption.3625760641 Sep 11 08:37:42 AM UTC 24 Sep 11 08:37:45 AM UTC 24 628480202 ps
T3636 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/330.usbdev_tx_rx_disruption.3256552052 Sep 11 08:37:26 AM UTC 24 Sep 11 08:37:43 AM UTC 24 499251057 ps
T3637 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/409.usbdev_tx_rx_disruption.2026203941 Sep 11 08:37:42 AM UTC 24 Sep 11 08:37:45 AM UTC 24 519227771 ps
T3638 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/414.usbdev_tx_rx_disruption.3575994143 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:47 AM UTC 24 509648350 ps
T3639 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/363.usbdev_tx_rx_disruption.3775647916 Sep 11 08:37:33 AM UTC 24 Sep 11 08:37:43 AM UTC 24 591388688 ps
T3640 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/374.usbdev_tx_rx_disruption.2660598101 Sep 11 08:37:34 AM UTC 24 Sep 11 08:37:43 AM UTC 24 445543458 ps
T3641 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/364.usbdev_tx_rx_disruption.3146787895 Sep 11 08:37:33 AM UTC 24 Sep 11 08:37:43 AM UTC 24 466978645 ps
T3642 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/370.usbdev_tx_rx_disruption.2255406193 Sep 11 08:37:34 AM UTC 24 Sep 11 08:37:43 AM UTC 24 597637973 ps
T3643 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/416.usbdev_tx_rx_disruption.2370561664 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:47 AM UTC 24 479197727 ps
T3644 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/375.usbdev_tx_rx_disruption.929305210 Sep 11 08:37:34 AM UTC 24 Sep 11 08:37:43 AM UTC 24 495229824 ps
T3645 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/376.usbdev_tx_rx_disruption.1242244697 Sep 11 08:37:34 AM UTC 24 Sep 11 08:37:43 AM UTC 24 475902543 ps
T3646 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/373.usbdev_tx_rx_disruption.1446506494 Sep 11 08:37:34 AM UTC 24 Sep 11 08:37:43 AM UTC 24 441470685 ps
T3647 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/368.usbdev_tx_rx_disruption.2244373446 Sep 11 08:37:34 AM UTC 24 Sep 11 08:37:43 AM UTC 24 482479755 ps
T3648 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/365.usbdev_tx_rx_disruption.3063905571 Sep 11 08:37:33 AM UTC 24 Sep 11 08:37:43 AM UTC 24 555989104 ps
T3649 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/366.usbdev_tx_rx_disruption.3613481145 Sep 11 08:37:34 AM UTC 24 Sep 11 08:37:44 AM UTC 24 583366887 ps
T3650 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/371.usbdev_tx_rx_disruption.554011129 Sep 11 08:37:34 AM UTC 24 Sep 11 08:37:44 AM UTC 24 654321518 ps
T3651 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/367.usbdev_tx_rx_disruption.2657194042 Sep 11 08:37:34 AM UTC 24 Sep 11 08:37:44 AM UTC 24 597170171 ps
T3652 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/369.usbdev_tx_rx_disruption.2255453144 Sep 11 08:37:34 AM UTC 24 Sep 11 08:37:44 AM UTC 24 693738295 ps
T3653 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/372.usbdev_tx_rx_disruption.1866459209 Sep 11 08:37:34 AM UTC 24 Sep 11 08:37:44 AM UTC 24 704744468 ps
T3654 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/402.usbdev_tx_rx_disruption.4032926251 Sep 11 08:37:42 AM UTC 24 Sep 11 08:37:44 AM UTC 24 510038860 ps
T3655 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/400.usbdev_tx_rx_disruption.3167089970 Sep 11 08:37:42 AM UTC 24 Sep 11 08:37:44 AM UTC 24 486069031 ps
T3656 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/396.usbdev_tx_rx_disruption.1004425533 Sep 11 08:37:42 AM UTC 24 Sep 11 08:37:44 AM UTC 24 574236921 ps
T3657 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/401.usbdev_tx_rx_disruption.2817334973 Sep 11 08:37:42 AM UTC 24 Sep 11 08:37:44 AM UTC 24 602617304 ps
T3658 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/398.usbdev_tx_rx_disruption.212169336 Sep 11 08:37:42 AM UTC 24 Sep 11 08:37:44 AM UTC 24 540542156 ps
T3659 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/397.usbdev_tx_rx_disruption.2562478098 Sep 11 08:37:42 AM UTC 24 Sep 11 08:37:44 AM UTC 24 606284174 ps
T3660 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/410.usbdev_tx_rx_disruption.1360151209 Sep 11 08:37:42 AM UTC 24 Sep 11 08:37:45 AM UTC 24 458282644 ps
T3661 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/404.usbdev_tx_rx_disruption.3332255744 Sep 11 08:37:42 AM UTC 24 Sep 11 08:37:45 AM UTC 24 503740632 ps
T3662 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/399.usbdev_tx_rx_disruption.3387122785 Sep 11 08:37:42 AM UTC 24 Sep 11 08:37:45 AM UTC 24 630148864 ps
T3663 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/411.usbdev_tx_rx_disruption.19423457 Sep 11 08:37:42 AM UTC 24 Sep 11 08:37:45 AM UTC 24 468707738 ps
T3664 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/403.usbdev_tx_rx_disruption.504490076 Sep 11 08:37:42 AM UTC 24 Sep 11 08:37:45 AM UTC 24 628061248 ps
T3665 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/405.usbdev_tx_rx_disruption.3564364408 Sep 11 08:37:42 AM UTC 24 Sep 11 08:37:45 AM UTC 24 628617321 ps
T3666 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/408.usbdev_tx_rx_disruption.3515362949 Sep 11 08:37:42 AM UTC 24 Sep 11 08:37:45 AM UTC 24 606391538 ps
T3667 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/406.usbdev_tx_rx_disruption.1192418736 Sep 11 08:37:42 AM UTC 24 Sep 11 08:37:45 AM UTC 24 684082859 ps
T3668 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/412.usbdev_tx_rx_disruption.171113495 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:47 AM UTC 24 593332461 ps
T3669 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/415.usbdev_tx_rx_disruption.3607000832 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:47 AM UTC 24 515396499 ps
T3670 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/413.usbdev_tx_rx_disruption.3968389292 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:47 AM UTC 24 576674310 ps
T3671 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/421.usbdev_tx_rx_disruption.405016165 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:47 AM UTC 24 451250263 ps
T3672 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/418.usbdev_tx_rx_disruption.3139496889 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:47 AM UTC 24 571277230 ps
T3673 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/422.usbdev_tx_rx_disruption.3548436482 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:47 AM UTC 24 560672500 ps
T3674 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/420.usbdev_tx_rx_disruption.3647225519 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:47 AM UTC 24 503843151 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/417.usbdev_tx_rx_disruption.3691999277 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:48 AM UTC 24 540214527 ps
T3675 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/419.usbdev_tx_rx_disruption.4046407120 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:48 AM UTC 24 603675571 ps
T3676 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/424.usbdev_tx_rx_disruption.1384292762 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:48 AM UTC 24 563088737 ps
T3677 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/432.usbdev_tx_rx_disruption.1371501302 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:48 AM UTC 24 462890993 ps
T3678 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/423.usbdev_tx_rx_disruption.189702882 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:48 AM UTC 24 589871507 ps
T3679 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/429.usbdev_tx_rx_disruption.2802739657 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:48 AM UTC 24 458371339 ps
T3680 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/425.usbdev_tx_rx_disruption.2430367320 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:48 AM UTC 24 649181642 ps
T3681 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/427.usbdev_tx_rx_disruption.3033516701 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:48 AM UTC 24 468935424 ps
T3682 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/428.usbdev_tx_rx_disruption.779824730 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:48 AM UTC 24 635176955 ps
T3683 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/431.usbdev_tx_rx_disruption.2082648655 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:48 AM UTC 24 550215218 ps
T3684 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/426.usbdev_tx_rx_disruption.320312964 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:48 AM UTC 24 581517523 ps
T3685 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/453.usbdev_tx_rx_disruption.2651011579 Sep 11 08:37:47 AM UTC 24 Sep 11 08:37:50 AM UTC 24 468877085 ps
T3686 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/455.usbdev_tx_rx_disruption.1307030636 Sep 11 08:37:47 AM UTC 24 Sep 11 08:37:50 AM UTC 24 466133502 ps
T3687 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/452.usbdev_tx_rx_disruption.1451607021 Sep 11 08:37:47 AM UTC 24 Sep 11 08:37:50 AM UTC 24 512099674 ps
T3688 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/456.usbdev_tx_rx_disruption.1105701663 Sep 11 08:37:47 AM UTC 24 Sep 11 08:37:50 AM UTC 24 522047460 ps
T3689 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/451.usbdev_tx_rx_disruption.954077117 Sep 11 08:37:47 AM UTC 24 Sep 11 08:37:50 AM UTC 24 518416472 ps
T3690 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/458.usbdev_tx_rx_disruption.693166617 Sep 11 08:37:48 AM UTC 24 Sep 11 08:37:50 AM UTC 24 507579483 ps
T3691 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/460.usbdev_tx_rx_disruption.3242020659 Sep 11 08:37:48 AM UTC 24 Sep 11 08:37:50 AM UTC 24 554797142 ps
T3692 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/454.usbdev_tx_rx_disruption.3813007246 Sep 11 08:37:47 AM UTC 24 Sep 11 08:37:50 AM UTC 24 611199480 ps
T3693 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/457.usbdev_tx_rx_disruption.2036091060 Sep 11 08:37:47 AM UTC 24 Sep 11 08:37:50 AM UTC 24 500560085 ps
T3694 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/464.usbdev_tx_rx_disruption.3238943370 Sep 11 08:37:48 AM UTC 24 Sep 11 08:37:50 AM UTC 24 470694727 ps
T3695 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/461.usbdev_tx_rx_disruption.3081061645 Sep 11 08:37:48 AM UTC 24 Sep 11 08:37:50 AM UTC 24 534416960 ps
T3696 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/459.usbdev_tx_rx_disruption.95126581 Sep 11 08:37:48 AM UTC 24 Sep 11 08:37:50 AM UTC 24 560465192 ps
T3697 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/462.usbdev_tx_rx_disruption.129851484 Sep 11 08:37:48 AM UTC 24 Sep 11 08:37:50 AM UTC 24 502971078 ps
T3698 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/463.usbdev_tx_rx_disruption.3113408822 Sep 11 08:37:48 AM UTC 24 Sep 11 08:37:50 AM UTC 24 639940285 ps
T3699 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/465.usbdev_tx_rx_disruption.1298235080 Sep 11 08:37:48 AM UTC 24 Sep 11 08:37:51 AM UTC 24 674063752 ps
T3700 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/434.usbdev_tx_rx_disruption.1229366268 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:51 AM UTC 24 501248410 ps
T3701 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/430.usbdev_tx_rx_disruption.401820411 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:51 AM UTC 24 479024739 ps
T3702 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/433.usbdev_tx_rx_disruption.1662993791 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:51 AM UTC 24 491346917 ps
T3703 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/435.usbdev_tx_rx_disruption.2692056002 Sep 11 08:37:45 AM UTC 24 Sep 11 08:37:51 AM UTC 24 604448098 ps
T3704 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/449.usbdev_tx_rx_disruption.3758534701 Sep 11 08:37:46 AM UTC 24 Sep 11 08:37:55 AM UTC 24 621440796 ps
T3705 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/447.usbdev_tx_rx_disruption.2665924601 Sep 11 08:37:46 AM UTC 24 Sep 11 08:37:59 AM UTC 24 621122883 ps
T3706 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/438.usbdev_tx_rx_disruption.2752302356 Sep 11 08:37:45 AM UTC 24 Sep 11 08:38:01 AM UTC 24 462803380 ps
T3707 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/437.usbdev_tx_rx_disruption.2566124318 Sep 11 08:37:45 AM UTC 24 Sep 11 08:38:01 AM UTC 24 538518672 ps
T3708 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/436.usbdev_tx_rx_disruption.4145669366 Sep 11 08:37:45 AM UTC 24 Sep 11 08:38:01 AM UTC 24 524140155 ps
T3709 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/441.usbdev_tx_rx_disruption.385017005 Sep 11 08:37:45 AM UTC 24 Sep 11 08:38:01 AM UTC 24 490657804 ps
T3710 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/444.usbdev_tx_rx_disruption.2431121052 Sep 11 08:37:46 AM UTC 24 Sep 11 08:38:01 AM UTC 24 486486563 ps
T3711 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/440.usbdev_tx_rx_disruption.3419065046 Sep 11 08:37:45 AM UTC 24 Sep 11 08:38:01 AM UTC 24 555365239 ps
T3712 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/439.usbdev_tx_rx_disruption.2350138505 Sep 11 08:37:45 AM UTC 24 Sep 11 08:38:01 AM UTC 24 576222634 ps
T3713 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/442.usbdev_tx_rx_disruption.2832250179 Sep 11 08:37:45 AM UTC 24 Sep 11 08:38:01 AM UTC 24 516233399 ps
T3714 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/492.usbdev_tx_rx_disruption.3025194658 Sep 11 08:37:52 AM UTC 24 Sep 11 08:38:01 AM UTC 24 507892018 ps
T3715 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/445.usbdev_tx_rx_disruption.75676741 Sep 11 08:37:46 AM UTC 24 Sep 11 08:38:01 AM UTC 24 487948034 ps
T3716 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/446.usbdev_tx_rx_disruption.3664078578 Sep 11 08:37:46 AM UTC 24 Sep 11 08:38:01 AM UTC 24 519897919 ps
T3717 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/448.usbdev_tx_rx_disruption.676706877 Sep 11 08:37:46 AM UTC 24 Sep 11 08:38:01 AM UTC 24 573273495 ps
T3718 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/490.usbdev_tx_rx_disruption.3283361622 Sep 11 08:37:52 AM UTC 24 Sep 11 08:38:02 AM UTC 24 520113353 ps
T3719 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/443.usbdev_tx_rx_disruption.4147732887 Sep 11 08:37:46 AM UTC 24 Sep 11 08:38:02 AM UTC 24 605412003 ps
T3720 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/495.usbdev_tx_rx_disruption.4075773412 Sep 11 08:37:52 AM UTC 24 Sep 11 08:38:02 AM UTC 24 525147863 ps
T3721 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/496.usbdev_tx_rx_disruption.1757040494 Sep 11 08:37:52 AM UTC 24 Sep 11 08:38:02 AM UTC 24 513261013 ps
T3722 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/494.usbdev_tx_rx_disruption.3162021294 Sep 11 08:37:52 AM UTC 24 Sep 11 08:38:02 AM UTC 24 612758045 ps
T3723 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/493.usbdev_tx_rx_disruption.3470860846 Sep 11 08:37:52 AM UTC 24 Sep 11 08:38:02 AM UTC 24 622445284 ps
T3724 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/499.usbdev_tx_rx_disruption.1584180852 Sep 11 08:37:52 AM UTC 24 Sep 11 08:38:05 AM UTC 24 516197325 ps
T3725 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/498.usbdev_tx_rx_disruption.2568486682 Sep 11 08:37:52 AM UTC 24 Sep 11 08:38:05 AM UTC 24 505991125 ps
T3726 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/497.usbdev_tx_rx_disruption.126233369 Sep 11 08:37:52 AM UTC 24 Sep 11 08:38:05 AM UTC 24 565424895 ps
T3727 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/480.usbdev_tx_rx_disruption.2466325421 Sep 11 08:37:50 AM UTC 24 Sep 11 08:38:16 AM UTC 24 506815794 ps
T3728 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/475.usbdev_tx_rx_disruption.1135342758 Sep 11 08:37:50 AM UTC 24 Sep 11 08:38:16 AM UTC 24 575763068 ps
T3729 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/478.usbdev_tx_rx_disruption.845568205 Sep 11 08:37:50 AM UTC 24 Sep 11 08:38:16 AM UTC 24 535016457 ps
T3730 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/481.usbdev_tx_rx_disruption.2130195074 Sep 11 08:37:50 AM UTC 24 Sep 11 08:38:16 AM UTC 24 636570101 ps
T3731 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/479.usbdev_tx_rx_disruption.2147830187 Sep 11 08:37:50 AM UTC 24 Sep 11 08:38:16 AM UTC 24 627015450 ps
T3732 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/483.usbdev_tx_rx_disruption.1294560002 Sep 11 08:37:50 AM UTC 24 Sep 11 08:38:16 AM UTC 24 638925227 ps
T3733 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/477.usbdev_tx_rx_disruption.989534418 Sep 11 08:37:50 AM UTC 24 Sep 11 08:38:16 AM UTC 24 533711750 ps
T3734 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/484.usbdev_tx_rx_disruption.705897659 Sep 11 08:37:50 AM UTC 24 Sep 11 08:38:16 AM UTC 24 562265720 ps
T3735 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/482.usbdev_tx_rx_disruption.1294087811 Sep 11 08:37:50 AM UTC 24 Sep 11 08:38:16 AM UTC 24 669162598 ps
T3736 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/default/485.usbdev_tx_rx_disruption.2873097727 Sep 11 08:37:50 AM UTC 24 Sep 11 08:38:16 AM UTC 24 631006918 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1720082310 Sep 11 08:37:55 AM UTC 24 Sep 11 08:38:00 AM UTC 24 76960645 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_intr_test.1818575311 Sep 11 08:38:02 AM UTC 24 Sep 11 08:38:04 AM UTC 24 40505613 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3797360612 Sep 11 08:38:02 AM UTC 24 Sep 11 08:38:04 AM UTC 24 180245050 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3184401902 Sep 11 08:38:02 AM UTC 24 Sep 11 08:38:05 AM UTC 24 99293068 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.727639798 Sep 11 08:38:02 AM UTC 24 Sep 11 08:38:05 AM UTC 24 134361468 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_errors.4196250727 Sep 11 08:38:02 AM UTC 24 Sep 11 08:38:06 AM UTC 24 244632332 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_intg_err.1802731839 Sep 11 08:38:02 AM UTC 24 Sep 11 08:38:06 AM UTC 24 622931775 ps
T3737 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_rw.1982690525 Sep 11 08:38:00 AM UTC 24 Sep 11 08:38:09 AM UTC 24 53327581 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_rw.676054589 Sep 11 08:38:05 AM UTC 24 Sep 11 08:38:10 AM UTC 24 65766815 ps
T3738 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3934764638 Sep 11 08:38:05 AM UTC 24 Sep 11 08:38:10 AM UTC 24 92862056 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_errors.3882486139 Sep 11 08:38:07 AM UTC 24 Sep 11 08:38:10 AM UTC 24 153678231 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_partial_access.2193237437 Sep 11 08:38:05 AM UTC 24 Sep 11 08:38:10 AM UTC 24 129919275 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_intg_err.1751427294 Sep 11 08:38:07 AM UTC 24 Sep 11 08:38:11 AM UTC 24 733005139 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_aliasing.3694263685 Sep 11 08:38:06 AM UTC 24 Sep 11 08:38:12 AM UTC 24 212035668 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1049179921 Sep 11 08:38:06 AM UTC 24 Sep 11 08:38:14 AM UTC 24 649320756 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_intr_test.1985077136 Sep 11 08:37:52 AM UTC 24 Sep 11 08:38:14 AM UTC 24 61619496 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_rw.1958699883 Sep 11 08:38:03 AM UTC 24 Sep 11 08:38:14 AM UTC 24 63489608 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_intr_test.1689509230 Sep 11 08:38:03 AM UTC 24 Sep 11 08:38:14 AM UTC 24 45170658 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_rw.859367743 Sep 11 08:38:12 AM UTC 24 Sep 11 08:38:15 AM UTC 24 44338338 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4097103165 Sep 11 08:38:03 AM UTC 24 Sep 11 08:38:15 AM UTC 24 72773484 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2292326691 Sep 11 08:38:06 AM UTC 24 Sep 11 08:38:15 AM UTC 24 121956537 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.253973318 Sep 11 08:38:03 AM UTC 24 Sep 11 08:38:15 AM UTC 24 81082822 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_aliasing.210663493 Sep 11 08:38:02 AM UTC 24 Sep 11 08:38:15 AM UTC 24 116624454 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_errors.629852507 Sep 11 08:38:03 AM UTC 24 Sep 11 08:38:15 AM UTC 24 161271085 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1010098002 Sep 11 08:38:06 AM UTC 24 Sep 11 08:38:16 AM UTC 24 122250350 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_aliasing.2006738948 Sep 11 08:38:03 AM UTC 24 Sep 11 08:38:16 AM UTC 24 198412307 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_intr_test.1581206149 Sep 11 08:38:11 AM UTC 24 Sep 11 08:38:16 AM UTC 24 73308745 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_aliasing.4263945647 Sep 11 08:38:13 AM UTC 24 Sep 11 08:38:16 AM UTC 24 173841803 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1105955556 Sep 11 08:38:11 AM UTC 24 Sep 11 08:38:16 AM UTC 24 146831244 ps
T3739 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_walk.1064674644 Sep 11 08:37:52 AM UTC 24 Sep 11 08:38:16 AM UTC 24 258086110 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_partial_access.2962678294 Sep 11 08:38:11 AM UTC 24 Sep 11 08:38:16 AM UTC 24 66105160 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_partial_access.155661737 Sep 11 08:38:02 AM UTC 24 Sep 11 08:38:16 AM UTC 24 171002401 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_errors.463704942 Sep 11 08:37:52 AM UTC 24 Sep 11 08:38:16 AM UTC 24 97319051 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_partial_access.61999198 Sep 11 08:37:53 AM UTC 24 Sep 11 08:38:16 AM UTC 24 184308243 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_intg_err.3884121192 Sep 11 08:38:03 AM UTC 24 Sep 11 08:38:17 AM UTC 24 694590814 ps
T3740 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_walk.4088068472 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:21 AM UTC 24 475807570 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3071769600 Sep 11 08:38:18 AM UTC 24 Sep 11 08:38:21 AM UTC 24 99775799 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_bit_bash.4255659914 Sep 11 08:38:02 AM UTC 24 Sep 11 08:38:17 AM UTC 24 294275049 ps
T3741 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_walk.1020937015 Sep 11 08:38:04 AM UTC 24 Sep 11 08:38:17 AM UTC 24 292622909 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_tl_errors.3968545434 Sep 11 08:38:18 AM UTC 24 Sep 11 08:38:21 AM UTC 24 131799178 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_intr_test.839674160 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:17 AM UTC 24 31466165 ps
T3742 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1034692001 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:18 AM UTC 24 68427020 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3606941604 Sep 11 08:38:12 AM UTC 24 Sep 11 08:38:18 AM UTC 24 503313597 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_intr_test.4017205296 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:18 AM UTC 24 75959167 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_rw.1514515426 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:18 AM UTC 24 58552727 ps
T561 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_intg_err.3600610405 Sep 11 08:37:52 AM UTC 24 Sep 11 08:38:18 AM UTC 24 796891939 ps
T3743 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_walk.2754370395 Sep 11 08:38:02 AM UTC 24 Sep 11 08:38:18 AM UTC 24 711375572 ps
T3744 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_partial_access.544662463 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:18 AM UTC 24 73151240 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_rw.3205771368 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:18 AM UTC 24 124086764 ps
T3745 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.4087781703 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:18 AM UTC 24 121151179 ps
T3746 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1274909587 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:18 AM UTC 24 214673186 ps
T3747 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2360439673 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:19 AM UTC 24 80072433 ps
T3748 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_csr_rw.965026732 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:19 AM UTC 24 42630948 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_intr_test.207095779 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:19 AM UTC 24 82972322 ps
T3749 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2995640022 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:19 AM UTC 24 117016124 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_aliasing.2421337851 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:19 AM UTC 24 161006882 ps
T3750 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.413357474 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:19 AM UTC 24 97760531 ps
T3751 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_walk.34930037 Sep 11 08:38:11 AM UTC 24 Sep 11 08:38:19 AM UTC 24 713069514 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_tl_errors.893389091 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:19 AM UTC 24 144151253 ps
T3752 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2594764387 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:19 AM UTC 24 88048121 ps
T557 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_intg_err.3032218873 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:19 AM UTC 24 424959396 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_errors.3748288712 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:20 AM UTC 24 138360776 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2747527022 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:20 AM UTC 24 224783084 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_intr_test.3649234734 Sep 11 08:38:18 AM UTC 24 Sep 11 08:38:20 AM UTC 24 75400226 ps
T3753 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3641029138 Sep 11 08:38:18 AM UTC 24 Sep 11 08:38:20 AM UTC 24 62747247 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_csr_rw.4042488413 Sep 11 08:38:18 AM UTC 24 Sep 11 08:38:20 AM UTC 24 88297451 ps
T3754 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_bit_bash.648953001 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:21 AM UTC 24 529846909 ps
T3755 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2153127458 Sep 11 08:38:03 AM UTC 24 Sep 11 08:38:21 AM UTC 24 1446033759 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.79740263 Sep 11 08:38:18 AM UTC 24 Sep 11 08:38:21 AM UTC 24 132363259 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2230278368 Sep 11 08:38:19 AM UTC 24 Sep 11 08:38:21 AM UTC 24 106253371 ps
T3756 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_tl_errors.1747027734 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:21 AM UTC 24 341502696 ps
T558 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_tl_intg_err.1269882339 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:22 AM UTC 24 1055005121 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_tl_errors.2352248808 Sep 11 08:38:18 AM UTC 24 Sep 11 08:38:22 AM UTC 24 150489241 ps
T3757 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_tl_intg_err.11252616 Sep 11 08:38:19 AM UTC 24 Sep 11 08:38:23 AM UTC 24 790752578 ps
T565 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_tl_intg_err.2188897180 Sep 11 08:38:18 AM UTC 24 Sep 11 08:38:23 AM UTC 24 475668674 ps
T562 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_tl_intg_err.2902329166 Sep 11 08:38:18 AM UTC 24 Sep 11 08:38:23 AM UTC 24 535997577 ps
T3758 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_tl_intg_err.703162087 Sep 11 08:38:16 AM UTC 24 Sep 11 08:38:23 AM UTC 24 2532044677 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_intr_test.1591465356 Sep 11 08:38:19 AM UTC 24 Sep 11 08:38:24 AM UTC 24 57929453 ps
T3759 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_csr_rw.2444096972 Sep 11 08:38:19 AM UTC 24 Sep 11 08:38:24 AM UTC 24 67693945 ps
T3760 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1678512920 Sep 11 08:38:19 AM UTC 24 Sep 11 08:38:24 AM UTC 24 176193051 ps
T563 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_intg_err.2952465406 Sep 11 08:38:19 AM UTC 24 Sep 11 08:38:28 AM UTC 24 1171377955 ps
T3761 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_rw.2708956082 Sep 11 08:38:19 AM UTC 24 Sep 11 08:38:34 AM UTC 24 49958375 ps
T3762 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_errors.197116052 Sep 11 08:38:19 AM UTC 24 Sep 11 08:38:34 AM UTC 24 65003663 ps
T3763 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_rw.2416374460 Sep 11 08:38:22 AM UTC 24 Sep 11 08:38:34 AM UTC 24 52142830 ps
T3764 /workspaces/repo/scratch/os_regression_2024_09_10/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.968969995 Sep 11 08:38:19 AM UTC 24 Sep 11 08:38:34 AM UTC 24 166534800 ps
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