Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	171408	1			T1	6		T2	4		T3	7
all_values[1]	171408	1			T1	6		T2	4		T3	7
all_values[2]	171408	1			T1	6		T2	4		T3	7
all_values[3]	171408	1			T1	6		T2	4		T3	7
all_values[4]	171408	1			T1	6		T2	4		T3	7
all_values[5]	171408	1			T1	6		T2	4		T3	7
all_values[6]	171408	1			T1	6		T2	4		T3	7
all_values[7]	171408	1			T1	6		T2	4		T3	7
all_values[8]	171408	1			T1	6		T2	4		T3	7
all_values[9]	171408	1			T1	6		T2	4		T3	7
all_values[10]	171408	1			T1	6		T2	4		T3	7
all_values[11]	171408	1			T1	6		T2	4		T3	7
all_values[12]	171408	1			T1	6		T2	4		T3	7
all_values[13]	171408	1			T1	6		T2	4		T3	7
all_values[14]	171408	1			T1	6		T2	4		T3	7
all_values[15]	171408	1			T1	6		T2	4		T3	7
all_values[16]	171408	1			T1	6		T2	4		T3	7
all_values[17]	171408	1			T1	6		T2	4		T3	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5475677

1

T1

189

T2

128

T3

219

auto[1]

9379

1

T1

3

T3

5

T39

2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4701573

1

T1

177

T2

110

T3

210

auto[1]

783483

1

T1

15

T2

18

T3

14

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	142789	1			T1	3		T2	3		T3	7
all_values[0]	auto[0]	auto[1]	25413	1			T1	3		T2	1		T30	3
all_values[0]	auto[1]	auto[0]	3105	1			T18	3		T52	3		T53	3
all_values[0]	auto[1]	auto[1]	101	1			T52	1		T585	1		T586	1
all_values[1]	auto[0]	auto[0]	166979	1			T1	6		T2	4		T3	7
all_values[1]	auto[0]	auto[1]	3031	1			T28	2		T29	2		T30	1
all_values[1]	auto[1]	auto[0]	524	1			T34	2		T49	2		T54	2
all_values[1]	auto[1]	auto[1]	874	1			T34	1		T49	12		T54	1
all_values[2]	auto[0]	auto[0]	4350	1			T1	5		T2	1		T3	6
all_values[2]	auto[0]	auto[1]	166807	1			T1	1		T2	3		T3	1
all_values[2]	auto[1]	auto[0]	136	1			T41	1		T66	1		T67	1
all_values[2]	auto[1]	auto[1]	115	1			T41	1		T66	1		T67	1
all_values[3]	auto[0]	auto[0]	169478	1			T1	6		T2	4		T3	7
all_values[3]	auto[0]	auto[1]	290	1			T51	1		T68	1		T69	1
all_values[3]	auto[1]	auto[0]	1584	1			T51	1484		T236	1		T239	3
all_values[3]	auto[1]	auto[1]	56	1			T51	1		T234	1		T236	3
all_values[4]	auto[0]	auto[0]	4338	1			T1	5		T2	1		T3	6
all_values[4]	auto[0]	auto[1]	166928	1			T1	1		T2	3		T3	1
all_values[4]	auto[1]	auto[0]	90	1			T50	1		T234	2		T236	2
all_values[4]	auto[1]	auto[1]	52	1			T50	1		T236	1		T238	3
all_values[5]	auto[0]	auto[0]	170911	1			T1	6		T2	4		T3	7
all_values[5]	auto[0]	auto[1]	341	1			T7	1		T63	1		T8	1
all_values[5]	auto[1]	auto[0]	91	1			T234	1		T236	5		T238	2
all_values[5]	auto[1]	auto[1]	65	1			T234	1		T236	1		T325	4
all_values[6]	auto[0]	auto[0]	171013	1			T1	6		T2	4		T3	7
all_values[6]	auto[0]	auto[1]	219	1			T8	1		T68	1		T70	1
all_values[6]	auto[1]	auto[0]	87	1			T234	6		T236	1		T239	1
all_values[6]	auto[1]	auto[1]	89	1			T71	1		T72	1		T73	1
all_values[7]	auto[0]	auto[0]	115183	1			T1	1		T3	5		T39	3
all_values[7]	auto[0]	auto[1]	56073	1			T1	2		T2	4		T3	2
all_values[7]	auto[1]	auto[0]	99	1			T1	2		T55	2		T56	2
all_values[7]	auto[1]	auto[1]	53	1			T1	1		T55	1		T56	1
all_values[8]	auto[0]	auto[0]	170520	1			T1	6		T2	4		T3	7
all_values[8]	auto[0]	auto[1]	240	1			T35	2		T36	2		T207	2
all_values[8]	auto[1]	auto[0]	574	1			T57	10		T58	10		T59	10
all_values[8]	auto[1]	auto[1]	74	1			T57	1		T58	1		T61	1
all_values[9]	auto[0]	auto[0]	171174	1			T1	6		T2	4		T3	2
all_values[9]	auto[0]	auto[1]	53	1			T234	4		T325	4		T326	1
all_values[9]	auto[1]	auto[0]	102	1			T3	3		T64	3		T65	3
all_values[9]	auto[1]	auto[1]	79	1			T3	2		T64	2		T65	2
all_values[10]	auto[0]	auto[0]	170876	1			T1	6		T2	4		T3	7
all_values[10]	auto[0]	auto[1]	376	1			T29	1		T33	2		T38	1
all_values[10]	auto[1]	auto[0]	86	1			T236	1		T238	5		T325	1
all_values[10]	auto[1]	auto[1]	70	1			T234	1		T236	1		T239	1
all_values[11]	auto[0]	auto[0]	170509	1			T1	6		T2	4		T3	7
all_values[11]	auto[0]	auto[1]	656	1			T39	1		T32	4		T37	4
all_values[11]	auto[1]	auto[0]	138	1			T76	1		T77	1		T78	1
all_values[11]	auto[1]	auto[1]	105	1			T76	1		T77	1		T78	1
all_values[12]	auto[0]	auto[0]	171060	1			T1	6		T2	4		T3	7
all_values[12]	auto[0]	auto[1]	191	1			T81	1		T83	1		T84	1
all_values[12]	auto[1]	auto[0]	101	1			T79	2		T80	2		T82	2
all_values[12]	auto[1]	auto[1]	56	1			T79	1		T80	1		T82	1
all_values[13]	auto[0]	auto[0]	171080	1			T1	6		T2	4		T3	7
all_values[13]	auto[0]	auto[1]	60	1			T81	1		T83	1		T84	1
all_values[13]	auto[1]	auto[0]	173	1			T39	1		T85	1		T86	1
all_values[13]	auto[1]	auto[1]	95	1			T39	1		T85	1		T86	1
all_values[14]	auto[0]	auto[0]	35537	1			T1	6		T2	4		T3	7
all_values[14]	auto[0]	auto[1]	135713	1			T41	1		T24	1		T51	1486
all_values[14]	auto[1]	auto[0]	98	1			T234	2		T236	5		T239	1
all_values[14]	auto[1]	auto[1]	60	1			T234	2		T236	2		T239	3
all_values[15]	auto[0]	auto[0]	4393	1			T1	5		T2	1		T3	6
all_values[15]	auto[0]	auto[1]	166871	1			T1	1		T2	3		T3	1
all_values[15]	auto[1]	auto[0]	87	1			T234	1		T325	2		T315	3
all_values[15]	auto[1]	auto[1]	57	1			T234	1		T236	3		T325	2
all_values[16]	auto[0]	auto[0]	170397	1			T1	6		T2	4		T3	7
all_values[16]	auto[0]	auto[1]	856	1			T29	1		T35	1		T75	1
all_values[16]	auto[1]	auto[0]	95	1			T32	4		T37	4		T74	4
all_values[16]	auto[1]	auto[1]	60	1			T32	4		T37	4		T74	4
all_values[17]	auto[0]	auto[0]	114007	1			T87	2		T88	2		T35	2
all_values[17]	auto[0]	auto[1]	57253	1			T1	6		T2	4		T3	7
all_values[17]	auto[1]	auto[0]	97	1			T62	2		T234	4		T236	3
all_values[17]	auto[1]	auto[1]	51	1			T62	1		T236	1		T239	2