Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.38 98.21 96.03 97.44 94.92 98.38 98.21 98.46


Total tests in report: 3848
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
66.01 66.01 87.41 87.41 68.93 68.93 60.02 60.02 50.85 50.85 80.87 80.87 91.07 91.07 22.90 22.90 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_restore.3737332734
72.02 6.02 87.53 0.11 72.29 3.35 83.05 23.03 52.54 1.69 81.11 0.25 91.07 0.00 36.56 13.67 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_host_lost.1331368405
75.86 3.84 90.97 3.44 80.40 8.11 86.25 3.20 52.54 0.00 90.47 9.36 91.47 0.40 38.91 2.35 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_disable_endpoint.144867419
79.18 3.32 93.56 2.59 83.68 3.28 87.85 1.60 62.71 10.17 93.76 3.29 93.45 1.98 39.28 0.36 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_disconnect.496079655
81.32 2.14 94.26 0.70 83.71 0.02 89.77 1.92 62.71 0.00 93.76 0.00 93.45 0.00 51.58 12.31 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_intr_test.474859259
83.08 1.76 94.58 0.32 85.39 1.69 89.98 0.21 69.49 6.78 94.47 0.71 93.45 0.00 54.21 2.62 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_resets.249779244
84.22 1.13 95.72 1.14 85.97 0.57 91.47 1.49 69.49 0.00 94.55 0.08 95.83 2.38 56.47 2.26 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_intg_err.1982018311
85.28 1.07 95.89 0.17 86.66 0.69 91.47 0.00 74.58 5.08 94.72 0.17 95.83 0.00 57.83 1.36 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_low_speed_traffic.2361624730
86.08 0.80 96.37 0.48 88.27 1.62 91.90 0.43 74.58 0.00 95.55 0.83 95.83 0.00 60.09 2.26 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_access.1333796721
86.83 0.75 96.41 0.04 88.73 0.45 91.90 0.00 74.58 0.00 95.67 0.12 95.83 0.00 64.71 4.62 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_device_address.791459162
87.43 0.60 96.46 0.06 88.82 0.10 92.11 0.21 77.97 3.39 95.76 0.08 95.83 0.00 65.07 0.36 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/5.usbdev_link_resume.3207077657
88.02 0.59 96.63 0.17 88.82 0.00 92.64 0.53 81.36 3.39 95.80 0.04 95.83 0.00 65.07 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/4.usbdev_aon_wake_reset.2374243202
88.57 0.55 96.81 0.17 88.92 0.10 92.64 0.00 84.75 3.39 95.97 0.17 95.83 0.00 65.07 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.917059663
89.11 0.54 96.81 0.00 88.96 0.05 95.63 2.99 84.75 0.00 95.97 0.00 96.03 0.20 65.61 0.54 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_sec_cm.3961563611
89.59 0.48 96.81 0.00 88.96 0.00 95.63 0.00 88.14 3.39 95.97 0.00 96.03 0.00 65.61 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/116.usbdev_tx_rx_disruption.2955091238
90.05 0.46 96.81 0.00 89.84 0.88 95.63 0.00 88.14 0.00 96.01 0.04 96.43 0.40 67.51 1.90 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_errors.2168905644
90.49 0.44 97.55 0.74 90.98 1.14 95.63 0.00 88.14 0.00 97.17 1.16 96.43 0.00 67.51 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_phy_pins_sense.2441465762
90.91 0.42 97.55 0.00 91.08 0.10 95.84 0.21 88.14 0.00 97.17 0.00 96.43 0.00 70.14 2.62 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_intr_test.2318405698
91.28 0.38 97.85 0.30 91.96 0.88 95.84 0.00 88.14 0.00 97.71 0.54 96.43 0.00 71.04 0.90 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_levels.327277579
91.65 0.37 97.85 0.00 92.03 0.07 96.06 0.21 89.83 1.69 97.71 0.00 96.43 0.00 71.67 0.63 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_disconnected.2846307335
91.99 0.34 97.91 0.06 93.43 1.40 96.06 0.00 89.83 0.00 97.80 0.08 96.43 0.00 72.49 0.81 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_stress_usb_traffic.3942164051
92.25 0.26 97.91 0.00 93.43 0.00 96.16 0.11 91.53 1.69 97.80 0.00 96.43 0.00 72.49 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/39.usbdev_tx_rx_disruption.103453414
92.50 0.25 97.93 0.02 93.43 0.00 96.16 0.00 93.22 1.69 97.84 0.04 96.43 0.00 72.49 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/11.usbdev_aon_wake_reset.2157160704
92.74 0.24 97.93 0.00 93.43 0.00 96.16 0.00 94.92 1.69 97.84 0.00 96.43 0.00 72.49 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/117.usbdev_tx_rx_disruption.2078611018
92.94 0.20 97.93 0.00 93.43 0.00 96.16 0.00 94.92 0.00 97.84 0.00 97.82 1.39 72.49 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_partial_access.2576846617
93.13 0.19 97.93 0.00 93.51 0.07 96.16 0.00 94.92 0.00 97.84 0.00 97.82 0.00 73.76 1.27 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_device_address.3140735759
93.27 0.14 97.93 0.00 93.51 0.00 96.16 0.00 94.92 0.00 97.84 0.00 97.82 0.00 74.75 1.00 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_endpoint_types.3136622850
93.42 0.14 97.95 0.02 93.77 0.26 96.48 0.32 94.92 0.00 98.04 0.21 97.82 0.00 74.93 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_pinflip.3874976257
93.54 0.13 97.95 0.00 93.82 0.05 96.70 0.21 94.92 0.00 98.04 0.00 97.82 0.00 75.57 0.63 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_rx_full.3123463628
93.66 0.12 97.95 0.00 93.82 0.00 96.70 0.00 94.92 0.00 98.04 0.00 97.82 0.00 76.38 0.81 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/138.usbdev_endpoint_types.204848728
93.78 0.12 97.95 0.00 93.82 0.00 96.70 0.00 94.92 0.00 98.04 0.00 97.82 0.00 77.19 0.81 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/80.usbdev_endpoint_types.2501101610
93.89 0.11 97.95 0.00 93.89 0.07 96.70 0.00 94.92 0.00 98.04 0.00 97.82 0.00 77.92 0.72 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_device_address.1724060210
93.99 0.10 97.95 0.00 93.89 0.00 96.70 0.00 94.92 0.00 98.04 0.00 97.82 0.00 78.64 0.72 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/156.usbdev_endpoint_types.70735994
94.10 0.10 97.95 0.00 93.89 0.00 96.70 0.00 94.92 0.00 98.04 0.00 97.82 0.00 79.37 0.72 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/193.usbdev_endpoint_types.1218518169
94.20 0.10 97.95 0.00 93.89 0.00 96.70 0.00 94.92 0.00 98.04 0.00 97.82 0.00 80.09 0.72 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/5.usbdev_endpoint_types.1529644117
94.30 0.10 97.95 0.00 93.93 0.05 96.91 0.21 94.92 0.00 98.04 0.00 97.82 0.00 80.54 0.45 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_bitstuff_err.1772773336
94.40 0.10 97.95 0.00 93.98 0.05 97.12 0.21 94.92 0.00 98.04 0.00 97.82 0.00 81.00 0.45 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_rx_crc_err.1609409346
94.50 0.10 97.95 0.00 94.27 0.29 97.12 0.00 94.92 0.00 98.04 0.00 98.21 0.40 81.00 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_rand_bus_disconnects.2756835617
94.59 0.09 97.95 0.00 94.29 0.02 97.12 0.00 94.92 0.00 98.04 0.00 98.21 0.00 81.63 0.63 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_device_address.2068590951
94.69 0.09 97.95 0.00 94.29 0.00 97.12 0.00 94.92 0.00 98.04 0.00 98.21 0.00 82.26 0.63 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/163.usbdev_endpoint_types.2538008039
94.77 0.09 97.98 0.04 94.41 0.12 97.12 0.00 94.92 0.00 98.13 0.08 98.21 0.00 82.62 0.36 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority.3615801455
94.85 0.08 97.98 0.00 94.41 0.00 97.12 0.00 94.92 0.00 98.13 0.00 98.21 0.00 83.17 0.54 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_intg_err.316917950
94.93 0.08 97.98 0.00 94.41 0.00 97.12 0.00 94.92 0.00 98.13 0.00 98.21 0.00 83.71 0.54 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_intr_test.2434919475
95.00 0.08 97.98 0.00 94.41 0.00 97.12 0.00 94.92 0.00 98.13 0.00 98.21 0.00 84.25 0.54 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/196.usbdev_endpoint_types.2512681038
95.08 0.08 97.98 0.00 94.41 0.00 97.12 0.00 94.92 0.00 98.13 0.00 98.21 0.00 84.80 0.54 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/91.usbdev_endpoint_types.3487061204
95.15 0.06 97.98 0.00 94.41 0.00 97.12 0.00 94.92 0.00 98.13 0.00 98.21 0.00 85.25 0.45 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/12.usbdev_data_toggle_restore.3967990860
95.21 0.06 97.98 0.00 94.41 0.00 97.12 0.00 94.92 0.00 98.13 0.00 98.21 0.00 85.70 0.45 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/12.usbdev_endpoint_types.1610049482
95.28 0.06 97.98 0.00 94.41 0.00 97.12 0.00 94.92 0.00 98.13 0.00 98.21 0.00 86.15 0.45 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/183.usbdev_endpoint_types.1238488966
95.34 0.06 97.98 0.00 94.41 0.00 97.12 0.00 94.92 0.00 98.13 0.00 98.21 0.00 86.61 0.45 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/7.usbdev_endpoint_types.1270948734
95.39 0.05 97.98 0.00 94.41 0.00 97.12 0.00 94.92 0.00 98.13 0.00 98.21 0.00 86.97 0.36 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/148.usbdev_endpoint_types.1427548084
95.44 0.05 97.98 0.00 94.41 0.00 97.12 0.00 94.92 0.00 98.13 0.00 98.21 0.00 87.33 0.36 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/162.usbdev_endpoint_types.3350863921
95.50 0.05 97.98 0.00 94.41 0.00 97.12 0.00 94.92 0.00 98.13 0.00 98.21 0.00 87.69 0.36 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_data_toggle_restore.759692261
95.55 0.05 97.98 0.00 94.41 0.00 97.12 0.00 94.92 0.00 98.13 0.00 98.21 0.00 88.05 0.36 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/4.usbdev_endpoint_types.674016873
95.60 0.05 98.00 0.02 94.51 0.10 97.23 0.11 94.92 0.00 98.17 0.04 98.21 0.00 88.14 0.09 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_tx_rx_disruption.2937320104
95.65 0.05 98.06 0.06 94.58 0.07 97.44 0.21 94.92 0.00 98.17 0.00 98.21 0.00 88.14 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_alert_test.894876394
95.69 0.04 98.08 0.02 94.65 0.07 97.44 0.00 94.92 0.00 98.21 0.04 98.21 0.00 88.33 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_link_out_err.882805596
95.73 0.04 98.08 0.00 94.84 0.19 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 88.42 0.09 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_av_overflow.2144311244
95.77 0.04 98.08 0.00 94.84 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 88.69 0.27 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_received.2735145965
95.81 0.04 98.08 0.00 94.84 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 88.96 0.27 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/120.usbdev_endpoint_types.4231171123
95.85 0.04 98.08 0.00 94.84 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 89.23 0.27 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/125.usbdev_endpoint_types.3717690773
95.89 0.04 98.08 0.00 94.84 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 89.50 0.27 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/130.usbdev_endpoint_types.2591742939
95.92 0.04 98.08 0.00 94.84 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 89.77 0.27 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/152.usbdev_endpoint_types.3452783645
95.96 0.04 98.08 0.00 94.84 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 90.05 0.27 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/16.usbdev_device_address.3834625678
96.00 0.04 98.08 0.00 94.84 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 90.32 0.27 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/31.usbdev_endpoint_types.2926532785
96.04 0.04 98.08 0.00 94.84 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 90.59 0.27 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/32.usbdev_endpoint_types.3523095910
96.08 0.04 98.08 0.00 94.84 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 90.86 0.27 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/39.usbdev_endpoint_types.3579655778
96.12 0.04 98.08 0.00 94.84 0.00 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 91.13 0.27 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/85.usbdev_endpoint_types.3891809035
96.16 0.04 98.14 0.06 94.86 0.02 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 91.31 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/4.usbdev_nak_trans.1780927087
96.19 0.03 98.14 0.00 95.10 0.24 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 91.31 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_errors.3859932704
96.22 0.03 98.14 0.00 95.12 0.02 97.44 0.00 94.92 0.00 98.21 0.00 98.21 0.00 91.49 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_low_speed_traffic.1041975273
96.25 0.03 98.17 0.04 95.15 0.02 97.44 0.00 94.92 0.00 98.25 0.04 98.21 0.00 91.58 0.09 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority_over_stall_response.3920507048
96.27 0.03 98.17 0.00 95.15 0.00 97.44 0.00 94.92 0.00 98.25 0.00 98.21 0.00 91.76 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_intr_test.1514898568
96.30 0.03 98.17 0.00 95.15 0.00 97.44 0.00 94.92 0.00 98.25 0.00 98.21 0.00 91.95 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_intg_err.411344456
96.32 0.03 98.17 0.00 95.15 0.00 97.44 0.00 94.92 0.00 98.25 0.00 98.21 0.00 92.13 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_tl_intg_err.4217664536
96.35 0.03 98.17 0.00 95.15 0.00 97.44 0.00 94.92 0.00 98.25 0.00 98.21 0.00 92.31 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_freq_loclk_max.3928158291
96.38 0.03 98.17 0.00 95.15 0.00 97.44 0.00 94.92 0.00 98.25 0.00 98.21 0.00 92.49 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/159.usbdev_endpoint_types.1199255674
96.40 0.03 98.17 0.00 95.15 0.00 97.44 0.00 94.92 0.00 98.25 0.00 98.21 0.00 92.67 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/161.usbdev_endpoint_types.2707390643
96.43 0.03 98.17 0.00 95.15 0.00 97.44 0.00 94.92 0.00 98.25 0.00 98.21 0.00 92.85 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/29.usbdev_device_address.122643322
96.45 0.03 98.17 0.00 95.15 0.00 97.44 0.00 94.92 0.00 98.25 0.00 98.21 0.00 93.03 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/36.usbdev_device_address.4079750203
96.48 0.02 98.19 0.02 95.15 0.00 97.44 0.00 94.92 0.00 98.29 0.04 98.21 0.00 93.12 0.09 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/11.usbdev_fifo_levels.3292848500
96.49 0.02 98.19 0.00 95.17 0.02 97.44 0.00 94.92 0.00 98.29 0.00 98.21 0.00 93.21 0.09 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/5.usbdev_pkt_buffer.1652436648
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97.37 0.01 98.21 0.00 95.98 0.02 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/29.usbdev_nak_trans.2526707232
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97.38 0.01 98.21 0.00 96.03 0.02 97.44 0.00 94.92 0.00 98.38 0.00 98.21 0.00 98.46 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/33.usbdev_nak_trans.1548136680

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_aliasing.1780265485
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_bit_bash.4287026093
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_hw_reset.631351237
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3306647019
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_rw.3873814260
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_intr_test.3413010569
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_walk.4163810751
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.984912623
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_errors.4294106065
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_intg_err.3153144224
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_bit_bash.777193823
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3770728602
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_partial_access.3743529403
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_walk.3194036572
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.75769210
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_rw.3356172007
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_intr_test.910704738
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.461908985
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_errors.4161027821
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_intg_err.3382258282
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.995656439
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3425731367
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_errors.3981273876
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2522082548
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_rw.3870473437
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2110003175
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_intg_err.282213626
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.187583116
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_rw.4081250950
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.4243769664
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_errors.3640744966
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_intg_err.2657696618
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1219501872
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_rw.2994354224
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_intr_test.3456459927
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2567137459
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_errors.4125246209
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_intg_err.3627088482
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3248776564
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_rw.626709022
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_intr_test.2332844814
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.4143631316
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_errors.3658499070
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_intg_err.2023642641
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.457696985
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_rw.3361912091
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_intr_test.4238902564
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1348148825
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_tl_errors.237041220
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2914148765
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_csr_rw.3770858130
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_intr_test.3228708349
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3154871418
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_errors.899827552
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.570884420
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_csr_rw.661058578
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_intr_test.2873503454
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.562598877
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_tl_errors.1973802885
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_tl_intg_err.1704604611
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2420829898
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.516161189
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_tl_errors.1577167774
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_aliasing.3801049403
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_bit_bash.546575194
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_hw_reset.346289355
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1404477680
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_rw.1224873088
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_partial_access.188629502
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_walk.3995336535
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2637889839
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/20.usbdev_intr_test.3617047809
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/21.usbdev_intr_test.2268323522
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/22.usbdev_intr_test.115309959
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/23.usbdev_intr_test.1251959994
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/24.usbdev_intr_test.690465969
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/25.usbdev_intr_test.286510169
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/26.usbdev_intr_test.661579564
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/27.usbdev_intr_test.3151482958
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/28.usbdev_intr_test.212812754
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/29.usbdev_intr_test.3827198348
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_aliasing.3395290634
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_bit_bash.845714707
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1126362195
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1505675409
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_rw.1616171599
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_intr_test.2769965555
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_partial_access.2599433607
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_walk.2319376100
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3678672486
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_errors.2512597265
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_intg_err.3846706506
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/30.usbdev_intr_test.2365533504
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/31.usbdev_intr_test.4145225928
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/32.usbdev_intr_test.3082074915
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/33.usbdev_intr_test.2116141990
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/34.usbdev_intr_test.3684420455
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/35.usbdev_intr_test.4042008637
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/36.usbdev_intr_test.2807754028
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/37.usbdev_intr_test.3307886283
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/38.usbdev_intr_test.2320016168
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/39.usbdev_intr_test.1778397894
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_aliasing.101261972
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2540707450
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1650019799
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_rw.1616842034
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_intr_test.843752700
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_partial_access.3760703736
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_walk.2290173893
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_errors.1272157567
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_intg_err.3674751645
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/40.usbdev_intr_test.2502283639
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/41.usbdev_intr_test.690995105
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/42.usbdev_intr_test.167336664
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/43.usbdev_intr_test.3928222520
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/44.usbdev_intr_test.911413104
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/45.usbdev_intr_test.266055001
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/46.usbdev_intr_test.2009128962
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/47.usbdev_intr_test.2713156947
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/48.usbdev_intr_test.3315655067
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/49.usbdev_intr_test.3371873406
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3109943213
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.872619527
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.4276205118
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_csr_rw.2610606402
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_intr_test.1098747131
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4236960611
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_tl_errors.365679945
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_tl_intg_err.2209014447
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2722399779
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_csr_rw.9745150
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_intr_test.1163060882
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.635749831
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_tl_errors.3091431716
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_tl_intg_err.4116157711
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.649286341
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_csr_rw.2774312605
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_intr_test.3159710300
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2907760652
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_tl_errors.3247409939
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/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_endpoint_types.3859922265
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_fifo_levels.156905888
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_fifo_rst.1911562540
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_in_iso.3567178215
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_in_stall.554930865
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_in_trans.3955977141
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_invalid_sync.3071230565
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_iso_retraction.915889341
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_link_in_err.2835806898
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_link_resume.1338339046
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_link_suspend.2401679865
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_low_speed_traffic.283150947
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_max_inter_pkt_delay.2590291184
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_max_length_in_transaction.3576364908
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_max_length_out_transaction.914427956
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_max_non_iso_usb_traffic.2949790712
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_max_usb_traffic.483827338
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_min_inter_pkt_delay.4277986017
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_min_length_in_transaction.200974312
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_min_length_out_transaction.1410065545
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_nak_trans.4253959459
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_out_iso.767635003
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_out_stall.530560926
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_out_trans_nak.4180764907
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_pending_in_trans.2563227347
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_phy_config_pinflip.3972263050
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_phy_config_usb_ref_disable.2274898112
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_phy_pins_sense.2467646418
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_pkt_buffer.309578086
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_pkt_received.4132719745
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_pkt_sent.2405259766
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_rand_bus_disconnects.3634179113
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_rand_bus_resets.362913730
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_rand_suspends.1379838242
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_random_length_in_transaction.689577485
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_random_length_out_transaction.3804154926
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_resume_link_active.3493225446
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_rx_crc_err.3212378399
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_rx_full.3895184771
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_setup_stage.1900642762
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_setup_trans_ignored.2287871044
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_smoke.4012848734
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_spurious_pids_ignored.2436692391
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_stall_priority_over_nak.2106624297
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_stall_trans.1932886324
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_stream_len_max.513275276
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_streaming_out.3680194538
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_stress_usb_traffic.37965091
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_timeout_missing_host_handshake.1342741752
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/9.usbdev_tx_rx_disruption.1631958355
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/90.usbdev_endpoint_types.2443440721
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/90.usbdev_fifo_levels.4061302325
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/90.usbdev_tx_rx_disruption.3991389804
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/91.usbdev_fifo_levels.2469445630
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/91.usbdev_tx_rx_disruption.1940048571
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/92.usbdev_endpoint_types.1854197088
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/92.usbdev_fifo_levels.868180878
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/92.usbdev_tx_rx_disruption.2276698252
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/93.usbdev_endpoint_types.3337726080
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/93.usbdev_fifo_levels.644081593
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/93.usbdev_tx_rx_disruption.615690127
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/94.usbdev_endpoint_types.2167569940
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/94.usbdev_fifo_levels.2984849640
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/94.usbdev_tx_rx_disruption.3042826080
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/95.usbdev_endpoint_types.1710371906
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/95.usbdev_fifo_levels.2521192743
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/95.usbdev_tx_rx_disruption.2956282546
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/96.usbdev_endpoint_types.3663924665
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/96.usbdev_fifo_levels.2570945984
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/96.usbdev_tx_rx_disruption.2904736991
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/97.usbdev_endpoint_types.2631175593
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/97.usbdev_fifo_levels.3499622787
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/97.usbdev_tx_rx_disruption.2410233853
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/98.usbdev_endpoint_types.3288716942
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/98.usbdev_tx_rx_disruption.4092446927
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/99.usbdev_endpoint_types.2794246655
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/99.usbdev_fifo_levels.3106708888
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/99.usbdev_tx_rx_disruption.2381023444



Total test records in report: 3848
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TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_av_empty.1498650706 Sep 18 12:50:43 PM UTC 24 Sep 18 12:50:46 PM UTC 24 159782103 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_av_buffer.2351599253 Sep 18 12:50:43 PM UTC 24 Sep 18 12:50:46 PM UTC 24 176931380 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_av_overflow.2144311244 Sep 18 12:50:43 PM UTC 24 Sep 18 12:50:46 PM UTC 24 142846755 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_bitstuff_err.1772773336 Sep 18 12:50:43 PM UTC 24 Sep 18 12:50:46 PM UTC 24 149584932 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_clear.3814886188 Sep 18 12:50:43 PM UTC 24 Sep 18 12:50:46 PM UTC 24 491018292 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_restore.3737332734 Sep 18 12:50:43 PM UTC 24 Sep 18 12:50:48 PM UTC 24 1089710759 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_in_iso.3943468978 Sep 18 12:50:45 PM UTC 24 Sep 18 12:50:48 PM UTC 24 300372420 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_enable.4210836004 Sep 18 12:50:45 PM UTC 24 Sep 18 12:50:48 PM UTC 24 65504931 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_in_stall.720169700 Sep 18 12:50:45 PM UTC 24 Sep 18 12:50:48 PM UTC 24 155885865 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_disconnected.2846307335 Sep 18 12:50:45 PM UTC 24 Sep 18 12:50:48 PM UTC 24 137740768 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.522709030 Sep 18 12:50:45 PM UTC 24 Sep 18 12:50:48 PM UTC 24 556954052 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_types.759114603 Sep 18 12:50:45 PM UTC 24 Sep 18 12:50:48 PM UTC 24 228606852 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_disable_endpoint.144867419 Sep 18 12:50:45 PM UTC 24 Sep 18 12:50:48 PM UTC 24 433990088 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_link_in_err.659569017 Sep 18 12:50:45 PM UTC 24 Sep 18 12:50:49 PM UTC 24 212991237 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_in_trans.1406530856 Sep 18 12:50:45 PM UTC 24 Sep 18 12:50:49 PM UTC 24 195583727 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_levels.327277579 Sep 18 12:50:45 PM UTC 24 Sep 18 12:50:49 PM UTC 24 268022836 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_rst.2689717228 Sep 18 12:50:45 PM UTC 24 Sep 18 12:50:50 PM UTC 24 283785821 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_link_out_err.882805596 Sep 18 12:50:47 PM UTC 24 Sep 18 12:50:50 PM UTC 24 576801795 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_device_timeout.3539832804 Sep 18 12:50:45 PM UTC 24 Sep 18 12:50:50 PM UTC 24 283766666 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_link_reset.2583251695 Sep 18 12:50:48 PM UTC 24 Sep 18 12:50:50 PM UTC 24 200941449 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_access.1333796721 Sep 18 12:50:45 PM UTC 24 Sep 18 12:50:51 PM UTC 24 1066537953 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_disconnect.496079655 Sep 18 12:50:43 PM UTC 24 Sep 18 12:50:52 PM UTC 24 4568433441 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.4042881846 Sep 18 12:50:50 PM UTC 24 Sep 18 12:50:53 PM UTC 24 169768873 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_rx_dp_dn.3593393490 Sep 18 12:50:50 PM UTC 24 Sep 18 12:50:53 PM UTC 24 239115912 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.917059663 Sep 18 12:50:50 PM UTC 24 Sep 18 12:50:53 PM UTC 24 307056554 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_max_length_out_transaction.537804633 Sep 18 12:50:48 PM UTC 24 Sep 18 12:50:53 PM UTC 24 226197019 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_max_length_in_transaction.2516180186 Sep 18 12:50:48 PM UTC 24 Sep 18 12:50:53 PM UTC 24 266814774 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_min_length_in_transaction.3294701122 Sep 18 12:50:48 PM UTC 24 Sep 18 12:50:53 PM UTC 24 156757038 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_phy_pins_sense.2441465762 Sep 18 12:50:52 PM UTC 24 Sep 18 12:50:54 PM UTC 24 58008683 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_usb_ref_disable.756496525 Sep 18 12:50:52 PM UTC 24 Sep 18 12:50:54 PM UTC 24 143119169 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_min_length_out_transaction.3694730938 Sep 18 12:50:49 PM UTC 24 Sep 18 12:50:54 PM UTC 24 179559344 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_received.2735145965 Sep 18 12:50:52 PM UTC 24 Sep 18 12:50:54 PM UTC 24 182854530 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_sent.293791724 Sep 18 12:50:52 PM UTC 24 Sep 18 12:50:54 PM UTC 24 168124600 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_use_d_se0.1179479723 Sep 18 12:50:52 PM UTC 24 Sep 18 12:50:54 PM UTC 24 263261992 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_random_length_in_transaction.2773664839 Sep 18 12:50:52 PM UTC 24 Sep 18 12:50:55 PM UTC 24 202221728 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_out_stall.1886499337 Sep 18 12:50:49 PM UTC 24 Sep 18 12:50:55 PM UTC 24 181766347 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_out_iso.271905553 Sep 18 12:50:49 PM UTC 24 Sep 18 12:50:55 PM UTC 24 170985172 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_nak_trans.2550245362 Sep 18 12:50:49 PM UTC 24 Sep 18 12:50:55 PM UTC 24 183121503 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_link_suspend.681449983 Sep 18 12:50:48 PM UTC 24 Sep 18 12:50:55 PM UTC 24 3907108180 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_rand_bus_type.2140874326 Sep 18 12:50:50 PM UTC 24 Sep 18 12:50:55 PM UTC 24 237892715 ps
T579 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_out_trans_nak.3382706490 Sep 18 12:50:50 PM UTC 24 Sep 18 12:50:55 PM UTC 24 178474289 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_pending_in_trans.2708469210 Sep 18 12:50:50 PM UTC 24 Sep 18 12:50:55 PM UTC 24 149255257 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_pinflip.3874976257 Sep 18 12:50:50 PM UTC 24 Sep 18 12:50:55 PM UTC 24 256204309 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.1346982888 Sep 18 12:50:49 PM UTC 24 Sep 18 12:50:56 PM UTC 24 515555873 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_host_lost.1331368405 Sep 18 12:50:45 PM UTC 24 Sep 18 12:50:57 PM UTC 24 4167052441 ps
T632 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_random_length_out_transaction.1532586549 Sep 18 12:50:55 PM UTC 24 Sep 18 12:50:58 PM UTC 24 162911680 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_rx_crc_err.1609409346 Sep 18 12:50:55 PM UTC 24 Sep 18 12:50:58 PM UTC 24 162090058 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_rx_full.1482790377 Sep 18 12:50:55 PM UTC 24 Sep 18 12:50:58 PM UTC 24 244697387 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_setup_trans_ignored.2357315129 Sep 18 12:50:57 PM UTC 24 Sep 18 12:50:59 PM UTC 24 150973489 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_bitstuff_err.2832011939 Sep 18 12:51:01 PM UTC 24 Sep 18 12:51:04 PM UTC 24 183631770 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_disable_endpoint.2609177793 Sep 18 12:51:02 PM UTC 24 Sep 18 12:51:05 PM UTC 24 490267781 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_setup_stage.1263396602 Sep 18 12:50:57 PM UTC 24 Sep 18 12:50:59 PM UTC 24 147559309 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_in_trans.763091500 Sep 18 12:51:07 PM UTC 24 Sep 18 12:51:10 PM UTC 24 208304122 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_rx_pid_err.2977487008 Sep 18 12:50:57 PM UTC 24 Sep 18 12:50:59 PM UTC 24 177634468 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority_over_stall_response.3920507048 Sep 18 12:50:57 PM UTC 24 Sep 18 12:50:59 PM UTC 24 207317364 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_stall_priority_over_nak.3358224437 Sep 18 12:50:57 PM UTC 24 Sep 18 12:50:59 PM UTC 24 178706747 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority.3615801455 Sep 18 12:50:57 PM UTC 24 Sep 18 12:51:00 PM UTC 24 456484093 ps
T582 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_stall_trans.3882074405 Sep 18 12:50:57 PM UTC 24 Sep 18 12:51:00 PM UTC 24 172237539 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_smoke.3476295458 Sep 18 12:50:57 PM UTC 24 Sep 18 12:51:00 PM UTC 24 213554417 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_tx_rx_disruption.2937320104 Sep 18 12:50:57 PM UTC 24 Sep 18 12:51:01 PM UTC 24 489109314 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_stream_len_max.2663420142 Sep 18 12:50:57 PM UTC 24 Sep 18 12:51:01 PM UTC 24 602920627 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_alert_test.894876394 Sep 18 12:51:00 PM UTC 24 Sep 18 12:51:02 PM UTC 24 40730577 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_sec_cm.3961563611 Sep 18 12:51:00 PM UTC 24 Sep 18 12:51:02 PM UTC 24 894139831 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_av_buffer.1366519362 Sep 18 12:51:00 PM UTC 24 Sep 18 12:51:04 PM UTC 24 172246976 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_av_empty.3241485573 Sep 18 12:51:00 PM UTC 24 Sep 18 12:51:04 PM UTC 24 166242965 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_av_overflow.430396906 Sep 18 12:51:00 PM UTC 24 Sep 18 12:51:04 PM UTC 24 138443065 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_reset.1441162161 Sep 18 12:50:43 PM UTC 24 Sep 18 12:51:04 PM UTC 24 15781313607 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_data_toggle_restore.3549289885 Sep 18 12:51:02 PM UTC 24 Sep 18 12:51:05 PM UTC 24 433381235 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_max_inter_pkt_delay.1197194045 Sep 18 12:50:48 PM UTC 24 Sep 18 12:51:06 PM UTC 24 2274572252 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_enable.68553681 Sep 18 12:51:04 PM UTC 24 Sep 18 12:51:06 PM UTC 24 31024765 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_disconnected.338476459 Sep 18 12:51:03 PM UTC 24 Sep 18 12:51:06 PM UTC 24 140452706 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_data_toggle_clear.2325643948 Sep 18 12:51:02 PM UTC 24 Sep 18 12:51:06 PM UTC 24 493357270 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_timeout_missing_host_handshake.995848912 Sep 18 12:50:45 PM UTC 24 Sep 18 12:51:07 PM UTC 24 995210709 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_fifo_levels.1880926357 Sep 18 12:51:06 PM UTC 24 Sep 18 12:51:08 PM UTC 24 175464077 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_endpoint_access.3259924072 Sep 18 12:51:04 PM UTC 24 Sep 18 12:51:08 PM UTC 24 766828318 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_endpoint_types.684604204 Sep 18 12:51:06 PM UTC 24 Sep 18 12:51:08 PM UTC 24 469193578 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_device_timeout.3508116164 Sep 18 12:51:02 PM UTC 24 Sep 18 12:51:10 PM UTC 24 775106132 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_in_stall.3147946911 Sep 18 12:51:07 PM UTC 24 Sep 18 12:51:10 PM UTC 24 196731264 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_in_iso.1447572496 Sep 18 12:51:07 PM UTC 24 Sep 18 12:51:10 PM UTC 24 194177330 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_disconnect.1952959434 Sep 18 12:51:00 PM UTC 24 Sep 18 12:51:10 PM UTC 24 4286325733 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_fifo_rst.658578822 Sep 18 12:51:06 PM UTC 24 Sep 18 12:51:11 PM UTC 24 352851535 ps
T627 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_link_in_err.1760978681 Sep 18 12:51:08 PM UTC 24 Sep 18 12:51:11 PM UTC 24 249075089 ps
T633 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_max_length_in_transaction.1563638934 Sep 18 12:51:11 PM UTC 24 Sep 18 12:51:13 PM UTC 24 233774402 ps
T634 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_max_length_out_transaction.2368872265 Sep 18 12:51:11 PM UTC 24 Sep 18 12:51:13 PM UTC 24 280903292 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_max_non_iso_usb_traffic.1838062151 Sep 18 12:50:48 PM UTC 24 Sep 18 12:51:14 PM UTC 24 2963880520 ps
T635 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_min_length_out_transaction.488547166 Sep 18 12:51:14 PM UTC 24 Sep 18 12:51:16 PM UTC 24 145489911 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_min_inter_pkt_delay.1059104427 Sep 18 12:50:48 PM UTC 24 Sep 18 12:51:16 PM UTC 24 2564154243 ps
T636 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_min_length_in_transaction.2534605072 Sep 18 12:51:14 PM UTC 24 Sep 18 12:51:16 PM UTC 24 156288441 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_disconnects.1075373049 Sep 18 12:50:55 PM UTC 24 Sep 18 12:51:17 PM UTC 24 3137951417 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_streaming_out.748809018 Sep 18 12:50:57 PM UTC 24 Sep 18 12:51:17 PM UTC 24 1718138607 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_nak_trans.3021939224 Sep 18 12:51:15 PM UTC 24 Sep 18 12:51:18 PM UTC 24 286379305 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_rand_suspends.3556780110 Sep 18 12:50:55 PM UTC 24 Sep 18 12:51:56 PM UTC 24 9488850158 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_buffer.985738914 Sep 18 12:50:52 PM UTC 24 Sep 18 12:51:19 PM UTC 24 8832475187 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_resume.2025213118 Sep 18 12:50:43 PM UTC 24 Sep 18 12:51:19 PM UTC 24 24567344860 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_out_trans_nak.176128640 Sep 18 12:51:18 PM UTC 24 Sep 18 12:51:20 PM UTC 24 163503498 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_out_stall.2236445334 Sep 18 12:51:18 PM UTC 24 Sep 18 12:51:20 PM UTC 24 167445335 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_out_iso.2160610575 Sep 18 12:51:17 PM UTC 24 Sep 18 12:51:20 PM UTC 24 152448586 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_pending_in_trans.3192885434 Sep 18 12:51:18 PM UTC 24 Sep 18 12:51:20 PM UTC 24 197792744 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_pinflip.1947006600 Sep 18 12:51:18 PM UTC 24 Sep 18 12:51:20 PM UTC 24 220015413 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_rand_bus_type.3857761334 Sep 18 12:51:19 PM UTC 24 Sep 18 12:51:21 PM UTC 24 241070262 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_link_suspend.4085370814 Sep 18 12:51:10 PM UTC 24 Sep 18 12:51:22 PM UTC 24 5432927117 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_phy_pins_sense.3530184613 Sep 18 12:51:20 PM UTC 24 Sep 18 12:51:22 PM UTC 24 47275196 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_usb_ref_disable.803424700 Sep 18 12:51:20 PM UTC 24 Sep 18 12:51:22 PM UTC 24 141357098 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_resets.249779244 Sep 18 12:50:55 PM UTC 24 Sep 18 12:51:23 PM UTC 24 6507106821 ps
T585 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_received.2292534448 Sep 18 12:51:21 PM UTC 24 Sep 18 12:51:24 PM UTC 24 156280055 ps
T637 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_sent.1836067 Sep 18 12:51:21 PM UTC 24 Sep 18 12:51:24 PM UTC 24 209513068 ps
T638 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_random_length_out_transaction.590029357 Sep 18 12:51:21 PM UTC 24 Sep 18 12:51:24 PM UTC 24 199161313 ps
T639 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_random_length_in_transaction.1039780916 Sep 18 12:51:21 PM UTC 24 Sep 18 12:51:24 PM UTC 24 269435023 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_resume_link_active.3473894458 Sep 18 12:50:55 PM UTC 24 Sep 18 12:51:24 PM UTC 24 20153882394 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_spurious_pids_ignored.1895758117 Sep 18 12:50:57 PM UTC 24 Sep 18 12:51:25 PM UTC 24 2773623478 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_reset.2945655247 Sep 18 12:51:00 PM UTC 24 Sep 18 12:51:25 PM UTC 24 16014607303 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_max_usb_traffic.1142484164 Sep 18 12:50:48 PM UTC 24 Sep 18 12:51:26 PM UTC 24 3218266036 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_rx_crc_err.1187163393 Sep 18 12:51:24 PM UTC 24 Sep 18 12:51:26 PM UTC 24 179599280 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_setup_priority_over_stall_response.2861842265 Sep 18 12:51:25 PM UTC 24 Sep 18 12:51:27 PM UTC 24 288442446 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_setup_stage.493278775 Sep 18 12:51:25 PM UTC 24 Sep 18 12:51:27 PM UTC 24 182655772 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_rx_pid_err.3394083763 Sep 18 12:51:25 PM UTC 24 Sep 18 12:51:28 PM UTC 24 212552121 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_rx_full.3123463628 Sep 18 12:51:25 PM UTC 24 Sep 18 12:51:28 PM UTC 24 257595946 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_max_inter_pkt_delay.3597968228 Sep 18 12:51:11 PM UTC 24 Sep 18 12:51:28 PM UTC 24 1642729578 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_setup_priority.2590020521 Sep 18 12:51:25 PM UTC 24 Sep 18 12:51:29 PM UTC 24 488863668 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_setup_trans_ignored.179753635 Sep 18 12:51:26 PM UTC 24 Sep 18 12:51:29 PM UTC 24 161126507 ps
T640 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_smoke.1127341398 Sep 18 12:51:26 PM UTC 24 Sep 18 12:51:29 PM UTC 24 223829424 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_max_non_iso_usb_traffic.3715658597 Sep 18 12:51:12 PM UTC 24 Sep 18 12:51:30 PM UTC 24 2045670435 ps
T583 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_stall_priority_over_nak.2138987696 Sep 18 12:51:28 PM UTC 24 Sep 18 12:51:30 PM UTC 24 150899282 ps
T641 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_max_length_in_transaction.3060801428 Sep 18 12:51:52 PM UTC 24 Sep 18 12:51:54 PM UTC 24 251621265 ps
T642 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_stall_trans.3283489154 Sep 18 12:51:29 PM UTC 24 Sep 18 12:51:31 PM UTC 24 174574525 ps
T643 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_streaming_out.1115404572 Sep 18 12:51:29 PM UTC 24 Sep 18 12:51:55 PM UTC 24 2575299142 ps
T644 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_stream_len_max.3481754658 Sep 18 12:51:29 PM UTC 24 Sep 18 12:51:32 PM UTC 24 434772386 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_sec_cm.2124416161 Sep 18 12:51:30 PM UTC 24 Sep 18 12:51:33 PM UTC 24 349394443 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_alert_test.1554841527 Sep 18 12:51:31 PM UTC 24 Sep 18 12:51:33 PM UTC 24 37036596 ps
T645 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_min_inter_pkt_delay.3265587113 Sep 18 12:51:12 PM UTC 24 Sep 18 12:51:34 PM UTC 24 2046696859 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_tx_rx_disruption.3226586700 Sep 18 12:51:30 PM UTC 24 Sep 18 12:51:34 PM UTC 24 551133225 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_stress_usb_traffic.3942164051 Sep 18 12:50:57 PM UTC 24 Sep 18 12:51:34 PM UTC 24 7976455462 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_link_resume.3564376707 Sep 18 12:50:48 PM UTC 24 Sep 18 12:51:34 PM UTC 24 28229929521 ps
T646 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_av_buffer.455997996 Sep 18 12:51:33 PM UTC 24 Sep 18 12:51:35 PM UTC 24 144232084 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_av_overflow.443285750 Sep 18 12:51:34 PM UTC 24 Sep 18 12:51:36 PM UTC 24 134379504 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_av_empty.1673605606 Sep 18 12:51:34 PM UTC 24 Sep 18 12:51:36 PM UTC 24 195133566 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_bitstuff_err.1232068215 Sep 18 12:51:35 PM UTC 24 Sep 18 12:51:37 PM UTC 24 195765350 ps
T647 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_data_toggle_clear.4236103062 Sep 18 12:51:35 PM UTC 24 Sep 18 12:51:38 PM UTC 24 435566495 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_timeout_missing_host_handshake.1156231180 Sep 18 12:51:02 PM UTC 24 Sep 18 12:51:39 PM UTC 24 3829123258 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_data_toggle_restore.759692261 Sep 18 12:51:35 PM UTC 24 Sep 18 12:51:39 PM UTC 24 1172340456 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_disconnected.3170786582 Sep 18 12:51:37 PM UTC 24 Sep 18 12:51:40 PM UTC 24 149728571 ps
T648 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_enable.3026928034 Sep 18 12:51:38 PM UTC 24 Sep 18 12:51:40 PM UTC 24 41281145 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_disable_endpoint.2148753128 Sep 18 12:51:37 PM UTC 24 Sep 18 12:51:41 PM UTC 24 557386862 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_buffer.2966523731 Sep 18 12:51:20 PM UTC 24 Sep 18 12:51:42 PM UTC 24 5788461347 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_fifo_levels.1496674265 Sep 18 12:51:40 PM UTC 24 Sep 18 12:51:42 PM UTC 24 271277496 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_endpoint_types.1225790546 Sep 18 12:51:40 PM UTC 24 Sep 18 12:51:43 PM UTC 24 550539599 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_resume.2019156791 Sep 18 12:51:00 PM UTC 24 Sep 18 12:51:43 PM UTC 24 30773881358 ps
T599 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_endpoint_access.1148550485 Sep 18 12:51:40 PM UTC 24 Sep 18 12:51:44 PM UTC 24 903122428 ps
T649 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_fifo_rst.3973523464 Sep 18 12:51:41 PM UTC 24 Sep 18 12:51:45 PM UTC 24 260912276 ps
T650 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_in_trans.1975942148 Sep 18 12:51:45 PM UTC 24 Sep 18 12:51:47 PM UTC 24 173428842 ps
T651 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_in_stall.4248582836 Sep 18 12:51:45 PM UTC 24 Sep 18 12:51:47 PM UTC 24 139785298 ps
T652 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_in_iso.2366536442 Sep 18 12:51:45 PM UTC 24 Sep 18 12:51:48 PM UTC 24 235015558 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_max_usb_traffic.3814151445 Sep 18 12:51:12 PM UTC 24 Sep 18 12:51:50 PM UTC 24 3525841267 ps
T653 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_rand_bus_resets.4217895140 Sep 18 12:51:23 PM UTC 24 Sep 18 12:51:50 PM UTC 24 5819579252 ps
T654 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_link_in_err.873099632 Sep 18 12:51:48 PM UTC 24 Sep 18 12:51:51 PM UTC 24 239000715 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_low_speed_traffic.2361624730 Sep 18 12:51:11 PM UTC 24 Sep 18 12:51:51 PM UTC 24 4928624888 ps
T655 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_max_length_out_transaction.1361398226 Sep 18 12:51:52 PM UTC 24 Sep 18 12:51:54 PM UTC 24 247728579 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_disconnect.2338320872 Sep 18 12:51:31 PM UTC 24 Sep 18 12:51:55 PM UTC 24 12142551536 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_spurious_pids_ignored.3618944399 Sep 18 12:51:28 PM UTC 24 Sep 18 12:51:55 PM UTC 24 2883566519 ps
T656 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_min_length_in_transaction.886715612 Sep 18 12:51:55 PM UTC 24 Sep 18 12:51:58 PM UTC 24 176637807 ps
T657 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_min_length_out_transaction.1299043107 Sep 18 12:51:55 PM UTC 24 Sep 18 12:51:58 PM UTC 24 164129962 ps
T658 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_out_stall.395072247 Sep 18 12:51:57 PM UTC 24 Sep 18 12:51:59 PM UTC 24 184610981 ps
T659 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_out_iso.2365911766 Sep 18 12:51:57 PM UTC 24 Sep 18 12:51:59 PM UTC 24 222791836 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_nak_trans.2776207000 Sep 18 12:51:57 PM UTC 24 Sep 18 12:51:59 PM UTC 24 194818233 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_reset.3828493462 Sep 18 12:51:32 PM UTC 24 Sep 18 12:52:00 PM UTC 24 15077439380 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_pending_in_trans.34219777 Sep 18 12:51:59 PM UTC 24 Sep 18 12:52:01 PM UTC 24 147333539 ps
T580 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_out_trans_nak.105785189 Sep 18 12:51:59 PM UTC 24 Sep 18 12:52:01 PM UTC 24 195010978 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_device_timeout.1217388579 Sep 18 12:51:35 PM UTC 24 Sep 18 12:52:02 PM UTC 24 3755698463 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_usb_ref_disable.594564572 Sep 18 12:52:00 PM UTC 24 Sep 18 12:52:02 PM UTC 24 157112546 ps
T608 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_pinflip.230726418 Sep 18 12:52:00 PM UTC 24 Sep 18 12:52:02 PM UTC 24 215422460 ps
T660 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_rand_bus_type.4170156686 Sep 18 12:52:00 PM UTC 24 Sep 18 12:52:03 PM UTC 24 260397703 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_phy_pins_sense.3310263260 Sep 18 12:52:01 PM UTC 24 Sep 18 12:52:03 PM UTC 24 94412245 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_resume_link_active.4222515369 Sep 18 12:51:24 PM UTC 24 Sep 18 12:52:04 PM UTC 24 20170342689 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_iso_retraction.2631666187 Sep 18 12:50:45 PM UTC 24 Sep 18 12:52:05 PM UTC 24 9932175041 ps
T586 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_received.3106053888 Sep 18 12:52:02 PM UTC 24 Sep 18 12:52:05 PM UTC 24 199200645 ps
T661 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_link_suspend.4024657129 Sep 18 12:51:49 PM UTC 24 Sep 18 12:52:05 PM UTC 24 5846745816 ps
T662 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_random_length_out_transaction.340989717 Sep 18 12:52:03 PM UTC 24 Sep 18 12:52:06 PM UTC 24 177872780 ps
T663 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_random_length_in_transaction.2140339601 Sep 18 12:52:03 PM UTC 24 Sep 18 12:52:06 PM UTC 24 207279961 ps
T664 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_sent.2607920867 Sep 18 12:52:03 PM UTC 24 Sep 18 12:52:06 PM UTC 24 220468161 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_rx_crc_err.1455788509 Sep 18 12:52:06 PM UTC 24 Sep 18 12:52:08 PM UTC 24 139536943 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_rx_full.1376951628 Sep 18 12:52:06 PM UTC 24 Sep 18 12:52:09 PM UTC 24 390770263 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_setup_priority_over_stall_response.2585672641 Sep 18 12:52:07 PM UTC 24 Sep 18 12:52:09 PM UTC 24 307402930 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_rx_pid_err.538985168 Sep 18 12:52:07 PM UTC 24 Sep 18 12:52:09 PM UTC 24 200086618 ps
T665 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_max_usb_traffic.1734788369 Sep 18 12:51:53 PM UTC 24 Sep 18 12:52:10 PM UTC 24 1876530579 ps
T666 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_max_non_iso_usb_traffic.2621241518 Sep 18 12:51:53 PM UTC 24 Sep 18 12:52:10 PM UTC 24 1966244995 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_setup_priority.3618841079 Sep 18 12:52:07 PM UTC 24 Sep 18 12:52:11 PM UTC 24 403706013 ps
T594 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_setup_stage.596822962 Sep 18 12:52:09 PM UTC 24 Sep 18 12:52:11 PM UTC 24 168860727 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_setup_trans_ignored.1173572782 Sep 18 12:52:11 PM UTC 24 Sep 18 12:52:13 PM UTC 24 201640774 ps
T584 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_stall_priority_over_nak.1499844211 Sep 18 12:52:11 PM UTC 24 Sep 18 12:52:13 PM UTC 24 182144579 ps
T667 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_min_inter_pkt_delay.447699658 Sep 18 12:51:55 PM UTC 24 Sep 18 12:52:14 PM UTC 24 2530202926 ps
T668 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_smoke.3182900564 Sep 18 12:52:11 PM UTC 24 Sep 18 12:52:14 PM UTC 24 260816261 ps
T669 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_out_stall.3473008956 Sep 18 12:52:52 PM UTC 24 Sep 18 12:52:55 PM UTC 24 171491973 ps
T670 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_timeout_missing_host_handshake.1004033507 Sep 18 12:51:36 PM UTC 24 Sep 18 12:52:14 PM UTC 24 1433239420 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_buffer.2143590267 Sep 18 12:52:02 PM UTC 24 Sep 18 12:52:54 PM UTC 24 17170169040 ps
T671 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_stall_trans.585220832 Sep 18 12:52:12 PM UTC 24 Sep 18 12:52:15 PM UTC 24 170313563 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/0.usbdev_device_address.2068590951 Sep 18 12:50:43 PM UTC 24 Sep 18 12:52:15 PM UTC 24 42562035906 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_link_resume.126958339 Sep 18 12:51:08 PM UTC 24 Sep 18 12:52:16 PM UTC 24 32923865346 ps
T672 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_stream_len_max.2407356313 Sep 18 12:52:12 PM UTC 24 Sep 18 12:52:18 PM UTC 24 969929931 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_sec_cm.1666093603 Sep 18 12:52:15 PM UTC 24 Sep 18 12:52:18 PM UTC 24 489078725 ps
T673 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_tx_rx_disruption.2995927329 Sep 18 12:52:14 PM UTC 24 Sep 18 12:52:18 PM UTC 24 560233949 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_resume.3047500090 Sep 18 12:51:32 PM UTC 24 Sep 18 12:52:19 PM UTC 24 24891392290 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_alert_test.2297346120 Sep 18 12:52:16 PM UTC 24 Sep 18 12:52:19 PM UTC 24 39189591 ps
T674 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_av_buffer.1928917234 Sep 18 12:52:18 PM UTC 24 Sep 18 12:52:21 PM UTC 24 183865977 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_av_empty.3180534476 Sep 18 12:52:18 PM UTC 24 Sep 18 12:52:21 PM UTC 24 200291624 ps
T675 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_av_overflow.1167743684 Sep 18 12:52:19 PM UTC 24 Sep 18 12:52:22 PM UTC 24 167069380 ps
T595 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_bitstuff_err.355492830 Sep 18 12:52:19 PM UTC 24 Sep 18 12:52:22 PM UTC 24 164364568 ps
T676 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_data_toggle_clear.2682152742 Sep 18 12:52:20 PM UTC 24 Sep 18 12:52:24 PM UTC 24 486875158 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_low_speed_traffic.1509603526 Sep 18 12:51:52 PM UTC 24 Sep 18 12:52:27 PM UTC 24 3767129560 ps
T618 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_data_toggle_restore.1441123650 Sep 18 12:52:20 PM UTC 24 Sep 18 12:52:27 PM UTC 24 1070592529 ps
T677 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_enable.1984870551 Sep 18 12:52:25 PM UTC 24 Sep 18 12:52:27 PM UTC 24 43447988 ps
T678 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_disconnected.3331768477 Sep 18 12:52:25 PM UTC 24 Sep 18 12:52:28 PM UTC 24 171983570 ps
T679 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_rand_bus_disconnects.1906703143 Sep 18 12:51:23 PM UTC 24 Sep 18 12:52:30 PM UTC 24 9326132794 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_disable_endpoint.1042900485 Sep 18 12:52:25 PM UTC 24 Sep 18 12:52:30 PM UTC 24 932041637 ps
T680 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_fifo_levels.860446652 Sep 18 12:52:27 PM UTC 24 Sep 18 12:52:30 PM UTC 24 181089168 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_device_address.791459162 Sep 18 12:51:02 PM UTC 24 Sep 18 12:52:30 PM UTC 24 39362435338 ps
T681 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_endpoint_access.338088784 Sep 18 12:52:25 PM UTC 24 Sep 18 12:52:30 PM UTC 24 722967889 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_disconnect.3663852040 Sep 18 12:52:16 PM UTC 24 Sep 18 12:52:31 PM UTC 24 10237107794 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_endpoint_types.3136622850 Sep 18 12:52:27 PM UTC 24 Sep 18 12:52:31 PM UTC 24 423769451 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_link_resume.3215333453 Sep 18 12:51:48 PM UTC 24 Sep 18 12:52:33 PM UTC 24 26196700811 ps
T682 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_fifo_rst.459836406 Sep 18 12:52:29 PM UTC 24 Sep 18 12:52:34 PM UTC 24 273790190 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_iso_retraction.2644932423 Sep 18 12:51:08 PM UTC 24 Sep 18 12:52:34 PM UTC 24 7363274517 ps
T683 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_in_stall.233627025 Sep 18 12:52:33 PM UTC 24 Sep 18 12:52:35 PM UTC 24 143030876 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_invalid_sync.4028403961 Sep 18 12:51:45 PM UTC 24 Sep 18 12:52:35 PM UTC 24 4580625068 ps
T684 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_in_iso.3317407276 Sep 18 12:52:33 PM UTC 24 Sep 18 12:52:36 PM UTC 24 199876771 ps
T685 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_in_trans.2887950624 Sep 18 12:52:35 PM UTC 24 Sep 18 12:52:38 PM UTC 24 189566261 ps
T686 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_link_in_err.3870018723 Sep 18 12:52:35 PM UTC 24 Sep 18 12:52:38 PM UTC 24 245166153 ps
T687 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_reset.8034313 Sep 18 12:52:17 PM UTC 24 Sep 18 12:52:39 PM UTC 24 13449308517 ps
T688 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_rand_bus_resets.2615729202 Sep 18 12:52:04 PM UTC 24 Sep 18 12:52:40 PM UTC 24 6928531280 ps
T689 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_max_length_out_transaction.915614794 Sep 18 12:52:40 PM UTC 24 Sep 18 12:52:42 PM UTC 24 181760345 ps
T690 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_max_length_in_transaction.3410814670 Sep 18 12:52:40 PM UTC 24 Sep 18 12:52:42 PM UTC 24 250134520 ps
T691 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_min_length_in_transaction.1409572280 Sep 18 12:52:46 PM UTC 24 Sep 18 12:52:49 PM UTC 24 234003629 ps
T692 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_timeout_missing_host_handshake.316726321 Sep 18 12:52:24 PM UTC 24 Sep 18 12:52:50 PM UTC 24 3627164281 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_stress_usb_traffic.3986781033 Sep 18 12:51:29 PM UTC 24 Sep 18 12:52:51 PM UTC 24 6592462118 ps
T693 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_min_length_out_transaction.2023406973 Sep 18 12:52:49 PM UTC 24 Sep 18 12:52:52 PM UTC 24 182665741 ps
T694 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_out_iso.2338613800 Sep 18 12:52:51 PM UTC 24 Sep 18 12:52:54 PM UTC 24 175989061 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_nak_trans.2228259130 Sep 18 12:52:51 PM UTC 24 Sep 18 12:52:54 PM UTC 24 270583836 ps
T695 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_device_timeout.2079548536 Sep 18 12:52:24 PM UTC 24 Sep 18 12:52:57 PM UTC 24 1244556626 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/2.usbdev_rand_bus_disconnects.2756835617 Sep 18 12:52:03 PM UTC 24 Sep 18 12:52:57 PM UTC 24 8910160083 ps
T696 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_pending_in_trans.2138303747 Sep 18 12:52:55 PM UTC 24 Sep 18 12:52:57 PM UTC 24 204785471 ps
T610 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_out_trans_nak.1747568751 Sep 18 12:52:55 PM UTC 24 Sep 18 12:52:57 PM UTC 24 250687057 ps
T697 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_phy_config_pinflip.3385083519 Sep 18 12:52:55 PM UTC 24 Sep 18 12:52:57 PM UTC 24 194802296 ps
T698 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_phy_config_rand_bus_type.823994941 Sep 18 12:52:56 PM UTC 24 Sep 18 12:52:59 PM UTC 24 250267295 ps
T699 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/4.usbdev_pkt_sent.1158451549 Sep 18 12:53:51 PM UTC 24 Sep 18 12:53:54 PM UTC 24 187019101 ps
T700 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_resume.192810971 Sep 18 12:52:17 PM UTC 24 Sep 18 12:53:00 PM UTC 24 24034156920 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_phy_pins_sense.3160754417 Sep 18 12:52:58 PM UTC 24 Sep 18 12:53:00 PM UTC 24 89384335 ps
T701 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_phy_config_usb_ref_disable.1511698068 Sep 18 12:52:58 PM UTC 24 Sep 18 12:53:01 PM UTC 24 196145146 ps
T702 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_pkt_received.2778552231 Sep 18 12:52:58 PM UTC 24 Sep 18 12:53:01 PM UTC 24 185040057 ps
T703 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_pkt_sent.89221294 Sep 18 12:52:58 PM UTC 24 Sep 18 12:53:01 PM UTC 24 240726414 ps
T704 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/1.usbdev_invalid_sync.630512101 Sep 18 12:51:07 PM UTC 24 Sep 18 12:53:01 PM UTC 24 3930246284 ps
T705 /workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/coverage/default/3.usbdev_random_length_in_transaction.2305537001 Sep 18 12:53:00 PM UTC 24 Sep 18 12:53:02 PM UTC 24 165473559 ps
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