Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::address_cg

Group : usbdev_env_pkg::usbdev_env_cov::address_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	14	0	14	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::address_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_address	7	0	7	100.00	100	1	1	0
cp_endp	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_address_X_endp	14	0	14	100.00	100	1	1	0

Summary for Variable cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_address

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	950	1			T93	124		T120	12		T121	5
range_16_to_126	152518	1			T1	1		T2	1		T28	19
fifteen	1337	1			T162	3		T120	9		T121	3
range_2_to_14	17677	1			T88	3		T33	2		T20	1
seven	1166	1			T260	1		T60	9		T594	1
one	3124	1			T120	7		T121	7		T317	6
zero	2229	1			T39	1		T120	7		T595	1

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Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_endp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

seven

14828

1

T32

11

T49

2

T74

11

three

13697

1

T29

3

T88

2

T49

2

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Summary for Cross cr_address_X_endp

Samples crossed: cp_address cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	0	14	100.00

Automatically Generated Cross Bins for cr_address_X_endp

Bins

cp_address	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	seven	25	1			T121	2		T317	1		T596	9
range_127	three	181	1			T93	124		T120	1		T596	9
range_16_to_126	seven	12876	1			T32	11		T49	2		T74	11
range_16_to_126	three	12333	1			T29	3		T88	1		T49	2
fifteen	seven	78	1			T120	1		T597	11		T598	1
fifteen	three	88	1			T162	3		T597	11		T201	1
range_2_to_14	seven	1687	1			T165	10		T599	2		T120	61
range_2_to_14	three	955	1			T88	1		T599	2		T120	50
seven	seven	771	1			T120	1		T317	1		T600	730
seven	three	18	1			T506	1		T601	1		T602	2
one	seven	76	1			T317	1		T603	1		T604	2
one	three	64	1			T605	17		T606	1		T607	28
zero	seven	86	1			T121	1		T122	1		T432	17
zero	three	76	1			T595	1		T121	2		T317	1