Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110282

1

T1

1

T2

1

T39

1

auto[1]

46040

1

T28

11

T29

16

T30

1

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	30071	1			T30	2		T20	1		T21	2
max_len_m1	789	1			T49	2		T51	1		T6	2
max_len_m2	740	1			T49	2		T51	2		T109	1
max_len_m3	782	1			T51	2		T5	2		T172	4
five	1192	1			T49	2		T51	3		T160	2
four	1143	1			T29	2		T51	1		T6	4
three	725	1			T51	3		T69	6		T283	7
one	828	1			T29	1		T54	2		T162	1
zero	11464	1			T39	1		T28	11		T29	9

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	24056	1			T30	1		T20	1		T21	1
max_len	auto[1]	6015	1			T30	1		T21	1		T4	1
max_len_m1	auto[0]	539	1			T49	1		T51	1		T6	1
max_len_m1	auto[1]	250	1			T49	1		T6	1		T174	1
max_len_m2	auto[0]	502	1			T49	1		T51	2		T109	1
max_len_m2	auto[1]	238	1			T49	1		T174	1		T99	1
max_len_m3	auto[0]	536	1			T51	2		T5	1		T172	2
max_len_m3	auto[1]	246	1			T5	1		T172	2		T68	2
five	auto[0]	594	1			T49	1		T51	3		T160	1
five	auto[1]	598	1			T49	1		T160	1		T68	2
four	auto[0]	606	1			T29	1		T51	1		T6	2
four	auto[1]	537	1			T29	1		T6	2		T172	1
three	auto[0]	355	1			T51	3		T69	2		T283	2
three	auto[1]	370	1			T69	4		T283	5		T608	1
one	auto[0]	395	1			T29	1		T54	1		T111	1
one	auto[1]	433	1			T54	1		T162	1		T111	1
zero	auto[0]	523	1			T39	1		T22	1		T25	1
zero	auto[1]	10941	1			T28	11		T29	9		T38	3