Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	0	96	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137729

1

T1

2

T2

2

T28

16

auto[1]

77405

1

T28

22

T29

28

T33

2

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	12544	1			T29	5		T36	16		T37	21
endpoints[0x1]	16541	1			T29	4		T49	4		T76	1
endpoints[0x2]	23583	1			T2	2		T28	38		T29	4
endpoints[0x3]	18352	1			T29	6		T49	4		T18	6
endpoints[0x4]	17349	1			T29	4		T49	4		T92	6
endpoints[0x5]	14744	1			T29	8		T49	4		T17	2
endpoints[0x6]	24174	1			T29	4		T49	4		T54	4
endpoints[0x7]	20396	1			T32	21		T49	4		T74	21
endpoints[0x8]	14453	1			T29	8		T33	4		T34	4
endpoints[0x9]	18722	1			T29	9		T35	17		T49	4
endpoints[0xa]	17136	1			T29	4		T49	4		T25	2
endpoints[0xb]	17140	1			T1	2		T29	4		T49	4

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	1482	1			T29	5		T32	2		T37	2
ack	103897	1			T1	1		T2	1		T28	19
data1	50477	1			T28	6		T29	16		T32	5
data0	59201	1			T1	1		T2	1		T28	13

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	0	96	100.00

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[0]	endpoints[0x0]	147	1			T37	2		T579	1		T129	1
nak	auto[0]	endpoints[0x1]	141	1			T60	1		T370	1		T371	1
nak	auto[0]	endpoints[0x2]	131	1			T580	1		T130	1		T609	1
nak	auto[0]	endpoints[0x3]	56	1			T610	1		T611	1		T138	1
nak	auto[0]	endpoints[0x4]	126	1			T121	12		T201	11		T432	5
nak	auto[0]	endpoints[0x5]	74	1			T143	1		T560	11		T612	11
nak	auto[0]	endpoints[0x6]	64	1			T613	8		T607	4		T602	13
nak	auto[0]	endpoints[0x7]	142	1			T32	2		T74	2		T148	1
nak	auto[0]	endpoints[0x8]	78	1			T122	6		T560	2		T183	13
nak	auto[0]	endpoints[0x9]	99	1			T281	1		T614	1		T615	1
nak	auto[0]	endpoints[0xa]	88	1			T154	1		T387	1		T317	16
nak	auto[0]	endpoints[0xb]	133	1			T157	1		T121	11		T122	2
nak	auto[1]	endpoints[0x0]	17	1			T111	1		T616	1		T617	1
nak	auto[1]	endpoints[0x1]	19	1			T29	1		T116	1		T618	2
nak	auto[1]	endpoints[0x2]	10	1			T618	1		T616	1		T619	1
nak	auto[1]	endpoints[0x3]	16	1			T620	2		T619	2		T621	2
nak	auto[1]	endpoints[0x4]	17	1			T29	2		T116	3		T619	1
nak	auto[1]	endpoints[0x5]	12	1			T116	1		T617	1		T622	1
nak	auto[1]	endpoints[0x6]	11	1			T116	2		T620	1		T623	1
nak	auto[1]	endpoints[0x7]	10	1			T116	1		T618	1		T620	1
nak	auto[1]	endpoints[0x8]	24	1			T621	1		T624	1		T625	3
nak	auto[1]	endpoints[0x9]	29	1			T29	1		T616	1		T617	3
nak	auto[1]	endpoints[0xa]	19	1			T29	1		T111	1		T622	1
nak	auto[1]	endpoints[0xb]	19	1			T618	1		T626	1		T623	1
ack	auto[0]	endpoints[0x0]	3084	1			T29	2		T36	8		T37	8
ack	auto[0]	endpoints[0x1]	4622	1			T29	1		T49	1		T60	7
ack	auto[0]	endpoints[0x2]	7942	1			T2	1		T28	8		T29	1
ack	auto[0]	endpoints[0x3]	5603	1			T29	2		T49	1		T18	2
ack	auto[0]	endpoints[0x4]	5212	1			T49	1		T92	2		T163	1
ack	auto[0]	endpoints[0x5]	4286	1			T29	2		T49	1		T17	1
ack	auto[0]	endpoints[0x6]	8211	1			T29	1		T49	1		T54	1
ack	auto[0]	endpoints[0x7]	6829	1			T32	8		T49	1		T74	8
ack	auto[0]	endpoints[0x8]	3693	1			T29	2		T33	1		T34	1
ack	auto[0]	endpoints[0x9]	5833	1			T29	3		T35	8		T49	1
ack	auto[0]	endpoints[0xa]	5386	1			T29	1		T49	1		T25	1
ack	auto[0]	endpoints[0xb]	5144	1			T1	1		T29	1		T49	1
ack	auto[1]	endpoints[0x0]	2830	1			T49	1		T160	1		T69	24
ack	auto[1]	endpoints[0x1]	3294	1			T49	1		T160	1		T5	8
ack	auto[1]	endpoints[0x2]	3541	1			T28	11		T29	1		T38	2
ack	auto[1]	endpoints[0x3]	3294	1			T29	1		T49	1		T18	1
ack	auto[1]	endpoints[0x4]	3071	1			T49	1		T92	1		T163	1
ack	auto[1]	endpoints[0x5]	2841	1			T29	2		T49	1		T160	1
ack	auto[1]	endpoints[0x6]	3653	1			T49	1		T54	1		T164	1
ack	auto[1]	endpoints[0x7]	3058	1			T49	1		T165	4		T160	1
ack	auto[1]	endpoints[0x8]	3242	1			T29	2		T34	1		T49	1
ack	auto[1]	endpoints[0x9]	3199	1			T49	1		T21	1		T22	1
ack	auto[1]	endpoints[0xa]	2938	1			T49	1		T53	1		T160	1
ack	auto[1]	endpoints[0xb]	3091	1			T29	1		T49	1		T89	1
data1	auto[0]	endpoints[0x0]	1320	1			T29	1		T37	5		T69	5
data1	auto[0]	endpoints[0x1]	2025	1			T29	1		T60	4		T264	3
data1	auto[0]	endpoints[0x2]	3646	1			T28	2		T29	1		T5	4
data1	auto[0]	endpoints[0x3]	2512	1			T29	1		T18	1		T162	1
data1	auto[0]	endpoints[0x4]	2308	1			T92	1		T111	1		T172	2
data1	auto[0]	endpoints[0x5]	1898	1			T29	1		T5	2		T172	2
data1	auto[0]	endpoints[0x6]	3705	1			T29	1		T4	17		T172	2
data1	auto[0]	endpoints[0x7]	3119	1			T32	5		T74	5		T6	19
data1	auto[0]	endpoints[0x8]	1523	1			T29	1		T166	1		T5	4
data1	auto[0]	endpoints[0x9]	2630	1			T29	1		T166	2		T5	3
data1	auto[0]	endpoints[0xa]	2386	1			T29	1		T53	1		T5	1
data1	auto[0]	endpoints[0xb]	2294	1			T157	1		T89	1		T244	3
data1	auto[1]	endpoints[0x0]	1568	1			T29	1		T111	1		T69	12
data1	auto[1]	endpoints[0x1]	1811	1			T5	4		T69	5		T167	1
data1	auto[1]	endpoints[0x2]	1975	1			T28	4		T38	2		T5	4
data1	auto[1]	endpoints[0x3]	1808	1			T29	1		T18	1		T162	1
data1	auto[1]	endpoints[0x4]	1724	1			T29	1		T92	1		T188	3
data1	auto[1]	endpoints[0x5]	1566	1			T29	1		T5	6		T172	3
data1	auto[1]	endpoints[0x6]	2057	1			T29	1		T4	17		T172	2
data1	auto[1]	endpoints[0x7]	1697	1			T165	5		T6	34		T68	6
data1	auto[1]	endpoints[0x8]	1788	1			T166	1		T5	4		T172	2
data1	auto[1]	endpoints[0x9]	1746	1			T29	1		T166	2		T5	5
data1	auto[1]	endpoints[0xa]	1640	1			T53	1		T5	6		T172	2
data1	auto[1]	endpoints[0xb]	1731	1			T29	1		T89	1		T244	2
data0	auto[0]	endpoints[0x0]	2226	1			T29	1		T36	8		T37	6
data0	auto[0]	endpoints[0x1]	3060	1			T49	1		T76	1		T60	4
data0	auto[0]	endpoints[0x2]	4717	1			T2	1		T28	6		T30	1
data0	auto[0]	endpoints[0x3]	3454	1			T29	1		T49	1		T18	1
data0	auto[0]	endpoints[0x4]	3433	1			T49	1		T92	1		T163	1
data0	auto[0]	endpoints[0x5]	2684	1			T29	1		T49	1		T17	1
data0	auto[0]	endpoints[0x6]	4807	1			T49	1		T54	1		T164	1
data0	auto[0]	endpoints[0x7]	4070	1			T32	6		T49	1		T74	6
data0	auto[0]	endpoints[0x8]	2574	1			T29	1		T33	1		T34	1
data0	auto[0]	endpoints[0x9]	3638	1			T29	2		T35	9		T49	1
data0	auto[0]	endpoints[0xa]	3292	1			T49	1		T25	1		T53	1
data0	auto[0]	endpoints[0xb]	3257	1			T1	1		T29	1		T49	1
data0	auto[1]	endpoints[0x0]	1346	1			T49	1		T160	1		T627	1
data0	auto[1]	endpoints[0x1]	1562	1			T29	1		T49	1		T160	1
data0	auto[1]	endpoints[0x2]	1611	1			T28	7		T29	1		T38	1
data0	auto[1]	endpoints[0x3]	1602	1			T49	1		T160	1		T69	9
data0	auto[1]	endpoints[0x4]	1450	1			T29	1		T49	1		T163	1
data0	auto[1]	endpoints[0x5]	1381	1			T29	1		T49	1		T160	1
data0	auto[1]	endpoints[0x6]	1658	1			T29	1		T49	1		T54	1
data0	auto[1]	endpoints[0x7]	1461	1			T49	1		T111	1		T165	5
data0	auto[1]	endpoints[0x8]	1527	1			T29	2		T33	1		T34	1
data0	auto[1]	endpoints[0x9]	1541	1			T29	1		T49	1		T21	1
data0	auto[1]	endpoints[0xa]	1383	1			T29	1		T49	1		T111	1
data0	auto[1]	endpoints[0xb]	1467	1			T49	1		T244	4		T160	1