Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv


Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_in_enable 2 0 2 100.00 100 1 1 2
cp_in_iso 2 0 2 100.00 100 1 1 2
cp_in_stall 2 0 2 100.00 100 1 1 2
cp_pid 2 0 2 100.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pid_x_epconfig 16 0 16 100.00 100 1 1 0


Summary for Variable cp_in_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7853 1 T88 5 T260 2 T117 3
auto[1] 54165 1 T28 11 T29 16 T30 1


Summary for Variable cp_in_iso

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_iso

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 53831 1 T28 11 T29 16 T31 1
auto[1] 8187 1 T30 1 T117 3 T107 1


Summary for Variable cp_in_stall

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_stall

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 56294 1 T28 11 T29 16 T30 1
auto[1] 5724 1 T31 1 T109 1 T117 3


Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_pid

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] 4318 1 T88 2 T260 2 T430 2
pkt_types[PidTypeInToken] 57700 1 T28 11 T29 16 T30 1


Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins
cp_pidcp_in_enablecp_in_isocp_in_stallCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] auto[0] auto[0] auto[0] 1307 1 T88 2 T168 2 T120 46
ignore_pre[PidTypePre] auto[0] auto[0] auto[1] 676 1 T122 3 T317 7 T201 11
ignore_pre[PidTypePre] auto[0] auto[1] auto[0] 100 1 T168 2 T217 2 T434 2
ignore_pre[PidTypePre] auto[0] auto[1] auto[1] 14 1 T452 1 T436 1 T453 1
ignore_pre[PidTypePre] auto[1] auto[0] auto[0] 1372 1 T260 2 T430 1 T168 2
ignore_pre[PidTypePre] auto[1] auto[0] auto[1] 732 1 T430 1 T120 22 T121 28
ignore_pre[PidTypePre] auto[1] auto[1] auto[0] 103 1 T168 2 T217 3 T434 2
ignore_pre[PidTypePre] auto[1] auto[1] auto[1] 14 1 T532 1 T491 1 T488 1
pkt_types[PidTypeInToken] auto[0] auto[0] auto[0] 3677 1 T88 3 T260 2 T120 116
pkt_types[PidTypeInToken] auto[0] auto[0] auto[1] 1987 1 T117 1 T121 3 T122 18
pkt_types[PidTypeInToken] auto[0] auto[1] auto[0] 48 1 T469 1 T446 1 T525 1
pkt_types[PidTypeInToken] auto[0] auto[1] auto[1] 44 1 T117 2 T469 2 T512 3
pkt_types[PidTypeInToken] auto[1] auto[0] auto[0] 41876 1 T28 11 T29 16 T88 1
pkt_types[PidTypeInToken] auto[1] auto[0] auto[1] 2204 1 T31 1 T109 1 T110 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[0] 7811 1 T30 1 T117 1 T107 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[1] 53 1 T469 1 T471 1 T525 1

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