Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.55	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	192	3	189	98.44

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_out_enable	2	0	2	100.00	100	1	1	2
cp_out_iso	2	0	2	100.00	100	1	1	2
cp_out_stall	2	0	2	100.00	100	1	1	2
cp_pid	3	0	3	100.00	100	1	1	0
cp_rxenable_out	2	0	2	100.00	100	1	1	2
cp_rxenable_setup	2	0	2	100.00	100	1	1	2
cp_set_nak_out	2	0	2	100.00	100	1	1	2

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	192	3	189	98.44	100	1	1	0

Summary for Variable cp_out_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_out_enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15423

1

T39

1

T87

2

T88

15

auto[1]

82240

1

T1

1

T2

1

T28

8

---

Summary for Variable cp_out_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_out_iso

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95205

1

T1

1

T2

1

T39

1

auto[1]

2458

1

T87

1

T205

1

T117

7

---

Summary for Variable cp_out_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_out_stall

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86911

1

T1

1

T2

1

T39

1

auto[1]

10752

1

T87

1

T88

2

T75

1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
ignore_pre[PidTypePre]	8774	1			T260	1		T117	2		T430	2
pkt_types[PidTypeSetupToken]	19714	1			T87	1		T88	6		T35	9
pkt_types[PidTypeOutToken]	69088	1			T1	1		T2	1		T39	1

---

Summary for Variable cp_rxenable_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxenable_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16878

1

T39

1

T87

1

T88

11

auto[1]

80785

1

T1

1

T2

1

T28

8

---

Summary for Variable cp_rxenable_setup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxenable_setup

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

66118

1

T1

1

T2

1

T39

1

auto[1]

31545

1

T87

2

T88

3

T35

9

---

Summary for Variable cp_set_nak_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_set_nak_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97010

1

T1

1

T2

1

T39

1

auto[1]

653

1

T87

1

T157

2

T209

1

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_out_enable cp_rxenable_setup cp_rxenable_out cp_set_nak_out cp_out_iso cp_out_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	192	3	189	98.44	3

Automatically Generated Cross Bins for cr_pid_x_epconfig

Uncovered bins

cp_pid	cp_out_enable	cp_rxenable_setup	cp_rxenable_out	cp_set_nak_out	cp_out_iso	cp_out_stall	COUNT	AT LEAST	NUMBER	STATUS
[ignore_pre[PidTypePre]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1
[ignore_pre[PidTypePre]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[pkt_types[PidTypeSetupToken]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_pid

cp_out_enable

cp_rxenable_setup

cp_rxenable_out

cp_set_nak_out

cp_out_iso

cp_out_stall

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

643

1

T168

4

T120

14

T122

5

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

466

1

T431

1

T432

8

T433

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

60

1

T117

1

T434

3

T435

3

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T436

1

T437

2

T438

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

12

1

T436

1

T439

1

T440

2

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T441

1

T442

1

T437

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

3

1

T443

1

T444

1

T445

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T446

1

T447

1

T448

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

345

1

T430

1

T120

36

T432

10

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

441

1

T120

20

T122

9

T317

29

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

2

1

T449

1

T450

1

-

-

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T451

1

T452

1

T453

2

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

3

1

T454

1

T455

1

T456

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2

1

T457

1

T442

1

-

-

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1

1

T458

1

-

-

-

-

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T459

1

T460

1

T461

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

626

1

T120

19

T217

4

T431

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

409

1

T430

1

T120

16

T121

19

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

60

1

T462

1

T435

2

T463

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

2

1

T464

1

T465

1

-

-

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

8

1

T466

1

T467

1

T468

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T119

1

T469

1

T470

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T471

1

T472

1

T473

2

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

433

1

T260

1

T119

1

T120

10

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

477

1

T431

3

T122

9

T317

11

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

3

1

T458

1

T474

1

T442

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

3

1

T475

1

T468

1

T476

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

4

1

T119

1

T477

1

T478

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T446

1

T479

1

T472

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T480

1

T481

1

T482

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T483

1

T459

1

T484

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

580

1

T121

12

T317

10

T201

17

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

338

1

T121

24

T432

10

T183

12

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

6

1

T485

1

T486

1

T487

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

3

1

T488

1

T489

1

T490

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

6

1

T491

1

T440

1

T489

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T492

1

T493

1

T494

2

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

3

1

T495

1

T496

1

T486

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

3

1

T486

1

T448

1

T497

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

696

1

T168

3

T217

3

T121

16

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

406

1

T120

12

T317

26

T432

5

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

75

1

T168

4

T434

2

T498

2

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T117

1

T499

1

T500

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

4

1

T440

1

T488

1

T501

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T119

1

T502

1

T503

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

4

1

T504

1

T496

1

T505

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

924

1

T120

17

T121

26

T122

9

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

30

1

T183

2

T506

2

T507

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

3

1

T469

1

T508

1

T487

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

2

1

T509

1

T510

1

-

-

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

3

1

T470

1

T441

1

T511

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T512

1

T513

1

T438

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

5

1

T509

1

T514

1

T473

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

4

1

T492

1

T495

1

T499

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1462

1

T168

7

T120

53

T217

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

37

1

T121

4

T201

1

T515

2

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

87

1

T217

2

T434

3

T462

5

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T503

1

T516

1

-

-

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1

1

T471

1

-

-

-

-

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T517

1

T439

3

T518

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

2

1

T519

1

T520

1

-

-

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T468

1

T464

1

-

-

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

859

1

T88

4

T430

3

T120

27

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

637

1

T431

2

T432

23

T521

2

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

8

1

T469

1

T522

1

T447

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T469

1

T457

1

T523

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

9

1

T524

1

T517

1

T458

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T525

1

T526

1

T527

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

7

1

T443

2

T444

2

T465

2

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T499

1

T528

1

T457

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

446

1

T120

49

T432

4

T433

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

619

1

T88

1

T260

2

T120

28

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

9

1

T529

1

T530

1

T531

2

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T451

1

T495

1

T481

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

7

1

T532

1

T470

2

T504

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

3

1

T451

1

T533

1

T519

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

9

1

T524

1

T534

1

T535

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T499

1

T496

1

T460

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

833

1

T260

1

T430

3

T120

32

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

586

1

T430

1

T120

28

T121

39

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

7

1

T484

2

T477

1

T536

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

3

1

T537

1

T464

1

T538

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

4

1

T441

1

T456

1

T539

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

9

1

T469

1

T524

1

T480

3

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1

1

T540

1

-

-

-

-

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T471

1

T529

1

T491

2

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

619

1

T88

1

T260

2

T120

27

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

745

1

T260

4

T431

4

T122

9

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

4

1

T87

1

T541

1

T503

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T493

1

T533

1

T509

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

4

1

T522

1

T480

1

T530

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T480

1

T518

2

T513

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

9

1

T453

1

T514

1

T542

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T543

1

T518

1

T511

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

918

1

T214

1

T215

1

T216

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

514

1

T121

47

T432

22

T183

24

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

6

1

T543

1

T544

1

T487

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T545

1

T489

1

T546

2

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

3

1

T547

1

T548

1

T549

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T493

1

T460

1

T528

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

4

1

T534

1

T495

1

T550

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T517

1

T542

2

T448

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

853

1

T121

24

T122

18

T317

75

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

577

1

T120

25

T317

39

T432

12

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

3

1

T494

1

T551

1

T449

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T552

1

T553

1

T554

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1

1

T555

1

-

-

-

-

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T471

1

T556

1

T502

2

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T504

1

T557

1

T538

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T558

1

T559

1

-

-

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1727

1

T91

1

T57

8

T169

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

38

1

T121

1

T560

1

T183

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

6

1

T534

2

T561

1

T530

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T562

1

T563

1

T439

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

5

1

T526

2

T479

1

T441

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

13

1

T458

1

T477

1

T546

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

8

1

T537

1

T553

2

T556

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T492

1

T508

1

T536

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

9026

1

T35

9

T36

8

T18

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

57

1

T109

1

T175

1

T189

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

391

1

T108

6

T179

10

T217

14

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

4

1

T508

1

T452

1

T472

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T517

1

T527

1

T448

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T458

1

T545

1

T493

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T117

2

T485

1

T460

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1146

1

T39

1

T88

6

T51

139

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

687

1

T88

1

T432

25

T433

5

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

7

1

T117

1

T564

1

T565

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T452

1

T541

2

T566

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

6

1

T495

1

T518

1

T565

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T527

1

T479

1

T519

2

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

6

1

T567

1

T568

1

T569

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T446

2

T452

1

T570

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

533

1

T120

53

T432

7

T433

2

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

622

1

T120

31

T122

11

T571

2

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

5

1

T529

1

T486

1

T558

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T453

1

T442

1

-

-

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

4

1

T504

1

T495

1

T496

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T485

1

T572

1

T460

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T458

1

T459

1

T484

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T573

1

T439

1

T493

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

821

1

T81

8

T430

3

T120

30

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

568

1

T120

26

T121

28

T317

22

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

2

1

T563

1

T528

1

-

-

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T574

1

T575

1

T490

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

6

1

T525

1

T482

1

T576

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T87

1

T469

1

T525

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

2

1

T451

1

T548

1

-

-

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T562

1

T552

1

T542

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

620

1

T88

2

T260

3

T120

23

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

714

1

T260

2

T431

3

T122

7

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

7

1

T474

1

T577

1

T460

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T492

1

T475

1

T533

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

5

1

T480

1

T466

1

T530

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T529

1

T518

2

T556

2

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T563

1

T489

1

T448

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T578

1

T486

1

T455

2

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1006

1

T579

1

T281

1

T580

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

543

1

T121

63

T432

16

T183

14

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

6

1

T451

1

T526

1

T564

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T488

1

T490

1

T511

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

57

1

T157

1

T154

1

T148

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

2

1

T460

1

T581

1

-

-

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

6

1

T488

1

T499

1

T496

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T119

1

T459

1

T484

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

49883

1

T1

1

T2

1

T28

8

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

705

1

T75

1

T582

1

T282

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

985

1

T205

1

T206

1

T108

15

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T117

1

T471

1

T470

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

54

1

T157

1

T154

1

T148

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

57

1

T209

1

T583

1

T584

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

6

1

T117

1

T527

1

T504

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T446

2

T514

1

T542

3

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1335

1

T120

36

T121

20

T122

20

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

46

1

T183

2

T506

2

T451

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

11

1

T529

1

T453

1

T530

4

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

10

1

T522

2

T563

1

T459

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

4

1

T441

1

T511

1

T502

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T453

1

T477

2

T475

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

2

1

T562

1

T483

1

-

-

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

4

1

T499

1

T489

1

T454

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

8049

1

T18

1

T53

1

T89

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

56

1

T109

1

T175

1

T189

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

357

1

T108

8

T179

14

T217

10

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T527

1

T557

1

T549

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

6

1

T471

1

T472

1

T440

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T471

1

T439

1

T499

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

6

1

T562

1

T451

1

T458

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T451

2

T460

1

T468

1