Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

Group : usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.46	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	54	1	53	98.15

Variables for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_avout	3	0	3	100.00	100	1	1	0
cp_avsetup	3	0	3	100.00	100	1	1	0
cp_pid	2	0	2	100.00	100	1	1	0
cp_rx	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_fifo_X_pid	54	1	53	98.15	100	1	1	0

Summary for Variable cp_avout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avout

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	20444	1			T60	1		T4	34		T5	56
solo	73240	1			T1	1		T2	1		T39	1
empty	5042	1			T32	1		T35	8		T36	8

---

Summary for Variable cp_avsetup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avsetup

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	20477	1			T35	1		T57	1		T4	34
solo	32707	1			T87	2		T88	14		T35	8
empty	45599	1			T1	1		T2	1		T39	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

out

75226

1

T1

1

T2

1

T39

1

setup

23699

1

T87

2

T88

6

T35

9

---

Summary for Variable cp_rx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rx

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	54	1			T35	1		T207	1		T208	1
solo	159	1			T32	1		T35	1		T36	1
empty	82531	1			T1	1		T2	1		T39	1

---

Summary for Cross cr_fifo_X_pid

Samples crossed: cp_avsetup cp_avout cp_rx cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	54	1	53	98.15	1

Automatically Generated Cross Bins for cr_fifo_X_pid

Uncovered bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	NUMBER	STATUS
[solo]	[full]	[solo]	[out]	0	1	1

Covered bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	full	full	out	1	1			T332	1		-	-		-	-
full	full	full	setup	4	1			T207	1		T208	1		T333	1
full	full	solo	out	1	1			T334	1		-	-		-	-
full	full	solo	setup	3	1			T335	1		T336	1		T337	1
full	full	empty	out	15710	1			T4	34		T5	32		T6	30
full	full	empty	setup	4665	1			T5	24		T6	23		T172	9
full	solo	full	out	2	1			T210	1		T338	1		-	-
full	solo	full	setup	3	1			T35	1		T339	1		T340	1
full	solo	solo	out	8	1			T341	1		T342	1		T343	1
full	solo	solo	setup	5	1			T344	1		T345	1		T346	1
full	solo	empty	out	2	1			T347	1		T348	1		-	-
full	solo	empty	setup	3	1			T349	1		T350	1		T351	1
full	empty	full	out	5	1			T212	1		T352	1		T353	1
full	empty	full	setup	4	1			T354	1		T355	1		T356	1
full	empty	solo	out	5	1			T357	1		T358	1		T359	1
full	empty	solo	setup	7	1			T61	1		T360	1		T361	1
full	empty	empty	out	1	1			T362	1		-	-		-	-
full	empty	empty	setup	8	1			T58	1		T363	1		T364	1
solo	full	full	out	1	1			T365	1		-	-		-	-
solo	full	full	setup	4	1			T366	1		T367	1		T368	1
solo	full	solo	setup	1	1			T369	1		-	-		-	-
solo	full	empty	out	8	1			T60	1		T370	1		T371	1
solo	full	empty	setup	6	1			T372	1		T373	1		T374	1
solo	solo	full	out	3	1			T375	1		T376	1		T377	1
solo	solo	full	setup	2	1			T378	1		T379	1		-	-
solo	solo	solo	out	6	1			T60	1		T370	1		T371	1
solo	solo	solo	setup	8	1			T60	1		T370	1		T371	1
solo	solo	empty	out	8236	1			T88	8		T260	5		T109	1
solo	solo	empty	setup	8178	1			T87	2		T88	6		T260	5
solo	empty	full	out	2	1			T380	1		T381	1		-	-
solo	empty	full	setup	5	1			T382	1		T383	1		T384	1
solo	empty	solo	out	5	1			T211	1		T385	1		T386	1
solo	empty	solo	setup	75	1			T35	1		T36	1		T207	1
solo	empty	empty	out	3	1			T387	1		T388	1		T389	1
solo	empty	empty	setup	2084	1			T35	1		T36	1		T18	1
empty	full	full	out	3	1			T390	1		T391	1		T392	1
empty	full	full	setup	3	1			T393	1		T394	1		T395	1
empty	full	solo	out	1	1			T396	1		-	-		-	-
empty	full	solo	setup	3	1			T397	1		T398	1		T399	1
empty	full	empty	out	4	1			T400	1		T401	1		T402	1
empty	full	empty	setup	2	1			T403	1		T404	1		-	-
empty	solo	full	out	3	1			T405	1		T406	1		T407	1
empty	solo	full	setup	4	1			T408	1		T409	1		T410	1
empty	solo	solo	out	2	1			T411	1		T412	1		-	-
empty	solo	solo	setup	3	1			T413	1		T414	1		T415	1
empty	solo	empty	out	43163	1			T1	1		T2	1		T39	1
empty	solo	empty	setup	4	1			T416	1		T417	1		T418	1
empty	empty	full	out	3	1			T419	1		T420	1		T421	1
empty	empty	full	setup	2	1			T422	1		T423	1		-	-
empty	empty	solo	out	3	1			T424	1		T425	1		T426	1
empty	empty	solo	setup	3	1			T427	1		T428	1		T429	1
empty	empty	empty	out	259	1			T32	1		T37	1		T74	1
empty	empty	empty	setup	152	1			T214	1		T166	1		T215	1