Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	171408	1			T1	6		T2	4		T3	7
all_pins[1]	171408	1			T1	6		T2	4		T3	7
all_pins[2]	171408	1			T1	6		T2	4		T3	7
all_pins[3]	171408	1			T1	6		T2	4		T3	7
all_pins[4]	171408	1			T1	6		T2	4		T3	7
all_pins[5]	171408	1			T1	6		T2	4		T3	7
all_pins[6]	171408	1			T1	6		T2	4		T3	7
all_pins[7]	171408	1			T1	6		T2	4		T3	7
all_pins[8]	171408	1			T1	6		T2	4		T3	7
all_pins[9]	171408	1			T1	6		T2	4		T3	7
all_pins[10]	171408	1			T1	6		T2	4		T3	7
all_pins[11]	171408	1			T1	6		T2	4		T3	7
all_pins[12]	171408	1			T1	6		T2	4		T3	7
all_pins[13]	171408	1			T1	6		T2	4		T3	7
all_pins[14]	171408	1			T1	6		T2	4		T3	7
all_pins[15]	171408	1			T1	6		T2	4		T3	7
all_pins[16]	171408	1			T1	6		T2	4		T3	7
all_pins[17]	171408	1			T1	6		T2	4		T3	7

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5482944	1			T1	191		T2	128		T3	222
values[0x1]	2112	1			T1	1		T3	2		T39	1
transitions[0x0=>0x1]	1893	1			T1	1		T3	2		T39	1
transitions[0x1=>0x0]	1893	1			T1	1		T3	2		T39	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	171307	1			T1	6		T2	4		T3	7
all_pins[0]	values[0x1]	101	1			T52	1		T585	1		T586	1
all_pins[0]	transitions[0x0=>0x1]	89	1			T52	1		T585	1		T586	1
all_pins[0]	transitions[0x1=>0x0]	862	1			T34	1		T49	12		T54	1
all_pins[1]	values[0x0]	170534	1			T1	6		T2	4		T3	7
all_pins[1]	values[0x1]	874	1			T34	1		T49	12		T54	1
all_pins[1]	transitions[0x0=>0x1]	864	1			T34	1		T49	12		T54	1
all_pins[1]	transitions[0x1=>0x0]	105	1			T41	1		T66	1		T67	1
all_pins[2]	values[0x0]	171293	1			T1	6		T2	4		T3	7
all_pins[2]	values[0x1]	115	1			T41	1		T66	1		T67	1
all_pins[2]	transitions[0x0=>0x1]	97	1			T41	1		T66	1		T67	1
all_pins[2]	transitions[0x1=>0x0]	38	1			T51	1		T234	1		T236	3
all_pins[3]	values[0x0]	171352	1			T1	6		T2	4		T3	7
all_pins[3]	values[0x1]	56	1			T51	1		T234	1		T236	3
all_pins[3]	transitions[0x0=>0x1]	46	1			T51	1		T234	1		T236	3
all_pins[3]	transitions[0x1=>0x0]	42	1			T50	1		T236	1		T238	3
all_pins[4]	values[0x0]	171356	1			T1	6		T2	4		T3	7
all_pins[4]	values[0x1]	52	1			T50	1		T236	1		T238	3
all_pins[4]	transitions[0x0=>0x1]	32	1			T50	1		T236	1		T238	3
all_pins[4]	transitions[0x1=>0x0]	45	1			T234	1		T236	1		T325	4
all_pins[5]	values[0x0]	171343	1			T1	6		T2	4		T3	7
all_pins[5]	values[0x1]	65	1			T234	1		T236	1		T325	4
all_pins[5]	transitions[0x0=>0x1]	56	1			T234	1		T325	4		T326	5
all_pins[5]	transitions[0x1=>0x0]	80	1			T71	1		T72	1		T73	1
all_pins[6]	values[0x0]	171319	1			T1	6		T2	4		T3	7
all_pins[6]	values[0x1]	89	1			T71	1		T72	1		T73	1
all_pins[6]	transitions[0x0=>0x1]	80	1			T71	1		T72	1		T73	1
all_pins[6]	transitions[0x1=>0x0]	44	1			T1	1		T55	1		T56	1
all_pins[7]	values[0x0]	171355	1			T1	5		T2	4		T3	7
all_pins[7]	values[0x1]	53	1			T1	1		T55	1		T56	1
all_pins[7]	transitions[0x0=>0x1]	38	1			T1	1		T55	1		T56	1
all_pins[7]	transitions[0x1=>0x0]	59	1			T57	1		T58	1		T61	1
all_pins[8]	values[0x0]	171334	1			T1	6		T2	4		T3	7
all_pins[8]	values[0x1]	74	1			T57	1		T58	1		T61	1
all_pins[8]	transitions[0x0=>0x1]	61	1			T57	1		T58	1		T61	1
all_pins[8]	transitions[0x1=>0x0]	66	1			T3	2		T64	2		T65	2
all_pins[9]	values[0x0]	171329	1			T1	6		T2	4		T3	5
all_pins[9]	values[0x1]	79	1			T3	2		T64	2		T65	2
all_pins[9]	transitions[0x0=>0x1]	63	1			T3	2		T64	2		T65	2
all_pins[9]	transitions[0x1=>0x0]	54	1			T234	1		T236	1		T325	3
all_pins[10]	values[0x0]	171338	1			T1	6		T2	4		T3	7
all_pins[10]	values[0x1]	70	1			T234	1		T236	1		T239	1
all_pins[10]	transitions[0x0=>0x1]	54	1			T234	1		T236	1		T239	1
all_pins[10]	transitions[0x1=>0x0]	89	1			T76	1		T77	1		T78	1
all_pins[11]	values[0x0]	171303	1			T1	6		T2	4		T3	7
all_pins[11]	values[0x1]	105	1			T76	1		T77	1		T78	1
all_pins[11]	transitions[0x0=>0x1]	94	1			T76	1		T77	1		T78	1
all_pins[11]	transitions[0x1=>0x0]	45	1			T79	1		T80	1		T82	1
all_pins[12]	values[0x0]	171352	1			T1	6		T2	4		T3	7
all_pins[12]	values[0x1]	56	1			T79	1		T80	1		T82	1
all_pins[12]	transitions[0x0=>0x1]	50	1			T79	1		T80	1		T82	1
all_pins[12]	transitions[0x1=>0x0]	89	1			T39	1		T85	1		T86	1
all_pins[13]	values[0x0]	171313	1			T1	6		T2	4		T3	7
all_pins[13]	values[0x1]	95	1			T39	1		T85	1		T86	1
all_pins[13]	transitions[0x0=>0x1]	81	1			T39	1		T85	1		T86	1
all_pins[13]	transitions[0x1=>0x0]	46	1			T234	1		T236	1		T239	3
all_pins[14]	values[0x0]	171348	1			T1	6		T2	4		T3	7
all_pins[14]	values[0x1]	60	1			T234	2		T236	2		T239	3
all_pins[14]	transitions[0x0=>0x1]	43	1			T234	2		T236	1		T239	3
all_pins[14]	transitions[0x1=>0x0]	40	1			T234	1		T236	2		T325	2
all_pins[15]	values[0x0]	171351	1			T1	6		T2	4		T3	7
all_pins[15]	values[0x1]	57	1			T234	1		T236	3		T325	2
all_pins[15]	transitions[0x0=>0x1]	42	1			T234	1		T236	2		T325	2
all_pins[15]	transitions[0x1=>0x0]	45	1			T32	4		T37	4		T74	4
all_pins[16]	values[0x0]	171348	1			T1	6		T2	4		T3	7
all_pins[16]	values[0x1]	60	1			T32	4		T37	4		T74	4
all_pins[16]	transitions[0x0=>0x1]	52	1			T32	4		T37	4		T74	4
all_pins[16]	transitions[0x1=>0x0]	43	1			T62	1		T236	1		T239	1
all_pins[17]	values[0x0]	171357	1			T1	6		T2	4		T3	7
all_pins[17]	values[0x1]	51	1			T62	1		T236	1		T239	2
all_pins[17]	transitions[0x0=>0x1]	51	1			T62	1		T236	1		T239	2