Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4549	1			T117	1		T120	116		T121	92
invalid_ep[0xd]	4485	1			T87	1		T117	1		T81	5
invalid_ep[0xe]	4620	1			T87	1		T117	2		T81	3
invalid_ep[0xf]	4500	1			T81	1		T120	117		T121	101
endpoints[0x0]	10810	1			T39	1		T29	3		T88	13
endpoints[0x1]	12545	1			T29	2		T31	1		T87	1
endpoints[0x2]	15783	1			T2	1		T28	19		T29	2
endpoints[0x3]	13697	1			T29	3		T88	2		T49	2
endpoints[0x4]	12899	1			T29	2		T49	2		T92	3
endpoints[0x5]	11978	1			T29	4		T88	4		T49	2
endpoints[0x6]	16296	1			T29	3		T88	1		T49	2
endpoints[0x7]	14828	1			T32	11		T49	2		T74	11
endpoints[0x8]	11267	1			T29	4		T33	2		T34	2
endpoints[0x9]	13771	1			T29	5		T35	9		T49	2
endpoints[0xa]	12943	1			T29	2		T49	2		T25	1
endpoints[0xb]	12864	1			T1	1		T29	2		T87	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	23699	1			T87	2		T88	6		T35	9
pkt_types[PidTypeOutToken]	75226	1			T1	1		T2	1		T39	1
pkt_types[PidTypeInToken]	61765	1			T28	11		T29	16		T30	1

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	956	1			T120	32		T121	20		T122	7
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	1024	1			T87	1		T120	27		T121	24
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	999	1			T120	28		T121	20		T122	7
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	1006	1			T120	24		T121	21		T122	13
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1542	1			T88	3		T36	8		T109	1
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1539	1			T260	2		T5	4		T167	1
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1718	1			T169	1		T170	1		T171	1
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1669	1			T88	1		T18	1		T260	1
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1740	1			T92	1		T260	1		T172	1
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1478	1			T88	1		T5	6		T172	2
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1853	1			T88	1		T260	1		T174	22
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1678	1			T57	8		T177	1		T6	23
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1652	1			T166	1		T117	2		T58	8
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1565	1			T35	9		T91	1		T260	2
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1609	1			T53	1		T260	2		T5	6
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1671	1			T87	1		T89	1		T214	1
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1557	1			T117	1		T120	18		T121	28
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1513	1			T81	5		T120	22		T121	20
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1580	1			T117	1		T81	3		T120	31
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1488	1			T81	1		T120	32		T121	26
pkt_types[PidTypeOutToken]	endpoints[0x0]	3533	1			T39	1		T29	2		T88	5
pkt_types[PidTypeOutToken]	endpoints[0x1]	4932	1			T29	1		T87	1		T49	1
pkt_types[PidTypeOutToken]	endpoints[0x2]	8077	1			T2	1		T28	8		T29	1
pkt_types[PidTypeOutToken]	endpoints[0x3]	5905	1			T29	2		T88	1		T49	1
pkt_types[PidTypeOutToken]	endpoints[0x4]	5500	1			T49	1		T92	1		T260	1
pkt_types[PidTypeOutToken]	endpoints[0x5]	4672	1			T29	2		T88	2		T49	1
pkt_types[PidTypeOutToken]	endpoints[0x6]	8234	1			T29	1		T49	1		T54	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	7041	1			T32	11		T49	1		T74	11
pkt_types[PidTypeOutToken]	endpoints[0x8]	3932	1			T29	2		T33	1		T34	1
pkt_types[PidTypeOutToken]	endpoints[0x9]	6231	1			T29	3		T49	1		T21	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	5606	1			T29	1		T49	1		T25	1
pkt_types[PidTypeOutToken]	endpoints[0xb]	5425	1			T1	1		T29	1		T49	1
pkt_types[PidTypeInToken]	invalid_ep[0xc]	1020	1			T120	32		T121	26		T122	6
pkt_types[PidTypeInToken]	invalid_ep[0xd]	1011	1			T117	1		T120	30		T121	36
pkt_types[PidTypeInToken]	invalid_ep[0xe]	1031	1			T119	1		T120	29		T121	24
pkt_types[PidTypeInToken]	invalid_ep[0xf]	1003	1			T120	26		T121	29		T122	13
pkt_types[PidTypeInToken]	endpoints[0x0]	4646	1			T29	1		T88	3		T49	1
pkt_types[PidTypeInToken]	endpoints[0x1]	4984	1			T29	1		T31	1		T49	1
pkt_types[PidTypeInToken]	endpoints[0x2]	4937	1			T28	11		T29	1		T30	1
pkt_types[PidTypeInToken]	endpoints[0x3]	5046	1			T29	1		T49	1		T18	1
pkt_types[PidTypeInToken]	endpoints[0x4]	4542	1			T29	2		T49	1		T92	1
pkt_types[PidTypeInToken]	endpoints[0x5]	4755	1			T29	2		T88	1		T49	1
pkt_types[PidTypeInToken]	endpoints[0x6]	5082	1			T29	2		T49	1		T54	1
pkt_types[PidTypeInToken]	endpoints[0x7]	4940	1			T49	1		T111	1		T165	10
pkt_types[PidTypeInToken]	endpoints[0x8]	4595	1			T29	2		T33	1		T34	1
pkt_types[PidTypeInToken]	endpoints[0x9]	4880	1			T29	2		T49	1		T21	1
pkt_types[PidTypeInToken]	endpoints[0xa]	4625	1			T29	1		T49	1		T53	1
pkt_types[PidTypeInToken]	endpoints[0xb]	4668	1			T29	1		T49	1		T89	1