Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	10199897	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10766272

1

T1

22

T2

7

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	20316717	1			T1	15		T2	10		T3	7
values[0x0]	324610	1			T1	4		T2	1		T3	4
values[0x1]	324842	1			T1	7		T2	9		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8106935	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

12859234

1

T1

23

T2

12

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	58589	1			T32	2		T37	2		T96	5
valid_sources[0x01]	59131	1			T35	1		T37	1		T65	4
valid_sources[0x02]	80500	1			T90	1		T4	38		T5	13
valid_sources[0x03]	59132	1			T33	2		T37	1		T51	1
valid_sources[0x04]	59634	1			T37	1		T64	12		T65	4
valid_sources[0x05]	110515	1			T37	2		T25	19		T55	1
valid_sources[0x06]	59003	1			T29	1		T36	1		T37	1
valid_sources[0x07]	121348	1			T29	1		T37	1		T64	2
valid_sources[0x08]	59669	1			T33	11		T36	1		T37	3
valid_sources[0x09]	185035	1			T37	3		T64	29		T4	39
valid_sources[0x0a]	59059	1			T33	4		T22	1		T169	1
valid_sources[0x0b]	117979	1			T39	1		T33	3		T37	1
valid_sources[0x0c]	58399	1			T33	5		T21	35		T4	40
valid_sources[0x0d]	59461	1			T32	1		T36	1		T37	1
valid_sources[0x0e]	59013	1			T33	6		T36	1		T37	1
valid_sources[0x0f]	69414	1			T1	6		T28	1		T36	3
valid_sources[0x10]	134244	1			T33	1		T37	7		T50	2
valid_sources[0x11]	85006	1			T29	1		T37	1		T55	1
valid_sources[0x12]	59797	1			T40	1		T33	8		T36	1
valid_sources[0x13]	84072	1			T33	11		T36	1		T37	1
valid_sources[0x14]	94742	1			T37	2		T419	12		T64	6
valid_sources[0x15]	61446	1			T40	1		T34	99		T37	1
valid_sources[0x16]	153648	1			T33	6		T37	2		T420	6
valid_sources[0x17]	60484	1			T37	2		T50	2		T51	3
valid_sources[0x18]	152440	1			T37	3		T96	1		T4	50
valid_sources[0x19]	136065	1			T33	1		T37	1		T65	1
valid_sources[0x1a]	80959	1			T29	1		T37	1		T75	1
valid_sources[0x1b]	59406	1			T1	3		T39	1		T32	1
valid_sources[0x1c]	59883	1			T37	1		T51	1		T64	21
valid_sources[0x1d]	59048	1			T33	8		T37	3		T4	39
valid_sources[0x1e]	61797	1			T33	2		T37	1		T55	1
valid_sources[0x1f]	60220	1			T37	1		T38	1		T421	10
valid_sources[0x20]	141994	1			T28	9		T33	2		T37	1
valid_sources[0x21]	58676	1			T33	10		T36	1		T37	3
valid_sources[0x22]	99682	1			T87	3		T90	1		T63	2
valid_sources[0x23]	98328	1			T33	4		T37	1		T7	5
valid_sources[0x24]	60259	1			T37	3		T90	1		T7	3
valid_sources[0x25]	84809	1			T96	3		T4	32		T5	32
valid_sources[0x26]	79321	1			T39	1		T28	2		T37	1
valid_sources[0x27]	81592	1			T30	3		T37	1		T38	2
valid_sources[0x28]	121255	1			T29	2		T50	2		T96	3
valid_sources[0x29]	135144	1			T36	1		T37	2		T75	1
valid_sources[0x2a]	84832	1			T49	1		T169	2		T4	32
valid_sources[0x2b]	66983	1			T42	1		T37	1		T51	1
valid_sources[0x2c]	59851	1			T28	2		T37	1		T7	1
valid_sources[0x2d]	208711	1			T29	3		T33	1		T38	1
valid_sources[0x2e]	59906	1			T39	1		T33	1		T37	1
valid_sources[0x2f]	60123	1			T33	11		T37	1		T51	1
valid_sources[0x30]	58568	1			T36	2		T37	2		T7	3
valid_sources[0x31]	129762	1			T29	1		T37	1		T169	2
valid_sources[0x32]	69582	1			T37	1		T4	30		T114	37
valid_sources[0x33]	111976	1			T40	1		T33	12		T37	2
valid_sources[0x34]	60445	1			T29	2		T33	3		T37	4
valid_sources[0x35]	61982	1			T33	3		T37	1		T38	3
valid_sources[0x36]	190892	1			T39	1		T29	1		T33	3
valid_sources[0x37]	60160	1			T37	2		T55	1		T96	2
valid_sources[0x38]	59809	1			T33	4		T37	3		T192	2
valid_sources[0x39]	66634	1			T37	1		T75	1		T55	1
valid_sources[0x3a]	94853	1			T37	5		T64	13		T4	26
valid_sources[0x3b]	59366	1			T37	1		T51	1		T64	18
valid_sources[0x3c]	60189	1			T42	1		T29	1		T37	1
valid_sources[0x3d]	60638	1			T29	1		T33	5		T64	35
valid_sources[0x3e]	58354	1			T42	1		T33	8		T37	3
valid_sources[0x3f]	60251	1			T37	2		T96	1		T4	46
valid_sources[0x40]	58851	1			T37	1		T7	10		T4	33
valid_sources[0x41]	59587	1			T29	1		T33	16		T37	3
valid_sources[0x42]	111923	1			T3	14		T33	2		T37	1
valid_sources[0x43]	59060	1			T33	6		T4	43		T5	75
valid_sources[0x44]	60347	1			T2	1		T29	2		T33	8
valid_sources[0x45]	276938	1			T89	3		T51	2		T55	1
valid_sources[0x46]	74024	1			T28	1		T29	3		T33	2
valid_sources[0x47]	96460	1			T64	4		T96	1		T4	50
valid_sources[0x48]	145920	1			T37	2		T51	4		T55	1
valid_sources[0x49]	105250	1			T33	4		T37	2		T51	3
valid_sources[0x4a]	76555	1			T33	7		T64	23		T201	1
valid_sources[0x4b]	119699	1			T33	1		T51	1		T4	30
valid_sources[0x4c]	77180	1			T37	1		T7	3		T64	74
valid_sources[0x4d]	58690	1			T33	5		T37	2		T64	4
valid_sources[0x4e]	60085	1			T33	5		T35	1		T64	22
valid_sources[0x4f]	59028	1			T39	1		T33	7		T49	1
valid_sources[0x50]	144756	1			T29	1		T33	6		T37	1
valid_sources[0x51]	59352	1			T96	1		T4	46		T5	70
valid_sources[0x52]	71358	1			T33	3		T87	9		T7	2
valid_sources[0x53]	59170	1			T1	3		T33	4		T4	40
valid_sources[0x54]	181147	1			T7	2		T65	2		T96	2
valid_sources[0x55]	60108	1			T36	1		T37	2		T7	1
valid_sources[0x56]	58774	1			T37	1		T51	1		T7	1
valid_sources[0x57]	117896	1			T37	3		T4	33		T5	18
valid_sources[0x58]	59975	1			T33	3		T37	2		T38	2
valid_sources[0x59]	81286	1			T29	1		T22	1		T4	26
valid_sources[0x5a]	58446	1			T37	2		T75	1		T51	1
valid_sources[0x5b]	57846	1			T36	3		T24	15		T169	1
valid_sources[0x5c]	67669	1			T33	1		T37	1		T64	27
valid_sources[0x5d]	59594	1			T29	1		T33	1		T37	2
valid_sources[0x5e]	66521	1			T33	6		T37	1		T192	2
valid_sources[0x5f]	59200	1			T42	1		T28	2		T37	1
valid_sources[0x60]	104689	1			T33	7		T37	2		T7	1
valid_sources[0x61]	60738	1			T35	1		T37	1		T51	1
valid_sources[0x62]	61164	1			T37	2		T55	1		T65	1
valid_sources[0x63]	78791	1			T28	1		T33	13		T36	1
valid_sources[0x64]	58065	1			T43	62		T33	10		T37	3
valid_sources[0x65]	57915	1			T4	43		T5	16		T114	54
valid_sources[0x66]	59408	1			T33	2		T37	2		T55	1
valid_sources[0x67]	134069	1			T32	1		T33	5		T4	27
valid_sources[0x68]	59421	1			T37	2		T65	1		T96	1
valid_sources[0x69]	125965	1			T33	4		T37	3		T51	1
valid_sources[0x6a]	94336	1			T33	6		T37	3		T65	2
valid_sources[0x6b]	60644	1			T42	1		T33	3		T90	1
valid_sources[0x6c]	58690	1			T33	7		T87	2		T37	1
valid_sources[0x6d]	146648	1			T51	1		T7	7		T55	1
valid_sources[0x6e]	73981	1			T37	1		T7	1		T23	5
valid_sources[0x6f]	132435	1			T33	3		T37	2		T22	1
valid_sources[0x70]	129767	1			T63	1		T64	11		T4	63
valid_sources[0x71]	71393	1			T37	1		T88	28		T7	1
valid_sources[0x72]	59749	1			T33	1		T37	2		T64	21
valid_sources[0x73]	79130	1			T36	3		T37	1		T79	2
valid_sources[0x74]	59753	1			T33	2		T87	6		T37	1
valid_sources[0x75]	59306	1			T37	1		T163	7		T96	2
valid_sources[0x76]	87350	1			T50	4		T65	1		T4	42
valid_sources[0x77]	60930	1			T40	1		T33	2		T51	2
valid_sources[0x78]	59044	1			T37	1		T63	2		T4	35
valid_sources[0x79]	59722	1			T29	1		T35	1		T37	1
valid_sources[0x7a]	58309	1			T33	1		T37	2		T64	34
valid_sources[0x7b]	59105	1			T33	9		T37	1		T4	34
valid_sources[0x7c]	58876	1			T33	9		T37	2		T74	58
valid_sources[0x7d]	94927	1			T42	1		T33	10		T37	2
valid_sources[0x7e]	60609	1			T2	1		T42	1		T33	1
valid_sources[0x7f]	95326	1			T37	1		T64	34		T76	2
valid_sources[0x80]	256631	1			T37	1		T55	2		T4	29

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10244339

1

T1

13

T2

2

T3

5

values[0x0]

all_enables

biggest_size

270232

1

T1

4

T2

1

T3

2

values[0x1]

all_enables

biggest_size

251701

1

T1

5

T2

4

T3

1