Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

10214703

1

T1

4

T2

13

T3

6

full_word

10767261

1

T1

22

T2

7

T3

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	20981664	1			T1	26		T2	20		T3	14
auto[TlIntgErrCmd]	99	1			T229	3		T230	9		T235	1
auto[TlIntgErrData]	89	1			T229	4		T230	6		T235	4
auto[TlIntgErrBoth]	112	1			T229	3		T230	5		T235	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20318484

1

T1

15

T2

10

T3

7

auto[1]

663480

1

T1

11

T2

10

T3

7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	10073837	1			T1	2		T2	8		T3	2
auto[TlIntgErrNone]	partial	auto[1]	140597	1			T1	2		T2	5		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	10244505	1			T1	13		T2	2		T3	5
auto[TlIntgErrNone]	full_word	auto[1]	522725	1			T1	9		T2	5		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T229	1		T230	3		T411	2
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T229	2		T230	5		T235	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T416	1		T242	1		T246	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T230	1		T412	1		T417	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T229	2		T230	3		T235	1
auto[TlIntgErrData]	partial	auto[1]	38	1			T229	2		T230	1		T235	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T230	1		T412	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T230	1		T242	1		T413	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T230	3		T235	2		T410	5
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T229	3		T230	2		T235	2
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T235	1		T416	1		T411	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T416	1		T413	1		T418	1