Module Definition
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Module : prim_fifo_sync_cnt
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.89 97.33 93.33 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.usbdev_avsetupfifo.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.usbdev_avoutfifo.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00


Module Instance : tb.dut.usbdev_avsetupfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 usbdev_avsetupfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.usbdev_avoutfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 usbdev_avoutfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 usbdev_rxfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reqfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_sramreqfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_rspfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=4,Secure=0,PtrW=2,DepthW=3,WrapPtrW=3 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.usbdev_avsetupfifo.gen_normal_fifo.u_fifo_cnt

Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T43 T29 T87 
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T39 T28 T33 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T2 T3 T39 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T43 T29 T87 
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T28 T33 T4 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T2 T3 T28 
133                           end
                        MISSING_ELSE
Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=8,Secure=0,PtrW=3,DepthW=4,WrapPtrW=4 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.usbdev_avoutfifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt

Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T43 T29 T33 
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T29 T33 T34 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T1 T2 T3 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T43 T29 T33 
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T34 T37 T55 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T1 T3 T29 
133                           end
                        MISSING_ELSE
Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Secure=0,PtrW=1,DepthW=1,WrapPtrW=2 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

Line No.TotalCoveredPercent
TOTAL252392.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS1137685.71
ALWAYS1257685.71


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        unreachable          wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T1 T3 T43 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        0/1     ==>          wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        unreachable          rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T1 T3 T43 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        0/1     ==>          rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
133                           end
                        MISSING_ELSE
Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=4,Secure=0,PtrW=2,DepthW=3,WrapPtrW=3 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.usbdev_avsetupfifo.gen_normal_fifo.u_fifo_cnt

TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 2'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT39,T28,T33
10CoveredT2,T3,T39
11CoveredT39,T28,T33 

 LINE       51
 SUB-EXPRESSION (wptr_o == 2'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT39,T28,T33 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 2'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT28,T33,T65
10CoveredT2,T3,T28
11CoveredT28,T33,T4 

 LINE       52
 SUB-EXPRESSION (rptr_o == 2'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T33,T65 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT39,T28,T33 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (3'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((3'(wptr_o) - 3'(rptr_o))) : (((3'(Depth) - 3'(rptr_o)) + 3'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT39,T28,T33 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((3'(wptr_o) - 3'(rptr_o))) : (((3'(Depth) - 3'(rptr_o)) + 3'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT28,T33,T4
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT28,T33,T4
1CoveredT1,T2,T3
Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=8,Secure=0,PtrW=3,DepthW=4,WrapPtrW=4 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.usbdev_avoutfifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt

TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 3'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT28,T29,T33
10CoveredT1,T2,T3
11CoveredT29,T33,T34 

 LINE       51
 SUB-EXPRESSION (wptr_o == 3'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T33 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 3'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT29,T34,T36
10CoveredT1,T3,T29
11CoveredT34,T37,T55 

 LINE       52
 SUB-EXPRESSION (rptr_o == 3'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT29,T34,T36 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT33,T55,T4 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (4'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT33,T55,T4 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT29,T34,T36
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT29,T34,T36
1CoveredT1,T2,T3
Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Secure=0,PtrW=1,DepthW=1,WrapPtrW=2 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

TotalCoveredPercent
Conditions201680.00
Logical201680.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T43 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T43 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T43 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T43 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3
Branch Coverage for Module : prim_fifo_sync_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00 



68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==>

Branches:
-1--2-StatusTests
1 - Covered T39,T28,T33
0 1 Covered T1,T2,T3
0 0 Covered T28,T29,T33 



113              if (!rst_ni) begin
                 -1-  
114                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
115              end else if (clr_i) begin
                          -2-  
116                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
117              end else if (wptr_wrap_set) begin
                          -3-  
118                wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
                   ==>
119              end else if (incr_wptr_i) begin
                          -4-  
120                wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
121              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T43,T29,T33
0 0 1 - Covered T1,T3,T39
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3 



125              if (!rst_ni) begin
                 -1-  
126                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
127              end else if (clr_i) begin
                          -2-  
128                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
129              end else if (rptr_wrap_set) begin
                          -3-  
130                rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
                   ==>
131              end else if (incr_rptr_i) begin
                          -4-  
132                rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
133              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T43,T29,T33
0 0 1 - Covered T1,T3,T28
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T43 T29 T87 
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T39 T28 T33 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T2 T3 T39 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T43 T29 T87 
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T28 T33 T4 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T2 T3 T28 
133                           end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 2'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT39,T28,T33
10CoveredT2,T3,T39
11CoveredT39,T28,T33 

 LINE       51
 SUB-EXPRESSION (wptr_o == 2'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT39,T28,T33 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 2'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT28,T33,T65
10CoveredT2,T3,T28
11CoveredT28,T33,T4 

 LINE       52
 SUB-EXPRESSION (rptr_o == 2'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T33,T65 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT39,T28,T33 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (3'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((3'(wptr_o) - 3'(rptr_o))) : (((3'(Depth) - 3'(rptr_o)) + 3'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT39,T28,T33 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((3'(wptr_o) - 3'(rptr_o))) : (((3'(Depth) - 3'(rptr_o)) + 3'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT28,T33,T4
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT28,T33,T4
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00 



68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==>

Branches:
-1--2-StatusTests
1 - Covered T39,T28,T33
0 1 Covered T1,T2,T3
0 0 Covered T28,T33,T4 



113              if (!rst_ni) begin
                 -1-  
114                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
115              end else if (clr_i) begin
                          -2-  
116                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
117              end else if (wptr_wrap_set) begin
                          -3-  
118                wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
                   ==>
119              end else if (incr_wptr_i) begin
                          -4-  
120                wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
121              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T43,T29,T87
0 0 1 - Covered T39,T28,T33
0 0 0 1 Covered T2,T3,T39
0 0 0 0 Covered T1,T2,T3 



125              if (!rst_ni) begin
                 -1-  
126                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
127              end else if (clr_i) begin
                          -2-  
128                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
129              end else if (rptr_wrap_set) begin
                          -3-  
130                rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
                   ==>
131              end else if (incr_rptr_i) begin
                          -4-  
132                rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
133              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T43,T29,T87
0 0 1 - Covered T28,T33,T4
0 0 0 1 Covered T2,T3,T28
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.usbdev_avoutfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T43 T29 T33 
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T29 T33 T34 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T1 T40 T42 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T43 T29 T33 
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T34 T96 T4 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T1 T29 T30 
133                           end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.usbdev_avoutfifo.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 3'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT29,T33,T34
10CoveredT1,T40,T42
11CoveredT29,T33,T34 

 LINE       51
 SUB-EXPRESSION (wptr_o == 3'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT29,T33,T34 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 3'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT29,T34,T36
10CoveredT1,T29,T30
11CoveredT34,T96,T4 

 LINE       52
 SUB-EXPRESSION (rptr_o == 3'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT29,T34,T36 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT33,T55,T4 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (4'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT33,T55,T4 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT29,T34,T36
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT29,T34,T36
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.usbdev_avoutfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00 



68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==>

Branches:
-1--2-StatusTests
1 - Covered T33,T55,T4
0 1 Covered T1,T2,T3
0 0 Covered T29,T34,T36 



113              if (!rst_ni) begin
                 -1-  
114                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
115              end else if (clr_i) begin
                          -2-  
116                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
117              end else if (wptr_wrap_set) begin
                          -3-  
118                wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
                   ==>
119              end else if (incr_wptr_i) begin
                          -4-  
120                wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
121              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T43,T29,T33
0 0 1 - Covered T29,T33,T34
0 0 0 1 Covered T1,T40,T42
0 0 0 0 Covered T1,T2,T3 



125              if (!rst_ni) begin
                 -1-  
126                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
127              end else if (clr_i) begin
                          -2-  
128                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
129              end else if (rptr_wrap_set) begin
                          -3-  
130                rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
                   ==>
131              end else if (incr_rptr_i) begin
                          -4-  
132                rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
133              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T43,T29,T33
0 0 1 - Covered T34,T96,T4
0 0 0 1 Covered T1,T29,T30
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T43 T29 T87 
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T33 T34 T37 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T1 T2 T3 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T43 T29 T87 
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T34 T37 T55 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T1 T3 T29 
133                           end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 3'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT28,T29,T33
10CoveredT1,T2,T3
11CoveredT33,T34,T37 

 LINE       51
 SUB-EXPRESSION (wptr_o == 3'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T33 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 3'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT29,T34,T36
10CoveredT1,T3,T29
11CoveredT34,T37,T55 

 LINE       52
 SUB-EXPRESSION (rptr_o == 3'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT29,T34,T36 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT33,T55,T56 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (4'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT33,T55,T56 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT34,T37,T55
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT34,T37,T55
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00 



68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==>

Branches:
-1--2-StatusTests
1 - Covered T33,T55,T56
0 1 Covered T1,T2,T3
0 0 Covered T34,T37,T55 



113              if (!rst_ni) begin
                 -1-  
114                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
115              end else if (clr_i) begin
                          -2-  
116                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
117              end else if (wptr_wrap_set) begin
                          -3-  
118                wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
                   ==>
119              end else if (incr_wptr_i) begin
                          -4-  
120                wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
121              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T43,T29,T87
0 0 1 - Covered T33,T34,T37
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Covered T1,T2,T3 



125              if (!rst_ni) begin
                 -1-  
126                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
127              end else if (clr_i) begin
                          -2-  
128                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
129              end else if (rptr_wrap_set) begin
                          -3-  
130                rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
                   ==>
131              end else if (incr_rptr_i) begin
                          -4-  
132                rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
133              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T43,T29,T87
0 0 1 - Covered T34,T37,T55
0 0 0 1 Covered T1,T3,T29
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2323100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11366100.00
ALWAYS12566100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        unreachable          wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T1 T3 T43 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        excluded             wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
Exclude Annotation: VC_COV_UNR
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        unreachable          rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T1 T3 T43 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        excluded             rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
Exclude Annotation: VC_COV_UNR
133                           end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions1616100.00
Logical1616100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T3,T43 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T3,T43 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T43 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T43 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))
                 ----------------1---------------
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 68 2 2 100.00
IF 113 3 3 100.00
IF 125 3 3 100.00 



68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==> (Excluded)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T1,T3,T43
0 1 Covered T1,T2,T3
0 0 Excluded VC_COV_UNR 



113              if (!rst_ni) begin
                 -1-  
114                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
115              end else if (clr_i) begin
                          -2-  
116                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==> (Unreachable)
117              end else if (wptr_wrap_set) begin
                          -3-  
118                wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
                   ==>
119              end else if (incr_wptr_i) begin
                          -4-  
120                wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==> (Excluded)
Exclude Annotation: VC_COV_UNR
121              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTestsExclude Annotation
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Covered T1,T3,T43
0 0 0 1 Excluded VC_COV_UNR
0 0 0 0 Covered T1,T2,T3 



125              if (!rst_ni) begin
                 -1-  
126                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
127              end else if (clr_i) begin
                          -2-  
128                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==> (Unreachable)
129              end else if (rptr_wrap_set) begin
                          -3-  
130                rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
                   ==>
131              end else if (incr_rptr_i) begin
                          -4-  
132                rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==> (Excluded)
Exclude Annotation: VC_COV_UNR
133              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTestsExclude Annotation
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Covered T1,T3,T43
0 0 0 1 Excluded VC_COV_UNR
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2323100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11366100.00
ALWAYS12566100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        unreachable          wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T1 T3 T32 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        excluded             wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
Exclude Annotation: VC_COV_UNR
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        unreachable          rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T1 T3 T32 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        excluded             rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
Exclude Annotation: VC_COV_UNR
133                           end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions1616100.00
Logical1616100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T3,T32 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T3,T32 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T32 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T32 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))
                 ----------------1---------------
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 68 2 2 100.00
IF 113 3 3 100.00
IF 125 3 3 100.00 



68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==> (Excluded)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T1,T3,T32
0 1 Covered T1,T2,T3
0 0 Excluded VC_COV_UNR 



113              if (!rst_ni) begin
                 -1-  
114                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
115              end else if (clr_i) begin
                          -2-  
116                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==> (Unreachable)
117              end else if (wptr_wrap_set) begin
                          -3-  
118                wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
                   ==>
119              end else if (incr_wptr_i) begin
                          -4-  
120                wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==> (Excluded)
Exclude Annotation: VC_COV_UNR
121              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTestsExclude Annotation
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Covered T1,T3,T32
0 0 0 1 Excluded VC_COV_UNR
0 0 0 0 Covered T1,T2,T3 



125              if (!rst_ni) begin
                 -1-  
126                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
127              end else if (clr_i) begin
                          -2-  
128                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==> (Unreachable)
129              end else if (rptr_wrap_set) begin
                          -3-  
130                rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
                   ==>
131              end else if (incr_rptr_i) begin
                          -4-  
132                rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==> (Excluded)
Exclude Annotation: VC_COV_UNR
133              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTestsExclude Annotation
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Covered T1,T3,T32
0 0 0 1 Excluded VC_COV_UNR
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2323100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11366100.00
ALWAYS12566100.00


40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        unreachable          wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T1 T3 T32 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        excluded             wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
Exclude Annotation: VC_COV_UNR
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        unreachable          rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T1 T3 T32 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        excluded             rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
Exclude Annotation: VC_COV_UNR
133                           end
                        MISSING_ELSE
Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions1616100.00
Logical1616100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T3,T32 

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T3,T32 

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT32,T37,T21 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT32,T37,T21 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))
                 ----------------1---------------
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 68 2 2 100.00
IF 113 3 3 100.00
IF 125 3 3 100.00 



68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==> (Excluded)

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T32,T37,T21
0 1 Covered T1,T2,T3
0 0 Excluded VC_COV_UNR 



113              if (!rst_ni) begin
                 -1-  
114                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
115              end else if (clr_i) begin
                          -2-  
116                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==> (Unreachable)
117              end else if (wptr_wrap_set) begin
                          -3-  
118                wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
                   ==>
119              end else if (incr_wptr_i) begin
                          -4-  
120                wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==> (Excluded)
Exclude Annotation: VC_COV_UNR
121              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTestsExclude Annotation
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Covered T1,T3,T32
0 0 0 1 Excluded VC_COV_UNR
0 0 0 0 Covered T1,T2,T3 



125              if (!rst_ni) begin
                 -1-  
126                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
127              end else if (clr_i) begin
                          -2-  
128                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==> (Unreachable)
129              end else if (rptr_wrap_set) begin
                          -3-  
130                rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
                   ==>
131              end else if (incr_rptr_i) begin
                          -4-  
132                rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==> (Excluded)
Exclude Annotation: VC_COV_UNR
133              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4-StatusTestsExclude Annotation
1 - - - Covered T1,T2,T3
0 1 - - Unreachable
0 0 1 - Covered T1,T3,T32
0 0 0 1 Excluded VC_COV_UNR
0 0 0 0 Covered T1,T2,T3

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