Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	593596346	11797	0	0
ep_in_enable_rd_A	593596346	3328	0	0
ep_out_enable_rd_A	593596346	3354	0	0
in_iso_rd_A	593596346	3814	0	0
intr_enable_rd_A	593596346	4916	0	0
out_iso_rd_A	593596346	3270	0	0
phy_config_rd_A	593596346	2177	0	0
phy_pins_drive_rd_A	593596346	2974	0	0
rxenable_setup_rd_A	593596346	3889	0	0
set_nak_out_rd_A	593596346	3887	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593596346	11797	0	0
T209	4484	107	0	0
T210	6595	15	0	0
T211	13747	952	0	0
T229	41531	4	0	0
T230	67470	1	0	0
T237	8053	461	0	0
T238	8225	655	0	0
T239	7449	340	0	0
T248	5560	6	0	0
T249	4771	21	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593596346	3328	0	0
T229	41531	131	0	0
T231	3584	58	0	0
T248	5560	52	0	0
T267	9527	88	0	0
T272	6945	6	0	0
T278	10998	18	0	0
T281	4094	7	0	0
T290	9108	73	0	0
T291	10016	86	0	0
T292	4319	63	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593596346	3354	0	0
T229	41531	364	0	0
T231	3584	2	0	0
T248	5560	4	0	0
T267	9527	83	0	0
T272	6945	5	0	0
T278	10998	25	0	0
T281	4094	41	0	0
T290	9108	69	0	0
T291	10016	89	0	0
T292	4319	69	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593596346	3814	0	0
T216	4210	4	0	0
T229	41531	360	0	0
T231	3584	27	0	0
T248	5560	7	0	0
T267	9527	94	0	0
T272	6945	4	0	0
T278	10998	48	0	0
T281	4094	50	0	0
T290	9108	47	0	0
T291	10016	114	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593596346	4916	0	0
T215	2807	41	0	0
T216	4210	4	0	0
T217	2540	16	0	0
T218	1895	15	0	0
T229	41531	256	0	0
T231	3584	5	0	0
T248	5560	9	0	0
T267	9527	65	0	0
T278	10998	90	0	0
T290	9108	43	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593596346	3270	0	0
T216	4210	3	0	0
T229	41531	282	0	0
T248	5560	6	0	0
T250	5995	10	0	0
T267	9527	76	0	0
T278	10998	32	0	0
T281	4094	36	0	0
T290	9108	17	0	0
T291	10016	124	0	0
T292	4319	6	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593596346	2177	0	0
T229	41531	126	0	0
T231	3584	16	0	0
T248	5560	2	0	0
T250	5995	6	0	0
T267	9527	59	0	0
T278	10998	56	0	0
T281	4094	12	0	0
T290	9108	62	0	0
T291	10016	122	0	0
T292	4319	50	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593596346	2974	0	0
T216	4210	1	0	0
T229	41531	192	0	0
T231	3584	24	0	0
T248	5560	27	0	0
T267	9527	65	0	0
T272	6945	16	0	0
T278	10998	71	0	0
T281	4094	22	0	0
T290	9108	67	0	0
T291	10016	78	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593596346	3889	0	0
T216	4210	8	0	0
T229	41531	165	0	0
T231	3584	48	0	0
T248	5560	36	0	0
T267	9527	80	0	0
T272	6945	5	0	0
T278	10998	21	0	0
T281	4094	86	0	0
T290	9108	79	0	0
T291	10016	102	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593596346	3887	0	0
T216	4210	2	0	0
T229	41531	353	0	0
T231	3584	26	0	0
T248	5560	2	0	0
T267	9527	99	0	0
T272	6945	5	0	0
T278	10998	17	0	0
T281	4094	95	0	0
T290	9108	38	0	0
T291	10016	101	0	0