Unified Coverage Report :: Module :: usb_fs_nb_pe

Module : usb_fs_nb_pe

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_pe.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.79	99.55	96.37		94.12	98.90	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.70	100.00	98.78			100.00	100.00	usbdev_impl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_usb_fs_nb_in_pe	96.14	98.32	95.61		90.91	95.83	100.00
u_usb_fs_nb_out_pe	95.47	99.21	92.54		87.50	98.08	100.00
u_usb_fs_rx	99.51	100.00	98.54			100.00
u_usb_fs_tx	99.63	100.00	98.15		100.00	100.00	100.00
u_usb_fs_tx_mux	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usb_fs_nb_pe

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	176	1	1	100.00

165                       // - SOF is detected and may be used for timing/synchronization purposes if the PID is valid.
166        1/1            assign sof_detected_o = rx_pkt_end & rx_pid_valid & (usb_pid_e'(rx_pid) == UsbPidSof);
           Tests:       T1 T2 T3 
167                       // - The SOF packet is considered valid iff the packet is also free of bit stuffing violations
168                       //   and the CRC5 is correct.
169        1/1            assign sof_valid_o = rx_pkt_end & rx_pkt_valid & (usb_pid_e'(rx_pid) == UsbPidSof);
           Tests:       T1 T2 T3 
170                       // - The frame number shall be used only if the SOF packet is valid.
171        1/1            assign frame_index_o = rx_frame_num;
           Tests:       T1 T2 T3 
172        1/1            assign usb_oe_o = usb_oe;
           Tests:       T1 T2 T3 
173                     
174                       // IN ep type configuration
175                       logic [NumInEps-1:0] in_ep_iso_not_control;
176        1/1            assign in_ep_iso_not_control = in_ep_iso_i & ~out_ep_control_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : usb_fs_nb_pe

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       166
 EXPRESSION (rx_pkt_end & rx_pid_valid & (usb_pid_e'(rx_pid) == UsbPidSof))
             -----1----   ------2-----   ----------------3----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T40,T32,T34
1	0	1	Covered	T83,T84,T176
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T40,T18,T20

 LINE       166
 SUB-EXPRESSION (usb_pid_e'(rx_pid) == UsbPidSof)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T40,T32,T34

 LINE       169
 EXPRESSION (rx_pkt_end & rx_pkt_valid & (usb_pid_e'(rx_pid) == UsbPidSof))
             -----1----   ------2-----   ----------------3----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T40,T18,T20
1	0	1	Covered	T83,T84,T176
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T40,T18,T20

 LINE       169
 SUB-EXPRESSION (usb_pid_e'(rx_pid) == UsbPidSof)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T40,T32,T34

---

Assert Coverage for Module : usb_fs_nb_pe

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumOutEpsEqualsNumInEps_A	3726	3726	0	0
ParamMaxPktSizeByteValid	3726	3726	0	0
ParamNumEpsOutAndInEqual	3726	3726	0	0
ParamNumInEpsValid	3726	3726	0	0
ParamNumOutEpsValid	3726	3726	0	0

NumOutEpsEqualsNumInEps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3726	3726	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0

ParamMaxPktSizeByteValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	3726	3726	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0

ParamNumEpsOutAndInEqual

Name	Attempts	Real Successes	Failures	Incomplete
Total	3726	3726	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0

ParamNumInEpsValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	3726	3726	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0

ParamNumOutEpsValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	3726	3726	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0