Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	10097144	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10686217

1

T1

6

T2

6

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	20129841	1			T1	10		T2	3		T3	7
values[0x0]	326543	1			T1	4		T2	2		T3	11
values[0x1]	326977	1			T1	6		T2	7		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8028502	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

12754859

1

T1

10

T2

9

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	132373	1			T29	20		T63	2		T40	31
valid_sources[0x01]	61566	1			T63	7		T40	43		T110	28
valid_sources[0x02]	122673	1			T63	5		T40	44		T110	21
valid_sources[0x03]	109677	1			T63	9		T40	43		T110	27
valid_sources[0x04]	107764	1			T63	8		T34	2		T40	41
valid_sources[0x05]	69379	1			T63	5		T40	36		T110	25
valid_sources[0x06]	62040	1			T63	7		T40	53		T110	26
valid_sources[0x07]	61560	1			T40	37		T110	19		T22	1
valid_sources[0x08]	70831	1			T63	19		T40	38		T110	26
valid_sources[0x09]	62310	1			T63	2		T40	35		T110	25
valid_sources[0x0a]	101177	1			T63	7		T34	1		T40	17
valid_sources[0x0b]	61662	1			T32	6		T63	10		T40	35
valid_sources[0x0c]	61146	1			T63	5		T40	44		T110	28
valid_sources[0x0d]	121632	1			T63	11		T40	40		T110	26
valid_sources[0x0e]	77292	1			T41	1		T32	2		T63	5
valid_sources[0x0f]	80826	1			T63	6		T34	1		T40	36
valid_sources[0x10]	61166	1			T63	3		T40	58		T110	29
valid_sources[0x11]	63075	1			T63	7		T40	37		T110	27
valid_sources[0x12]	60707	1			T63	4		T40	38		T110	23
valid_sources[0x13]	61999	1			T63	4		T40	47		T110	18
valid_sources[0x14]	62786	1			T63	12		T40	29		T110	20
valid_sources[0x15]	62651	1			T32	4		T40	35		T110	18
valid_sources[0x16]	60505	1			T32	8		T63	9		T40	53
valid_sources[0x17]	101027	1			T28	1		T63	7		T40	33
valid_sources[0x18]	152059	1			T32	6		T63	7		T40	24
valid_sources[0x19]	62057	1			T32	6		T63	7		T40	25
valid_sources[0x1a]	129013	1			T63	13		T40	40		T110	18
valid_sources[0x1b]	131536	1			T63	8		T40	30		T110	21
valid_sources[0x1c]	61149	1			T28	1		T63	9		T34	1
valid_sources[0x1d]	61705	1			T32	5		T63	8		T40	22
valid_sources[0x1e]	78085	1			T63	5		T40	32		T110	21
valid_sources[0x1f]	60376	1			T41	1		T88	3		T63	12
valid_sources[0x20]	60969	1			T63	7		T40	35		T110	22
valid_sources[0x21]	97134	1			T63	9		T40	39		T110	29
valid_sources[0x22]	79339	1			T63	9		T34	1		T40	58
valid_sources[0x23]	62826	1			T32	3		T63	12		T40	33
valid_sources[0x24]	206659	1			T28	1		T32	3		T63	5
valid_sources[0x25]	136854	1			T63	8		T40	35		T110	27
valid_sources[0x26]	156837	1			T32	1		T63	5		T33	2
valid_sources[0x27]	61919	1			T32	1		T63	2		T40	37
valid_sources[0x28]	60831	1			T63	2		T48	1		T40	38
valid_sources[0x29]	71071	1			T63	14		T40	45		T110	32
valid_sources[0x2a]	91248	1			T42	1		T63	5		T40	40
valid_sources[0x2b]	74028	1			T63	5		T48	1		T40	41
valid_sources[0x2c]	62682	1			T63	5		T40	43		T110	23
valid_sources[0x2d]	61938	1			T2	5		T29	10		T31	19
valid_sources[0x2e]	86941	1			T32	3		T63	2		T40	41
valid_sources[0x2f]	93782	1			T32	8		T63	7		T40	35
valid_sources[0x30]	85620	1			T41	1		T63	6		T40	34
valid_sources[0x31]	101141	1			T63	5		T34	1		T40	53
valid_sources[0x32]	61685	1			T32	1		T63	1		T34	1
valid_sources[0x33]	160897	1			T63	2		T34	2		T40	40
valid_sources[0x34]	68357	1			T29	4		T63	6		T40	55
valid_sources[0x35]	60573	1			T63	4		T40	39		T110	20
valid_sources[0x36]	61737	1			T63	11		T40	32		T110	21
valid_sources[0x37]	74301	1			T32	1		T63	4		T34	1
valid_sources[0x38]	97223	1			T32	1		T63	11		T40	25
valid_sources[0x39]	88201	1			T1	20		T63	1		T48	2
valid_sources[0x3a]	73709	1			T63	3		T40	36		T110	24
valid_sources[0x3b]	71818	1			T29	8		T32	11		T63	3
valid_sources[0x3c]	63353	1			T63	6		T89	3		T40	35
valid_sources[0x3d]	76118	1			T88	6		T63	3		T40	46
valid_sources[0x3e]	100129	1			T63	2		T40	42		T110	28
valid_sources[0x3f]	92385	1			T63	6		T40	21		T110	33
valid_sources[0x40]	77766	1			T63	2		T40	26		T110	24
valid_sources[0x41]	70052	1			T63	1		T34	1		T40	40
valid_sources[0x42]	72357	1			T63	8		T40	36		T110	21
valid_sources[0x43]	62515	1			T63	2		T40	57		T110	20
valid_sources[0x44]	61551	1			T63	4		T40	32		T110	20
valid_sources[0x45]	62244	1			T2	1		T63	3		T40	41
valid_sources[0x46]	80301	1			T63	5		T40	50		T110	23
valid_sources[0x47]	84621	1			T32	5		T63	13		T40	29
valid_sources[0x48]	61109	1			T63	2		T40	40		T110	22
valid_sources[0x49]	60126	1			T63	3		T40	31		T110	19
valid_sources[0x4a]	95959	1			T63	2		T40	31		T110	23
valid_sources[0x4b]	61518	1			T2	1		T32	2		T63	5
valid_sources[0x4c]	60386	1			T63	1		T40	24		T110	23
valid_sources[0x4d]	61375	1			T88	6		T63	4		T40	41
valid_sources[0x4e]	61671	1			T63	1		T40	34		T110	11
valid_sources[0x4f]	60357	1			T32	1		T63	5		T34	1
valid_sources[0x50]	108762	1			T63	10		T34	1		T40	25
valid_sources[0x51]	61770	1			T63	12		T48	1		T40	33
valid_sources[0x52]	61096	1			T63	10		T40	39		T110	26
valid_sources[0x53]	72909	1			T32	1		T63	7		T40	41
valid_sources[0x54]	62453	1			T63	8		T40	52		T110	20
valid_sources[0x55]	71114	1			T63	10		T40	35		T110	26
valid_sources[0x56]	62343	1			T63	4		T40	29		T110	20
valid_sources[0x57]	115491	1			T63	2		T33	1		T40	38
valid_sources[0x58]	61115	1			T63	12		T89	3		T40	24
valid_sources[0x59]	62430	1			T3	2		T63	4		T40	43
valid_sources[0x5a]	235895	1			T88	7		T63	7		T40	43
valid_sources[0x5b]	62207	1			T63	7		T40	43		T110	26
valid_sources[0x5c]	61568	1			T29	6		T63	7		T34	1
valid_sources[0x5d]	60249	1			T63	2		T33	1		T40	48
valid_sources[0x5e]	62638	1			T63	6		T34	1		T40	25
valid_sources[0x5f]	61974	1			T63	4		T34	1		T40	44
valid_sources[0x60]	62729	1			T32	1		T88	5		T63	6
valid_sources[0x61]	60965	1			T63	2		T40	38		T110	17
valid_sources[0x62]	114592	1			T32	1		T63	4		T40	30
valid_sources[0x63]	62212	1			T63	3		T48	2		T40	34
valid_sources[0x64]	110187	1			T63	3		T40	38		T110	29
valid_sources[0x65]	113389	1			T63	6		T40	40		T110	18
valid_sources[0x66]	62395	1			T29	22		T63	1		T40	51
valid_sources[0x67]	60601	1			T32	4		T63	5		T34	1
valid_sources[0x68]	61779	1			T32	5		T63	9		T40	30
valid_sources[0x69]	162525	1			T32	2		T63	7		T40	33
valid_sources[0x6a]	153982	1			T32	4		T63	1		T40	19
valid_sources[0x6b]	62852	1			T63	2		T40	33		T110	15
valid_sources[0x6c]	61368	1			T63	2		T34	1		T40	34
valid_sources[0x6d]	138920	1			T63	3		T40	27		T110	21
valid_sources[0x6e]	62597	1			T63	7		T40	32		T110	18
valid_sources[0x6f]	62809	1			T32	7		T88	1		T63	8
valid_sources[0x70]	61462	1			T32	11		T63	4		T33	1
valid_sources[0x71]	60883	1			T28	1		T63	4		T40	34
valid_sources[0x72]	111972	1			T88	3		T63	1		T34	1
valid_sources[0x73]	76771	1			T32	1		T63	7		T40	28
valid_sources[0x74]	60920	1			T32	4		T88	3		T63	12
valid_sources[0x75]	172674	1			T63	5		T34	1		T40	37
valid_sources[0x76]	140750	1			T63	3		T40	50		T110	16
valid_sources[0x77]	84816	1			T63	2		T34	1		T40	34
valid_sources[0x78]	80256	1			T88	3		T63	11		T40	27
valid_sources[0x79]	61421	1			T29	3		T63	6		T40	37
valid_sources[0x7a]	61258	1			T28	2		T29	37		T63	9
valid_sources[0x7b]	122949	1			T32	4		T63	11		T40	26
valid_sources[0x7c]	61978	1			T3	7		T63	7		T40	32
valid_sources[0x7d]	83332	1			T63	4		T34	1		T40	42
valid_sources[0x7e]	145454	1			T63	11		T40	32		T110	29
valid_sources[0x7f]	90102	1			T63	2		T34	3		T40	53
valid_sources[0x80]	81354	1			T63	8		T34	1		T40	32

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10164013

1

T1

1

T2

1

T3

3

values[0x0]

all_enables

biggest_size

270473

1

T1

3

T2

2

T3

6

values[0x1]

all_enables

biggest_size

251731

1

T1

2

T2

3

T3

1