Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	582225092	10922	0	0
ep_in_enable_rd_A	582225092	2264	0	0
ep_out_enable_rd_A	582225092	2655	0	0
in_iso_rd_A	582225092	2385	0	0
intr_enable_rd_A	582225092	3447	0	0
out_iso_rd_A	582225092	2538	0	0
phy_config_rd_A	582225092	1449	0	0
phy_pins_drive_rd_A	582225092	1917	0	0
rxenable_setup_rd_A	582225092	1845	0	0
set_nak_out_rd_A	582225092	2226	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582225092	10922	0	0
T204	5344	996	0	0
T205	5774	14	0	0
T206	29168	3	0	0
T232	8007	13	0	0
T240	13312	3	0	0
T241	2907	9	0	0
T242	8306	17	0	0
T243	6431	1092	0	0
T244	7820	463	0	0
T256	37679	2	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582225092	2264	0	0
T205	5774	61	0	0
T209	5413	7	0	0
T213	3996	15	0	0
T232	8007	7	0	0
T233	35603	246	0	0
T272	5728	8	0	0
T275	6881	4	0	0
T277	3816	46	0	0
T279	10856	24	0	0
T280	19274	193	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582225092	2655	0	0
T205	5774	53	0	0
T209	5413	1	0	0
T213	3996	4	0	0
T232	8007	43	0	0
T233	35603	178	0	0
T272	5728	14	0	0
T273	4731	23	0	0
T275	6881	6	0	0
T277	3816	45	0	0
T279	10856	32	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582225092	2385	0	0
T205	5774	6	0	0
T213	3996	11	0	0
T232	8007	64	0	0
T233	35603	214	0	0
T272	5728	12	0	0
T273	4731	25	0	0
T275	6881	2	0	0
T277	3816	67	0	0
T279	10856	46	0	0
T280	19274	198	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582225092	3447	0	0
T205	5774	11	0	0
T209	5413	16	0	0
T210	2315	30	0	0
T211	1923	8	0	0
T213	3996	4	0	0
T232	8007	40	0	0
T233	35603	456	0	0
T275	6881	7	0	0
T277	3816	71	0	0
T281	2284	14	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582225092	2538	0	0
T205	5774	1	0	0
T209	5413	8	0	0
T213	3996	10	0	0
T232	8007	70	0	0
T233	35603	189	0	0
T272	5728	7	0	0
T273	4731	15	0	0
T275	6881	17	0	0
T277	3816	48	0	0
T279	10856	14	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582225092	1449	0	0
T205	5774	46	0	0
T209	5413	10	0	0
T213	3996	2	0	0
T232	8007	4	0	0
T233	35603	134	0	0
T272	5728	5	0	0
T273	4731	1	0	0
T275	6881	12	0	0
T277	3816	40	0	0
T279	10856	15	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582225092	1917	0	0
T205	5774	3	0	0
T209	5413	1	0	0
T213	3996	12	0	0
T232	8007	44	0	0
T233	35603	219	0	0
T272	5728	2	0	0
T273	4731	27	0	0
T275	6881	12	0	0
T277	3816	56	0	0
T279	10856	15	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582225092	1845	0	0
T205	5774	39	0	0
T209	5413	13	0	0
T213	3996	8	0	0
T232	8007	14	0	0
T233	35603	221	0	0
T272	5728	6	0	0
T275	6881	9	0	0
T277	3816	56	0	0
T279	10856	7	0	0
T280	19274	171	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582225092	2226	0	0
T205	5774	10	0	0
T209	5413	5	0	0
T213	3996	3	0	0
T232	8007	18	0	0
T233	35603	146	0	0
T244	7820	2	0	0
T272	5728	1	0	0
T277	3816	106	0	0
T279	10856	7	0	0
T280	19274	191	0	0