Line Coverage for Module :
usbdev_linkstate
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 104 | 101 | 97.12 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| ALWAYS | 139 | 34 | 31 | 91.18 |
| ALWAYS | 231 | 3 | 3 | 100.00 |
| ALWAYS | 245 | 18 | 18 | 100.00 |
| CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
| ALWAYS | 292 | 5 | 5 | 100.00 |
| ALWAYS | 307 | 16 | 16 | 100.00 |
| ALWAYS | 348 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 365 | 1 | 1 | 100.00 |
| ALWAYS | 367 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| ALWAYS | 380 | 6 | 6 | 100.00 |
91
92 1/1 assign link_disconnect_o = (link_state_q == LinkDisconnected);
Tests: T1 T2 T3
93 1/1 assign link_powered_o = see_pwr_sense;
Tests: T1 T2 T3
94 1/1 assign link_suspend_o = (link_state_q == LinkSuspended ||
Tests: T1 T2 T3
95 link_state_q == LinkPoweredSuspended);
96 1/1 assign link_active_o = (link_state_q == LinkActive) ||
Tests: T1 T2 T3
97 (link_state_q == LinkActiveNoSOF);
98 // Link state is stable, so we can output it to the register
99 1/1 assign link_state_o = link_state_q;
Tests: T1 T2 T3
100
101 // If the PHY reflects the line state on rx pins when the device is driving
102 // then the usb_oe_i check isn't needed here. But it seems best to do the check
103 // to be robust in the face of different PHY designs.
104 logic see_se0, line_se0_raw;
105 1/1 assign line_se0_raw = (usb_dn_i == 1'b0) & (usb_dp_i == 1'b0) & (usb_oe_i == 1'b0);
Tests: T1 T2 T3
106
107 // four ticks is a bit time
108 // Could completely filter out 2-cycle EOP SE0 here but
109 // does not seem needed
110 prim_filter #(
111 .AsyncOn(0), // No synchronizer required
112 .Cycles(6)
113 ) filter_se0 (
114 .clk_i (clk_48mhz_i),
115 .rst_ni (rst_ni),
116 .enable_i (1'b1),
117 .filter_i (line_se0_raw),
118 .filter_o (see_se0)
119 );
120
121 prim_filter #(
122 .AsyncOn(0), // No synchronizer required
123 .Cycles(6)
124 ) filter_pwr_sense (
125 .clk_i (clk_48mhz_i),
126 .rst_ni (rst_ni),
127 .enable_i (1'b1),
128 .filter_i (usb_sense_i),
129 .filter_o (see_pwr_sense)
130 );
131
132 // Simple events
133 1/1 assign ev_bus_active = !rx_idle_det_i;
Tests: T1 T2 T3
134
135 1/1 assign monitor_inac = see_pwr_sense ? ((link_state_q == LinkPowered) | link_active_o) :
Tests: T1 T2 T3
136 1'b0;
137
138 always_comb begin
139 1/1 link_state_d = link_state_q;
Tests: T1 T2 T3
140 1/1 link_resume_o = 0;
Tests: T1 T2 T3
141
142 // If VBUS ever goes away the link has disconnected (likewise if the
143 // pull-up goes away / user requested disconnection)
144 1/1 if (!see_pwr_sense || !usb_pullup_en_i) begin
Tests: T1 T2 T3
145 1/1 link_state_d = LinkDisconnected;
Tests: T1 T2 T3
146 end else begin
147 1/1 unique case (link_state_q)
Tests: T1 T2 T3
148 // No USB supply detected (USB spec: Attached)
149 LinkDisconnected: begin
150 1/1 if (see_pwr_sense & usb_pullup_en_i) begin
Tests: T1 T2 T3
151 1/1 link_state_d = LinkPowered;
Tests: T1 T2 T3
152 end
==> MISSING_ELSE
153 end
154
155 LinkPowered: begin
156 1/1 if (ev_reset) begin
Tests: T1 T2 T3
157 1/1 link_state_d = LinkActiveNoSOF;
Tests: T1 T2 T3
158 1/1 end else if (resume_link_active_i) begin
Tests: T1 T2 T3
159 // Software-directed jump to resume from LinkSuspended, in case
160 // this module was previously powered down.
161 1/1 link_state_d = LinkResuming;
Tests: T70 T96 T73
162 1/1 end else if (ev_bus_inactive) begin
Tests: T1 T2 T3
163 1/1 link_state_d = LinkPoweredSuspended;
Tests: T73 T97 T98
164 end
MISSING_ELSE
165 end
166
167 LinkPoweredSuspended: begin
168 1/1 if (ev_reset) begin
Tests: T73 T97 T98
169 0/1 ==> link_state_d = LinkActiveNoSOF;
170 1/1 end else if (ev_bus_active) begin
Tests: T73 T97 T98
171 1/1 link_resume_o = 1;
Tests: T73 T97 T99
172 1/1 link_state_d = LinkPowered;
Tests: T73 T97 T99
173 end
MISSING_ELSE
174 end
175
176 // An event occurred that brought the link out of LinkSuspended, but
177 // the end-of-resume signaling may not have occurred yet.
178 // Park here before starting to count towards not seeing SOF. Wait for
179 // the end of resume signaling before expecting SOF. The host will
180 // return the link to idle after a low-speed EOP. Instead of trying to
181 // capture the termination of resume signaling direclty, wait for
182 // any J / idle symbol (or a bus reset).
183 LinkResuming: begin
184 1/1 if (rx_j_det_i | ev_reset) begin
Tests: T8 T68 T70
185 1/1 link_resume_o = 1;
Tests: T8 T68 T70
186 1/1 link_state_d = LinkActiveNoSOF;
Tests: T8 T68 T70
187 end
MISSING_ELSE
188 end
189
190 // Active but not yet seen a frame
191 // One reason for getting stuck here is the host thinks it is a LS link
192 // which could happen if the flipped bit does not match the actual pins
193 // Annother is the SI is bad so good data is not recovered from the link
194 LinkActiveNoSOF: begin
195 1/1 if (ev_bus_inactive) begin
Tests: T1 T2 T3
196 1/1 link_state_d = LinkSuspended;
Tests: T7 T8 T9
197 1/1 end else if (sof_detected_i) begin
Tests: T1 T2 T3
198 1/1 link_state_d = LinkActive;
Tests: T41 T7 T100
199 end
MISSING_ELSE
200 end
201
202 // Active (USB spec: Default / Address / Configured)
203 LinkActive: begin
204 1/1 if (ev_bus_inactive) begin
Tests: T41 T7 T100
205 1/1 link_state_d = LinkSuspended;
Tests: T62 T101 T11
206 1/1 end else if (ev_reset) begin
Tests: T41 T7 T100
207 1/1 link_state_d = LinkActiveNoSOF;
Tests: T10 T102 T103
208 end
MISSING_ELSE
209 end
210
211 LinkSuspended: begin
212 1/1 if (ev_reset) begin
Tests: T7 T8 T62
213 0/1 ==> link_resume_o = 1;
214 0/1 ==> link_state_d = LinkActiveNoSOF;
215 1/1 end else if (ev_bus_active) begin
Tests: T7 T8 T62
216 1/1 link_state_d = LinkResuming;
Tests: T8 T68 T101
217 end
MISSING_ELSE
218 end
219
220 default: begin
221 link_state_d = LinkDisconnected;
222 end
223 endcase // case (link_state_q)
224 end
225 end
226
227 `ASSERT(LinkStateValid_A, link_state_q inside {LinkDisconnected, LinkPowered,
228 LinkPoweredSuspended, LinkResuming, LinkActiveNoSOF, LinkActive, LinkSuspended}, clk_48mhz_i)
229
230 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
231 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
232 1/1 link_state_q <= LinkDisconnected;
Tests: T1 T2 T3
233 end else begin
234 1/1 link_state_q <= link_state_d;
Tests: T1 T2 T3
235 end
236 end
237
238 /////////////////////
239 // Reset detection //
240 /////////////////////
241 // Here we clean up the SE0 signal and generate a single ev_reset at
242 // the end of a valid reset
243
244 always_comb begin : proc_rst_fsm
245 1/1 link_rst_state_d = link_rst_state_q;
Tests: T1 T2 T3
246 1/1 link_rst_timer_d = link_rst_timer_q;
Tests: T1 T2 T3
247 1/1 ev_reset = 1'b0;
Tests: T1 T2 T3
248 1/1 link_reset = 1'b0;
Tests: T1 T2 T3
249
250 1/1 unique case (link_rst_state_q)
Tests: T1 T2 T3
251 // No reset signal detected
252 NoRst: begin
253 1/1 if (see_se0) begin
Tests: T1 T2 T3
254 1/1 link_rst_state_d = RstCnt;
Tests: T1 T2 T3
255 1/1 link_rst_timer_d = 0;
Tests: T1 T2 T3
256 end
MISSING_ELSE
257 end
258
259 // Reset signal detected -> counting
260 RstCnt: begin
261 1/1 if (!see_se0) begin
Tests: T1 T2 T3
262 1/1 link_rst_state_d = NoRst;
Tests: T1 T2 T28
263 end else begin
264 1/1 if (us_tick_i) begin
Tests: T1 T2 T3
265 1/1 if (link_rst_timer_q == RESET_TIMEOUT) begin
Tests: T1 T2 T3
266 1/1 link_rst_state_d = RstPend;
Tests: T1 T2 T3
267 end else begin
268 1/1 link_rst_timer_d = link_rst_timer_q + 1;
Tests: T1 T2 T3
269 end
270 end
MISSING_ELSE
271 end
272 end
273
274 // Detected reset -> wait for falling edge
275 RstPend: begin
276 1/1 if (!see_se0) begin
Tests: T1 T2 T3
277 1/1 link_rst_state_d = NoRst;
Tests: T1 T2 T3
278 1/1 ev_reset = 1'b1;
Tests: T1 T2 T3
279 end
MISSING_ELSE
280 1/1 link_reset = 1'b1;
Tests: T1 T2 T3
281 end
282
283 default : link_rst_state_d = NoRst;
284 endcase
285 end
286
287 `ASSERT(LinkRstStateValid_A, link_rst_state_q inside {NoRst, RstCnt, RstPend}, clk_48mhz_i)
288
289 1/1 assign link_reset_o = link_reset;
Tests: T1 T2 T3
290
291 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin : proc_reg_rst
292 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
293 1/1 link_rst_state_q <= NoRst;
Tests: T1 T2 T3
294 1/1 link_rst_timer_q <= 0;
Tests: T1 T2 T3
295 end else begin
296 1/1 link_rst_state_q <= link_rst_state_d;
Tests: T1 T2 T3
297 1/1 link_rst_timer_q <= link_rst_timer_d;
Tests: T1 T2 T3
298 end
299 end
300
301 ////////////////////
302 // Idle detection //
303 ////////////////////
304 // Here we clean up the idle signal and generate a single ev_bus_inactive
305 // after the timer expires
306 always_comb begin : proc_idle_det
307 1/1 link_inac_state_d = link_inac_state_q;
Tests: T1 T2 T3
308 1/1 link_inac_timer_d = link_inac_timer_q;
Tests: T1 T2 T3
309 1/1 ev_bus_inactive = 0;
Tests: T1 T2 T3
310
311 1/1 unique case (link_inac_state_q)
Tests: T1 T2 T3
312 // Active or disabled
313 Active: begin
314 1/1 link_inac_timer_d = 0;
Tests: T1 T2 T3
315 1/1 if (!ev_bus_active && monitor_inac) begin
Tests: T1 T2 T3
316 1/1 link_inac_state_d = InactCnt;
Tests: T1 T2 T3
317 end
MISSING_ELSE
318 end
319
320 // Got an inactivity signal -> count duration
321 InactCnt: begin
322 1/1 if (ev_bus_active || !monitor_inac) begin
Tests: T1 T2 T3
323 1/1 link_inac_state_d = Active;
Tests: T1 T2 T3
324 1/1 end else if (us_tick_i) begin
Tests: T1 T2 T3
325 1/1 if (link_inac_timer_q == SUSPEND_TIMEOUT) begin
Tests: T1 T2 T3
326 1/1 link_inac_state_d = InactPend;
Tests: T7 T8 T62
327 1/1 ev_bus_inactive = 1;
Tests: T7 T8 T62
328 end else begin
329 1/1 link_inac_timer_d = link_inac_timer_q + 1;
Tests: T1 T2 T3
330 end
331 end
MISSING_ELSE
332 end
333
334 // Counter expired & event sent, wait here
335 InactPend: begin
336 1/1 if (ev_bus_active || !monitor_inac) begin
Tests: T7 T8 T62
337 1/1 link_inac_state_d = Active;
Tests: T7 T8 T62
338 end
==> MISSING_ELSE
339 end
340
341 default : link_inac_state_d = Active;
342 endcase
343 end
344
345 `ASSERT(LincInacStateValid_A, link_inac_state_q inside {Active, InactCnt, InactPend}, clk_48mhz_i)
346
347 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin : proc_reg_idle_det
348 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
349 1/1 link_inac_state_q <= Active;
Tests: T1 T2 T3
350 1/1 link_inac_timer_q <= 0;
Tests: T1 T2 T3
351 end else begin
352 1/1 link_inac_state_q <= link_inac_state_d;
Tests: T1 T2 T3
353 1/1 link_inac_timer_q <= link_inac_timer_d;
Tests: T1 T2 T3
354 end
355 end
356
357 /////////////////////////////////////////
358 // Host loss and missing sof detection //
359 /////////////////////////////////////////
360 // sof_missed if no SOF was observed in 1.005ms and the link is active
361 // host_lost if 4 frames have gone by without observing a SOF
362 logic [2:0] missed_sof_count;
363 logic [9:0] missing_sof_timer;
364
365 1/1 assign host_lost_o = missed_sof_count[2];
Tests: T1 T2 T3
366 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
367 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
368 1/1 missed_sof_count <= '0;
Tests: T1 T2 T3
369 end else begin
370 1/1 if (sof_detected_i || !link_active_o || link_reset) begin
Tests: T1 T2 T3
371 1/1 missed_sof_count <= '0;
Tests: T1 T2 T3
372 1/1 end else if (sof_missed_o && !host_lost_o) begin
Tests: T1 T2 T3
373 1/1 missed_sof_count <= missed_sof_count + 1;
Tests: T7 T8 T49
374 end
MISSING_ELSE
375 end
376 end
377
378 1/1 assign sof_missed_o = (missing_sof_timer == SOF_TIMEOUT);
Tests: T1 T2 T3
379 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
380 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
381 1/1 missing_sof_timer <= '0;
Tests: T1 T2 T3
382 end else begin
383 1/1 if (sof_missed_o || sof_detected_i || !link_active_o || link_reset) begin
Tests: T1 T2 T3
384 1/1 missing_sof_timer <= '0;
Tests: T1 T2 T3
385 1/1 end else if (us_tick_i) begin
Tests: T1 T2 T3
386 1/1 missing_sof_timer <= missing_sof_timer + 1;
Tests: T1 T2 T3
387 end
MISSING_ELSE
Cond Coverage for Module :
usbdev_linkstate
| Total | Covered | Percent |
|---|
| Conditions | 69 | 64 | 92.75 |
| Logical | 69 | 64 | 92.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 92
EXPRESSION (link_state_q == LinkDisconnected)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION ((link_state_q == LinkSuspended) || (link_state_q == LinkPoweredSuspended))
---------------1--------------- -------------------2------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T73,T97,T98 |
| 1 | 0 | Covered | T7,T8,T62 |
LINE 94
SUB-EXPRESSION (link_state_q == LinkSuspended)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T62 |
LINE 94
SUB-EXPRESSION (link_state_q == LinkPoweredSuspended)
-------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T73,T97,T98 |
LINE 96
EXPRESSION ((link_state_q == LinkActive) || (link_state_q == LinkActiveNoSOF))
--------------1------------- ----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T41,T7,T100 |
LINE 96
SUB-EXPRESSION (link_state_q == LinkActive)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T41,T7,T100 |
LINE 96
SUB-EXPRESSION (link_state_q == LinkActiveNoSOF)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 105
EXPRESSION ((usb_dn_i == 1'b0) & (usb_dp_i == 1'b0) & (usb_oe_i == 1'b0))
---------1-------- ---------2-------- ---------3--------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T28 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T1,T28,T29 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 105
SUB-EXPRESSION (usb_dn_i == 1'b0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 105
SUB-EXPRESSION (usb_dp_i == 1'b0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 105
SUB-EXPRESSION (usb_oe_i == 1'b0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 135
EXPRESSION (see_pwr_sense ? ((link_state_q == LinkPowered) | link_active_o) : 1'b0)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION ((link_state_q == LinkPowered) | link_active_o)
--------------1-------------- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (link_state_q == LinkPowered)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 144
EXPRESSION (((!see_pwr_sense)) || ((!usb_pullup_en_i)))
---------1-------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T33,T7,T17 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 150
EXPRESSION (see_pwr_sense & usb_pullup_en_i)
------1------ -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 184
EXPRESSION (rx_j_det_i | ev_reset)
-----1---- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T8,T68,T70 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T8,T68,T70 |
LINE 265
EXPRESSION (link_rst_timer_q == RESET_TIMEOUT)
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 315
EXPRESSION (((!ev_bus_active)) && monitor_inac)
---------1-------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T7,T8,T62 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 322
EXPRESSION (ev_bus_active || ((!monitor_inac)))
------1------ --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T7,T8,T9 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 325
EXPRESSION (link_inac_timer_q == SUSPEND_TIMEOUT)
-------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T62 |
LINE 336
EXPRESSION (ev_bus_active || ((!monitor_inac)))
------1------ --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Covered | T7,T8,T62 |
| 1 | 0 | Not Covered | |
LINE 370
EXPRESSION (sof_detected_i || ((!link_active_o)) || link_reset)
-------1------ ---------2-------- -----3----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T1,T2,T3 |
| 0 | 1 | 0 | Covered | T1,T2,T3 |
| 1 | 0 | 0 | Covered | T41,T7,T100 |
LINE 372
EXPRESSION (sof_missed_o && ((!host_lost_o)))
------1----- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T68,T69,T104 |
| 1 | 1 | Covered | T7,T8,T49 |
LINE 378
EXPRESSION (missing_sof_timer == SOF_TIMEOUT)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T49 |
LINE 383
EXPRESSION (sof_missed_o || sof_detected_i || ((!link_active_o)) || link_reset)
------1----- -------2------ ---------3-------- -----4----
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | 0 | 0 | Covered | T41,T7,T100 |
| 1 | 0 | 0 | 0 | Covered | T7,T8,T49 |
FSM Coverage for Module :
usbdev_linkstate
Summary for FSM :: link_state_q
| Total | Covered | Percent | |
| States |
7 |
7 |
100.00 |
(Not included in score) |
| Transitions |
19 |
16 |
84.21 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: link_state_q
| states | Line No. | Covered | Tests |
| LinkActive |
198 |
Covered |
T41,T7,T100 |
| LinkActiveNoSOF |
157 |
Covered |
T1,T2,T3 |
| LinkDisconnected |
145 |
Covered |
T1,T2,T3 |
| LinkPowered |
151 |
Covered |
T1,T2,T3 |
| LinkPoweredSuspended |
163 |
Covered |
T73,T97,T98 |
| LinkResuming |
161 |
Covered |
T8,T68,T70 |
| LinkSuspended |
196 |
Covered |
T7,T8,T62 |
| transitions | Line No. | Covered | Tests |
| LinkActive->LinkActiveNoSOF |
207 |
Covered |
T10,T102,T103 |
| LinkActive->LinkDisconnected |
145 |
Covered |
T41,T7,T66 |
| LinkActive->LinkSuspended |
205 |
Covered |
T62,T101,T11 |
| LinkActiveNoSOF->LinkActive |
198 |
Covered |
T41,T7,T100 |
| LinkActiveNoSOF->LinkDisconnected |
145 |
Covered |
T8,T9,T70 |
| LinkActiveNoSOF->LinkSuspended |
196 |
Covered |
T7,T8,T9 |
| LinkDisconnected->LinkPowered |
151 |
Covered |
T1,T2,T3 |
| LinkPowered->LinkActiveNoSOF |
157 |
Covered |
T1,T2,T3 |
| LinkPowered->LinkDisconnected |
145 |
Covered |
T7,T8,T9 |
| LinkPowered->LinkPoweredSuspended |
163 |
Covered |
T73,T97,T98 |
| LinkPowered->LinkResuming |
161 |
Covered |
T70,T96,T73 |
| LinkPoweredSuspended->LinkActiveNoSOF |
169 |
Not Covered |
|
| LinkPoweredSuspended->LinkDisconnected |
145 |
Covered |
T98,T105,T106 |
| LinkPoweredSuspended->LinkPowered |
172 |
Covered |
T73,T97,T99 |
| LinkResuming->LinkActiveNoSOF |
186 |
Covered |
T8,T68,T70 |
| LinkResuming->LinkDisconnected |
145 |
Not Covered |
|
| LinkSuspended->LinkActiveNoSOF |
214 |
Not Covered |
|
| LinkSuspended->LinkDisconnected |
145 |
Covered |
T7,T62,T9 |
| LinkSuspended->LinkResuming |
216 |
Covered |
T8,T68,T101 |
Summary for FSM :: link_rst_state_q
| Total | Covered | Percent | |
| States |
3 |
3 |
100.00 |
(Not included in score) |
| Transitions |
4 |
4 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: link_rst_state_q
| states | Line No. | Covered | Tests |
| NoRst |
262 |
Covered |
T1,T2,T3 |
| RstCnt |
254 |
Covered |
T1,T2,T3 |
| RstPend |
266 |
Covered |
T1,T2,T3 |
| transitions | Line No. | Covered | Tests |
| NoRst->RstCnt |
254 |
Covered |
T1,T2,T3 |
| RstCnt->NoRst |
262 |
Covered |
T1,T2,T28 |
| RstCnt->RstPend |
266 |
Covered |
T1,T2,T3 |
| RstPend->NoRst |
277 |
Covered |
T1,T2,T3 |
Summary for FSM :: link_inac_state_q
| Total | Covered | Percent | |
| States |
3 |
3 |
100.00 |
(Not included in score) |
| Transitions |
4 |
4 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: link_inac_state_q
| states | Line No. | Covered | Tests |
| Active |
323 |
Covered |
T1,T2,T3 |
| InactCnt |
316 |
Covered |
T1,T2,T3 |
| InactPend |
326 |
Covered |
T7,T8,T62 |
| transitions | Line No. | Covered | Tests |
| Active->InactCnt |
316 |
Covered |
T1,T2,T3 |
| InactCnt->Active |
323 |
Covered |
T1,T2,T3 |
| InactCnt->InactPend |
326 |
Covered |
T7,T8,T62 |
| InactPend->Active |
337 |
Covered |
T7,T8,T62 |
Branch Coverage for Module :
usbdev_linkstate
| Line No. | Total | Covered | Percent |
| Branches |
|
56 |
49 |
87.50 |
| TERNARY |
135 |
2 |
2 |
100.00 |
| IF |
144 |
22 |
18 |
81.82 |
| IF |
231 |
2 |
2 |
100.00 |
| CASE |
250 |
9 |
8 |
88.89 |
| IF |
292 |
2 |
2 |
100.00 |
| CASE |
311 |
9 |
7 |
77.78 |
| IF |
348 |
2 |
2 |
100.00 |
| IF |
367 |
4 |
4 |
100.00 |
| IF |
380 |
4 |
4 |
100.00 |
135 assign monitor_inac = see_pwr_sense ? ((link_state_q == LinkPowered) | link_active_o) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
144 if (!see_pwr_sense || !usb_pullup_en_i) begin
-1-
145 link_state_d = LinkDisconnected;
==>
146 end else begin
147 unique case (link_state_q)
-2-
148 // No USB supply detected (USB spec: Attached)
149 LinkDisconnected: begin
150 if (see_pwr_sense & usb_pullup_en_i) begin
-3-
151 link_state_d = LinkPowered;
==>
152 end
MISSING_ELSE
==>
153 end
154
155 LinkPowered: begin
156 if (ev_reset) begin
-4-
157 link_state_d = LinkActiveNoSOF;
==>
158 end else if (resume_link_active_i) begin
-5-
159 // Software-directed jump to resume from LinkSuspended, in case
160 // this module was previously powered down.
161 link_state_d = LinkResuming;
==>
162 end else if (ev_bus_inactive) begin
-6-
163 link_state_d = LinkPoweredSuspended;
==>
164 end
MISSING_ELSE
==>
165 end
166
167 LinkPoweredSuspended: begin
168 if (ev_reset) begin
-7-
169 link_state_d = LinkActiveNoSOF;
==>
170 end else if (ev_bus_active) begin
-8-
171 link_resume_o = 1;
==>
172 link_state_d = LinkPowered;
173 end
MISSING_ELSE
==>
174 end
175
176 // An event occurred that brought the link out of LinkSuspended, but
177 // the end-of-resume signaling may not have occurred yet.
178 // Park here before starting to count towards not seeing SOF. Wait for
179 // the end of resume signaling before expecting SOF. The host will
180 // return the link to idle after a low-speed EOP. Instead of trying to
181 // capture the termination of resume signaling direclty, wait for
182 // any J / idle symbol (or a bus reset).
183 LinkResuming: begin
184 if (rx_j_det_i | ev_reset) begin
-9-
185 link_resume_o = 1;
==>
186 link_state_d = LinkActiveNoSOF;
187 end
MISSING_ELSE
==>
188 end
189
190 // Active but not yet seen a frame
191 // One reason for getting stuck here is the host thinks it is a LS link
192 // which could happen if the flipped bit does not match the actual pins
193 // Annother is the SI is bad so good data is not recovered from the link
194 LinkActiveNoSOF: begin
195 if (ev_bus_inactive) begin
-10-
196 link_state_d = LinkSuspended;
==>
197 end else if (sof_detected_i) begin
-11-
198 link_state_d = LinkActive;
==>
199 end
MISSING_ELSE
==>
200 end
201
202 // Active (USB spec: Default / Address / Configured)
203 LinkActive: begin
204 if (ev_bus_inactive) begin
-12-
205 link_state_d = LinkSuspended;
==>
206 end else if (ev_reset) begin
-13-
207 link_state_d = LinkActiveNoSOF;
==>
208 end
MISSING_ELSE
==>
209 end
210
211 LinkSuspended: begin
212 if (ev_reset) begin
-14-
213 link_resume_o = 1;
==>
214 link_state_d = LinkActiveNoSOF;
215 end else if (ev_bus_active) begin
-15-
216 link_state_d = LinkResuming;
==>
217 end
MISSING_ELSE
==>
218 end
219
220 default: begin
221 link_state_d = LinkDisconnected;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | Status | Tests |
| 1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
LinkDisconnected |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
LinkDisconnected |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| 0 |
LinkPowered |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
LinkPowered |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T70,T96,T73 |
| 0 |
LinkPowered |
- |
0 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T73,T97,T98 |
| 0 |
LinkPowered |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
LinkPoweredSuspended |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| 0 |
LinkPoweredSuspended |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T73,T97,T99 |
| 0 |
LinkPoweredSuspended |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T73,T97,T98 |
| 0 |
LinkResuming |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T8,T68,T70 |
| 0 |
LinkResuming |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T8,T68,T70 |
| 0 |
LinkActiveNoSOF |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T7,T8,T9 |
| 0 |
LinkActiveNoSOF |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
Covered |
T41,T7,T100 |
| 0 |
LinkActiveNoSOF |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
LinkActive |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T62,T101,T11 |
| 0 |
LinkActive |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
Covered |
T10,T102,T103 |
| 0 |
LinkActive |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
Covered |
T41,T7,T100 |
| 0 |
LinkSuspended |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Not Covered |
|
| 0 |
LinkSuspended |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
Covered |
T8,T68,T101 |
| 0 |
LinkSuspended |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
Covered |
T7,T8,T62 |
| 0 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
231 if (!rst_ni) begin
-1-
232 link_state_q <= LinkDisconnected;
==>
233 end else begin
234 link_state_q <= link_state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
250 unique case (link_rst_state_q)
-1-
251 // No reset signal detected
252 NoRst: begin
253 if (see_se0) begin
-2-
254 link_rst_state_d = RstCnt;
==>
255 link_rst_timer_d = 0;
256 end
MISSING_ELSE
==>
257 end
258
259 // Reset signal detected -> counting
260 RstCnt: begin
261 if (!see_se0) begin
-3-
262 link_rst_state_d = NoRst;
==>
263 end else begin
264 if (us_tick_i) begin
-4-
265 if (link_rst_timer_q == RESET_TIMEOUT) begin
-5-
266 link_rst_state_d = RstPend;
==>
267 end else begin
268 link_rst_timer_d = link_rst_timer_q + 1;
==>
269 end
270 end
MISSING_ELSE
==>
271 end
272 end
273
274 // Detected reset -> wait for falling edge
275 RstPend: begin
276 if (!see_se0) begin
-6-
277 link_rst_state_d = NoRst;
==>
278 ev_reset = 1'b1;
279 end
MISSING_ELSE
==>
280 link_reset = 1'b1;
281 end
282
283 default : link_rst_state_d = NoRst;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
| NoRst |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| NoRst |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| RstCnt |
- |
1 |
- |
- |
- |
Covered |
T1,T2,T28 |
| RstCnt |
- |
0 |
1 |
1 |
- |
Covered |
T1,T2,T3 |
| RstCnt |
- |
0 |
1 |
0 |
- |
Covered |
T1,T2,T3 |
| RstCnt |
- |
0 |
0 |
- |
- |
Covered |
T1,T2,T3 |
| RstPend |
- |
- |
- |
- |
1 |
Covered |
T1,T2,T3 |
| RstPend |
- |
- |
- |
- |
0 |
Covered |
T1,T2,T3 |
| default |
- |
- |
- |
- |
- |
Not Covered |
|
292 if (!rst_ni) begin
-1-
293 link_rst_state_q <= NoRst;
==>
294 link_rst_timer_q <= 0;
295 end else begin
296 link_rst_state_q <= link_rst_state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
311 unique case (link_inac_state_q)
-1-
312 // Active or disabled
313 Active: begin
314 link_inac_timer_d = 0;
315 if (!ev_bus_active && monitor_inac) begin
-2-
316 link_inac_state_d = InactCnt;
==>
317 end
MISSING_ELSE
==>
318 end
319
320 // Got an inactivity signal -> count duration
321 InactCnt: begin
322 if (ev_bus_active || !monitor_inac) begin
-3-
323 link_inac_state_d = Active;
==>
324 end else if (us_tick_i) begin
-4-
325 if (link_inac_timer_q == SUSPEND_TIMEOUT) begin
-5-
326 link_inac_state_d = InactPend;
==>
327 ev_bus_inactive = 1;
328 end else begin
329 link_inac_timer_d = link_inac_timer_q + 1;
==>
330 end
331 end
MISSING_ELSE
==>
332 end
333
334 // Counter expired & event sent, wait here
335 InactPend: begin
336 if (ev_bus_active || !monitor_inac) begin
-6-
337 link_inac_state_d = Active;
==>
338 end
MISSING_ELSE
==>
339 end
340
341 default : link_inac_state_d = Active;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
| Active |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| Active |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| InactCnt |
- |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| InactCnt |
- |
0 |
1 |
1 |
- |
Covered |
T7,T8,T62 |
| InactCnt |
- |
0 |
1 |
0 |
- |
Covered |
T1,T2,T3 |
| InactCnt |
- |
0 |
0 |
- |
- |
Covered |
T1,T2,T3 |
| InactPend |
- |
- |
- |
- |
1 |
Covered |
T7,T8,T62 |
| InactPend |
- |
- |
- |
- |
0 |
Not Covered |
|
| default |
- |
- |
- |
- |
- |
Not Covered |
|
348 if (!rst_ni) begin
-1-
349 link_inac_state_q <= Active;
==>
350 link_inac_timer_q <= 0;
351 end else begin
352 link_inac_state_q <= link_inac_state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
367 if (!rst_ni) begin
-1-
368 missed_sof_count <= '0;
==>
369 end else begin
370 if (sof_detected_i || !link_active_o || link_reset) begin
-2-
371 missed_sof_count <= '0;
==>
372 end else if (sof_missed_o && !host_lost_o) begin
-3-
373 missed_sof_count <= missed_sof_count + 1;
==>
374 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T7,T8,T49 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
380 if (!rst_ni) begin
-1-
381 missing_sof_timer <= '0;
==>
382 end else begin
383 if (sof_missed_o || sof_detected_i || !link_active_o || link_reset) begin
-2-
384 missing_sof_timer <= '0;
==>
385 end else if (us_tick_i) begin
-3-
386 missing_sof_timer <= missing_sof_timer + 1;
==>
387 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
usbdev_linkstate
Assertion Details
LincInacStateValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
580384169 |
580090083 |
0 |
0 |
| T1 |
7293 |
7243 |
0 |
0 |
| T2 |
7698 |
7601 |
0 |
0 |
| T3 |
6346 |
6265 |
0 |
0 |
| T28 |
8471 |
8384 |
0 |
0 |
| T29 |
21708 |
21622 |
0 |
0 |
| T30 |
38925 |
38834 |
0 |
0 |
| T31 |
7561 |
7478 |
0 |
0 |
| T32 |
48746 |
48670 |
0 |
0 |
| T41 |
7600 |
7502 |
0 |
0 |
| T42 |
1581 |
1491 |
0 |
0 |
LinkRstStateValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
580384169 |
580090083 |
0 |
0 |
| T1 |
7293 |
7243 |
0 |
0 |
| T2 |
7698 |
7601 |
0 |
0 |
| T3 |
6346 |
6265 |
0 |
0 |
| T28 |
8471 |
8384 |
0 |
0 |
| T29 |
21708 |
21622 |
0 |
0 |
| T30 |
38925 |
38834 |
0 |
0 |
| T31 |
7561 |
7478 |
0 |
0 |
| T32 |
48746 |
48670 |
0 |
0 |
| T41 |
7600 |
7502 |
0 |
0 |
| T42 |
1581 |
1491 |
0 |
0 |
LinkStateValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
580384169 |
580090083 |
0 |
0 |
| T1 |
7293 |
7243 |
0 |
0 |
| T2 |
7698 |
7601 |
0 |
0 |
| T3 |
6346 |
6265 |
0 |
0 |
| T28 |
8471 |
8384 |
0 |
0 |
| T29 |
21708 |
21622 |
0 |
0 |
| T30 |
38925 |
38834 |
0 |
0 |
| T31 |
7561 |
7478 |
0 |
0 |
| T32 |
48746 |
48670 |
0 |
0 |
| T41 |
7600 |
7502 |
0 |
0 |
| T42 |
1581 |
1491 |
0 |
0 |
Line Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 101 | 101 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| ALWAYS | 139 | 31 | 31 | 100.00 |
| ALWAYS | 231 | 3 | 3 | 100.00 |
| ALWAYS | 245 | 18 | 18 | 100.00 |
| CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
| ALWAYS | 292 | 5 | 5 | 100.00 |
| ALWAYS | 307 | 16 | 16 | 100.00 |
| ALWAYS | 348 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 365 | 1 | 1 | 100.00 |
| ALWAYS | 367 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 378 | 1 | 1 | 100.00 |
| ALWAYS | 380 | 6 | 6 | 100.00 |
91
92 1/1 assign link_disconnect_o = (link_state_q == LinkDisconnected);
Tests: T1 T2 T3
93 1/1 assign link_powered_o = see_pwr_sense;
Tests: T1 T2 T3
94 1/1 assign link_suspend_o = (link_state_q == LinkSuspended ||
Tests: T1 T2 T3
95 link_state_q == LinkPoweredSuspended);
96 1/1 assign link_active_o = (link_state_q == LinkActive) ||
Tests: T1 T2 T3
97 (link_state_q == LinkActiveNoSOF);
98 // Link state is stable, so we can output it to the register
99 1/1 assign link_state_o = link_state_q;
Tests: T1 T2 T3
100
101 // If the PHY reflects the line state on rx pins when the device is driving
102 // then the usb_oe_i check isn't needed here. But it seems best to do the check
103 // to be robust in the face of different PHY designs.
104 logic see_se0, line_se0_raw;
105 1/1 assign line_se0_raw = (usb_dn_i == 1'b0) & (usb_dp_i == 1'b0) & (usb_oe_i == 1'b0);
Tests: T1 T2 T3
106
107 // four ticks is a bit time
108 // Could completely filter out 2-cycle EOP SE0 here but
109 // does not seem needed
110 prim_filter #(
111 .AsyncOn(0), // No synchronizer required
112 .Cycles(6)
113 ) filter_se0 (
114 .clk_i (clk_48mhz_i),
115 .rst_ni (rst_ni),
116 .enable_i (1'b1),
117 .filter_i (line_se0_raw),
118 .filter_o (see_se0)
119 );
120
121 prim_filter #(
122 .AsyncOn(0), // No synchronizer required
123 .Cycles(6)
124 ) filter_pwr_sense (
125 .clk_i (clk_48mhz_i),
126 .rst_ni (rst_ni),
127 .enable_i (1'b1),
128 .filter_i (usb_sense_i),
129 .filter_o (see_pwr_sense)
130 );
131
132 // Simple events
133 1/1 assign ev_bus_active = !rx_idle_det_i;
Tests: T1 T2 T3
134
135 1/1 assign monitor_inac = see_pwr_sense ? ((link_state_q == LinkPowered) | link_active_o) :
Tests: T1 T2 T3
136 1'b0;
137
138 always_comb begin
139 1/1 link_state_d = link_state_q;
Tests: T1 T2 T3
140 1/1 link_resume_o = 0;
Tests: T1 T2 T3
141
142 // If VBUS ever goes away the link has disconnected (likewise if the
143 // pull-up goes away / user requested disconnection)
144 1/1 if (!see_pwr_sense || !usb_pullup_en_i) begin
Tests: T1 T2 T3
145 1/1 link_state_d = LinkDisconnected;
Tests: T1 T2 T3
146 end else begin
147 1/1 unique case (link_state_q)
Tests: T1 T2 T3
148 // No USB supply detected (USB spec: Attached)
149 LinkDisconnected: begin
150 1/1 if (see_pwr_sense & usb_pullup_en_i) begin
Tests: T1 T2 T3
151 1/1 link_state_d = LinkPowered;
Tests: T1 T2 T3
152 end
==> MISSING_ELSE
153 end
154
155 LinkPowered: begin
156 1/1 if (ev_reset) begin
Tests: T1 T2 T3
157 1/1 link_state_d = LinkActiveNoSOF;
Tests: T1 T2 T3
158 1/1 end else if (resume_link_active_i) begin
Tests: T1 T2 T3
159 // Software-directed jump to resume from LinkSuspended, in case
160 // this module was previously powered down.
161 1/1 link_state_d = LinkResuming;
Tests: T70 T96 T73
162 1/1 end else if (ev_bus_inactive) begin
Tests: T1 T2 T3
163 1/1 link_state_d = LinkPoweredSuspended;
Tests: T73 T97 T98
164 end
MISSING_ELSE
165 end
166
167 LinkPoweredSuspended: begin
168 1/1 if (ev_reset) begin
Tests: T73 T97 T98
169 excluded link_state_d = LinkActiveNoSOF;
Exclude Annotation: rtl/usbdev_linkstate.sv, LineNumber: 169
170 1/1 end else if (ev_bus_active) begin
Tests: T73 T97 T98
171 1/1 link_resume_o = 1;
Tests: T73 T97 T99
172 1/1 link_state_d = LinkPowered;
Tests: T73 T97 T99
173 end
MISSING_ELSE
174 end
175
176 // An event occurred that brought the link out of LinkSuspended, but
177 // the end-of-resume signaling may not have occurred yet.
178 // Park here before starting to count towards not seeing SOF. Wait for
179 // the end of resume signaling before expecting SOF. The host will
180 // return the link to idle after a low-speed EOP. Instead of trying to
181 // capture the termination of resume signaling direclty, wait for
182 // any J / idle symbol (or a bus reset).
183 LinkResuming: begin
184 1/1 if (rx_j_det_i | ev_reset) begin
Tests: T8 T68 T70
185 1/1 link_resume_o = 1;
Tests: T8 T68 T70
186 1/1 link_state_d = LinkActiveNoSOF;
Tests: T8 T68 T70
187 end
MISSING_ELSE
188 end
189
190 // Active but not yet seen a frame
191 // One reason for getting stuck here is the host thinks it is a LS link
192 // which could happen if the flipped bit does not match the actual pins
193 // Annother is the SI is bad so good data is not recovered from the link
194 LinkActiveNoSOF: begin
195 1/1 if (ev_bus_inactive) begin
Tests: T1 T2 T3
196 1/1 link_state_d = LinkSuspended;
Tests: T7 T8 T9
197 1/1 end else if (sof_detected_i) begin
Tests: T1 T2 T3
198 1/1 link_state_d = LinkActive;
Tests: T41 T7 T100
199 end
MISSING_ELSE
200 end
201
202 // Active (USB spec: Default / Address / Configured)
203 LinkActive: begin
204 1/1 if (ev_bus_inactive) begin
Tests: T41 T7 T100
205 1/1 link_state_d = LinkSuspended;
Tests: T62 T101 T11
206 1/1 end else if (ev_reset) begin
Tests: T41 T7 T100
207 1/1 link_state_d = LinkActiveNoSOF;
Tests: T10 T102 T103
208 end
MISSING_ELSE
209 end
210
211 LinkSuspended: begin
212 1/1 if (ev_reset) begin
Tests: T7 T8 T62
213 excluded link_resume_o = 1;
Exclude Annotation: rtl/usbdev_linkstate.sv, LineNumber: 213
214 excluded link_state_d = LinkActiveNoSOF;
Exclude Annotation: rtl/usbdev_linkstate.sv, LineNumber: 213
215 1/1 end else if (ev_bus_active) begin
Tests: T7 T8 T62
216 1/1 link_state_d = LinkResuming;
Tests: T8 T68 T101
217 end
MISSING_ELSE
218 end
219
220 default: begin
221 link_state_d = LinkDisconnected;
Exclude Annotation: VC_COV_UNR
222 end
223 endcase // case (link_state_q)
224 end
225 end
226
227 `ASSERT(LinkStateValid_A, link_state_q inside {LinkDisconnected, LinkPowered,
228 LinkPoweredSuspended, LinkResuming, LinkActiveNoSOF, LinkActive, LinkSuspended}, clk_48mhz_i)
229
230 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
231 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
232 1/1 link_state_q <= LinkDisconnected;
Tests: T1 T2 T3
233 end else begin
234 1/1 link_state_q <= link_state_d;
Tests: T1 T2 T3
235 end
236 end
237
238 /////////////////////
239 // Reset detection //
240 /////////////////////
241 // Here we clean up the SE0 signal and generate a single ev_reset at
242 // the end of a valid reset
243
244 always_comb begin : proc_rst_fsm
245 1/1 link_rst_state_d = link_rst_state_q;
Tests: T1 T2 T3
246 1/1 link_rst_timer_d = link_rst_timer_q;
Tests: T1 T2 T3
247 1/1 ev_reset = 1'b0;
Tests: T1 T2 T3
248 1/1 link_reset = 1'b0;
Tests: T1 T2 T3
249
250 1/1 unique case (link_rst_state_q)
Tests: T1 T2 T3
251 // No reset signal detected
252 NoRst: begin
253 1/1 if (see_se0) begin
Tests: T1 T2 T3
254 1/1 link_rst_state_d = RstCnt;
Tests: T1 T2 T3
255 1/1 link_rst_timer_d = 0;
Tests: T1 T2 T3
256 end
MISSING_ELSE
257 end
258
259 // Reset signal detected -> counting
260 RstCnt: begin
261 1/1 if (!see_se0) begin
Tests: T1 T2 T3
262 1/1 link_rst_state_d = NoRst;
Tests: T1 T2 T28
263 end else begin
264 1/1 if (us_tick_i) begin
Tests: T1 T2 T3
265 1/1 if (link_rst_timer_q == RESET_TIMEOUT) begin
Tests: T1 T2 T3
266 1/1 link_rst_state_d = RstPend;
Tests: T1 T2 T3
267 end else begin
268 1/1 link_rst_timer_d = link_rst_timer_q + 1;
Tests: T1 T2 T3
269 end
270 end
MISSING_ELSE
271 end
272 end
273
274 // Detected reset -> wait for falling edge
275 RstPend: begin
276 1/1 if (!see_se0) begin
Tests: T1 T2 T3
277 1/1 link_rst_state_d = NoRst;
Tests: T1 T2 T3
278 1/1 ev_reset = 1'b1;
Tests: T1 T2 T3
279 end
MISSING_ELSE
280 1/1 link_reset = 1'b1;
Tests: T1 T2 T3
281 end
282
283 default : link_rst_state_d = NoRst;
Exclude Annotation: VC_COV_UNR
284 endcase
285 end
286
287 `ASSERT(LinkRstStateValid_A, link_rst_state_q inside {NoRst, RstCnt, RstPend}, clk_48mhz_i)
288
289 1/1 assign link_reset_o = link_reset;
Tests: T1 T2 T3
290
291 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin : proc_reg_rst
292 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
293 1/1 link_rst_state_q <= NoRst;
Tests: T1 T2 T3
294 1/1 link_rst_timer_q <= 0;
Tests: T1 T2 T3
295 end else begin
296 1/1 link_rst_state_q <= link_rst_state_d;
Tests: T1 T2 T3
297 1/1 link_rst_timer_q <= link_rst_timer_d;
Tests: T1 T2 T3
298 end
299 end
300
301 ////////////////////
302 // Idle detection //
303 ////////////////////
304 // Here we clean up the idle signal and generate a single ev_bus_inactive
305 // after the timer expires
306 always_comb begin : proc_idle_det
307 1/1 link_inac_state_d = link_inac_state_q;
Tests: T1 T2 T3
308 1/1 link_inac_timer_d = link_inac_timer_q;
Tests: T1 T2 T3
309 1/1 ev_bus_inactive = 0;
Tests: T1 T2 T3
310
311 1/1 unique case (link_inac_state_q)
Tests: T1 T2 T3
312 // Active or disabled
313 Active: begin
314 1/1 link_inac_timer_d = 0;
Tests: T1 T2 T3
315 1/1 if (!ev_bus_active && monitor_inac) begin
Tests: T1 T2 T3
316 1/1 link_inac_state_d = InactCnt;
Tests: T1 T2 T3
317 end
MISSING_ELSE
318 end
319
320 // Got an inactivity signal -> count duration
321 InactCnt: begin
322 1/1 if (ev_bus_active || !monitor_inac) begin
Tests: T1 T2 T3
323 1/1 link_inac_state_d = Active;
Tests: T1 T2 T3
324 1/1 end else if (us_tick_i) begin
Tests: T1 T2 T3
325 1/1 if (link_inac_timer_q == SUSPEND_TIMEOUT) begin
Tests: T1 T2 T3
326 1/1 link_inac_state_d = InactPend;
Tests: T7 T8 T62
327 1/1 ev_bus_inactive = 1;
Tests: T7 T8 T62
328 end else begin
329 1/1 link_inac_timer_d = link_inac_timer_q + 1;
Tests: T1 T2 T3
330 end
331 end
MISSING_ELSE
332 end
333
334 // Counter expired & event sent, wait here
335 InactPend: begin
336 1/1 if (ev_bus_active || !monitor_inac) begin
Tests: T7 T8 T62
337 1/1 link_inac_state_d = Active;
Tests: T7 T8 T62
338 end
==> MISSING_ELSE
339 end
340
341 default : link_inac_state_d = Active;
Exclude Annotation: VC_COV_UNR
342 endcase
343 end
344
345 `ASSERT(LincInacStateValid_A, link_inac_state_q inside {Active, InactCnt, InactPend}, clk_48mhz_i)
346
347 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin : proc_reg_idle_det
348 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
349 1/1 link_inac_state_q <= Active;
Tests: T1 T2 T3
350 1/1 link_inac_timer_q <= 0;
Tests: T1 T2 T3
351 end else begin
352 1/1 link_inac_state_q <= link_inac_state_d;
Tests: T1 T2 T3
353 1/1 link_inac_timer_q <= link_inac_timer_d;
Tests: T1 T2 T3
354 end
355 end
356
357 /////////////////////////////////////////
358 // Host loss and missing sof detection //
359 /////////////////////////////////////////
360 // sof_missed if no SOF was observed in 1.005ms and the link is active
361 // host_lost if 4 frames have gone by without observing a SOF
362 logic [2:0] missed_sof_count;
363 logic [9:0] missing_sof_timer;
364
365 1/1 assign host_lost_o = missed_sof_count[2];
Tests: T1 T2 T3
366 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
367 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
368 1/1 missed_sof_count <= '0;
Tests: T1 T2 T3
369 end else begin
370 1/1 if (sof_detected_i || !link_active_o || link_reset) begin
Tests: T1 T2 T3
371 1/1 missed_sof_count <= '0;
Tests: T1 T2 T3
372 1/1 end else if (sof_missed_o && !host_lost_o) begin
Tests: T1 T2 T3
373 1/1 missed_sof_count <= missed_sof_count + 1;
Tests: T7 T8 T49
374 end
MISSING_ELSE
375 end
376 end
377
378 1/1 assign sof_missed_o = (missing_sof_timer == SOF_TIMEOUT);
Tests: T1 T2 T3
379 always_ff @(posedge clk_48mhz_i or negedge rst_ni) begin
380 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
381 1/1 missing_sof_timer <= '0;
Tests: T1 T2 T3
382 end else begin
383 1/1 if (sof_missed_o || sof_detected_i || !link_active_o || link_reset) begin
Tests: T1 T2 T3
384 1/1 missing_sof_timer <= '0;
Tests: T1 T2 T3
385 1/1 end else if (us_tick_i) begin
Tests: T1 T2 T3
386 1/1 missing_sof_timer <= missing_sof_timer + 1;
Tests: T1 T2 T3
387 end
MISSING_ELSE
Cond Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate
| Total | Covered | Percent |
|---|
| Conditions | 67 | 64 | 95.52 |
| Logical | 67 | 64 | 95.52 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 92
EXPRESSION (link_state_q == LinkDisconnected)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION ((link_state_q == LinkSuspended) || (link_state_q == LinkPoweredSuspended))
---------------1--------------- -------------------2------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T73,T97,T98 |
| 1 | 0 | Covered | T7,T8,T62 |
LINE 94
SUB-EXPRESSION (link_state_q == LinkSuspended)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T62 |
LINE 94
SUB-EXPRESSION (link_state_q == LinkPoweredSuspended)
-------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T73,T97,T98 |
LINE 96
EXPRESSION ((link_state_q == LinkActive) || (link_state_q == LinkActiveNoSOF))
--------------1------------- ----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T41,T7,T100 |
LINE 96
SUB-EXPRESSION (link_state_q == LinkActive)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T41,T7,T100 |
LINE 96
SUB-EXPRESSION (link_state_q == LinkActiveNoSOF)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 105
EXPRESSION ((usb_dn_i == 1'b0) & (usb_dp_i == 1'b0) & (usb_oe_i == 1'b0))
---------1-------- ---------2-------- ---------3--------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T28 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T1,T28,T29 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 105
SUB-EXPRESSION (usb_dn_i == 1'b0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 105
SUB-EXPRESSION (usb_dp_i == 1'b0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 105
SUB-EXPRESSION (usb_oe_i == 1'b0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 135
EXPRESSION (see_pwr_sense ? ((link_state_q == LinkPowered) | link_active_o) : 1'b0)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION ((link_state_q == LinkPowered) | link_active_o)
--------------1-------------- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (link_state_q == LinkPowered)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 144
EXPRESSION (((!see_pwr_sense)) || ((!usb_pullup_en_i)))
---------1-------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T33,T7,T17 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 150
EXPRESSION (see_pwr_sense & usb_pullup_en_i)
------1------ -------2-------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 184
EXPRESSION (rx_j_det_i | ev_reset)
-----1---- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T8,T68,T70 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T8,T68,T70 |
LINE 265
EXPRESSION (link_rst_timer_q == RESET_TIMEOUT)
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 315
EXPRESSION (((!ev_bus_active)) && monitor_inac)
---------1-------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T7,T8,T62 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 322
EXPRESSION (ev_bus_active || ((!monitor_inac)))
------1------ --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T7,T8,T9 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 325
EXPRESSION (link_inac_timer_q == SUSPEND_TIMEOUT)
-------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T62 |
LINE 336
EXPRESSION (ev_bus_active || ((!monitor_inac)))
------1------ --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Covered | T7,T8,T62 |
| 1 | 0 | Not Covered | |
LINE 370
EXPRESSION (sof_detected_i || ((!link_active_o)) || link_reset)
-------1------ ---------2-------- -----3----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T1,T2,T3 |
| 0 | 1 | 0 | Covered | T1,T2,T3 |
| 1 | 0 | 0 | Covered | T41,T7,T100 |
LINE 372
EXPRESSION (sof_missed_o && ((!host_lost_o)))
------1----- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T68,T69,T104 |
| 1 | 1 | Covered | T7,T8,T49 |
LINE 378
EXPRESSION (missing_sof_timer == SOF_TIMEOUT)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T49 |
LINE 383
EXPRESSION (sof_missed_o || sof_detected_i || ((!link_active_o)) || link_reset)
------1----- -------2------ ---------3-------- -----4----
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | 0 | 0 | Covered | T41,T7,T100 |
| 1 | 0 | 0 | 0 | Covered | T7,T8,T49 |
FSM Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate
Summary for FSM :: link_state_q
| Total | Covered | Percent | |
| States |
7 |
7 |
100.00 |
(Not included in score) |
| Transitions |
17 |
16 |
94.12 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: link_state_q
| states | Line No. | Covered | Tests |
| LinkActive |
198 |
Covered |
T41,T7,T100 |
| LinkActiveNoSOF |
157 |
Covered |
T1,T2,T3 |
| LinkDisconnected |
145 |
Covered |
T1,T2,T3 |
| LinkPowered |
151 |
Covered |
T1,T2,T3 |
| LinkPoweredSuspended |
163 |
Covered |
T73,T97,T98 |
| LinkResuming |
161 |
Covered |
T8,T68,T70 |
| LinkSuspended |
196 |
Covered |
T7,T8,T62 |
| transitions | Line No. | Covered | Tests | Exclude Annotation |
| LinkActive->LinkActiveNoSOF |
207 |
Covered |
T10,T102,T103 |
|
| LinkActive->LinkDisconnected |
145 |
Covered |
T41,T7,T66 |
|
| LinkActive->LinkSuspended |
205 |
Covered |
T62,T101,T11 |
|
| LinkActiveNoSOF->LinkActive |
198 |
Covered |
T41,T7,T100 |
|
| LinkActiveNoSOF->LinkDisconnected |
145 |
Covered |
T8,T9,T70 |
|
| LinkActiveNoSOF->LinkSuspended |
196 |
Covered |
T7,T8,T9 |
|
| LinkDisconnected->LinkPowered |
151 |
Covered |
T1,T2,T3 |
|
| LinkPowered->LinkActiveNoSOF |
157 |
Covered |
T1,T2,T3 |
|
| LinkPowered->LinkDisconnected |
145 |
Covered |
T7,T8,T9 |
|
| LinkPowered->LinkPoweredSuspended |
163 |
Covered |
T73,T97,T98 |
|
| LinkPowered->LinkResuming |
161 |
Covered |
T70,T96,T73 |
|
| LinkPoweredSuspended->LinkActiveNoSOF |
169 |
Excluded |
|
Signal `ev_reset` is delayed relative to the signal `ev_bus_active` which also triggers. |
| LinkPoweredSuspended->LinkDisconnected |
145 |
Covered |
T98,T105,T106 |
|
| LinkPoweredSuspended->LinkPowered |
172 |
Covered |
T73,T97,T99 |
|
| LinkResuming->LinkActiveNoSOF |
186 |
Covered |
T8,T68,T70 |
|
| LinkResuming->LinkDisconnected |
145 |
Not Covered |
|
|
| LinkSuspended->LinkActiveNoSOF |
214 |
Excluded |
|
Signal `ev_reset` is delayed relative to the signal `ev_bus_active` which also triggers. |
| LinkSuspended->LinkDisconnected |
145 |
Covered |
T7,T62,T9 |
|
| LinkSuspended->LinkResuming |
216 |
Covered |
T8,T68,T101 |
|
Summary for FSM :: link_rst_state_q
| Total | Covered | Percent | |
| States |
3 |
3 |
100.00 |
(Not included in score) |
| Transitions |
4 |
4 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: link_rst_state_q
| states | Line No. | Covered | Tests |
| NoRst |
262 |
Covered |
T1,T2,T3 |
| RstCnt |
254 |
Covered |
T1,T2,T3 |
| RstPend |
266 |
Covered |
T1,T2,T3 |
| transitions | Line No. | Covered | Tests |
| NoRst->RstCnt |
254 |
Covered |
T1,T2,T3 |
| RstCnt->NoRst |
262 |
Covered |
T1,T2,T28 |
| RstCnt->RstPend |
266 |
Covered |
T1,T2,T3 |
| RstPend->NoRst |
277 |
Covered |
T1,T2,T3 |
Summary for FSM :: link_inac_state_q
| Total | Covered | Percent | |
| States |
3 |
3 |
100.00 |
(Not included in score) |
| Transitions |
4 |
4 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: link_inac_state_q
| states | Line No. | Covered | Tests |
| Active |
323 |
Covered |
T1,T2,T3 |
| InactCnt |
316 |
Covered |
T1,T2,T3 |
| InactPend |
326 |
Covered |
T7,T8,T62 |
| transitions | Line No. | Covered | Tests |
| Active->InactCnt |
316 |
Covered |
T1,T2,T3 |
| InactCnt->Active |
323 |
Covered |
T1,T2,T3 |
| InactCnt->InactPend |
326 |
Covered |
T7,T8,T62 |
| InactPend->Active |
337 |
Covered |
T7,T8,T62 |
Branch Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate
| Line No. | Total | Covered | Percent |
| Branches |
|
50 |
49 |
98.00 |
| TERNARY |
135 |
2 |
2 |
100.00 |
| IF |
144 |
18 |
18 |
100.00 |
| IF |
231 |
2 |
2 |
100.00 |
| CASE |
250 |
8 |
8 |
100.00 |
| IF |
292 |
2 |
2 |
100.00 |
| CASE |
311 |
8 |
7 |
87.50 |
| IF |
348 |
2 |
2 |
100.00 |
| IF |
367 |
4 |
4 |
100.00 |
| IF |
380 |
4 |
4 |
100.00 |
135 assign monitor_inac = see_pwr_sense ? ((link_state_q == LinkPowered) | link_active_o) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
144 if (!see_pwr_sense || !usb_pullup_en_i) begin
-1-
145 link_state_d = LinkDisconnected;
==>
146 end else begin
147 unique case (link_state_q)
-2-
148 // No USB supply detected (USB spec: Attached)
149 LinkDisconnected: begin
150 if (see_pwr_sense & usb_pullup_en_i) begin
-3-
151 link_state_d = LinkPowered;
==>
152 end
MISSING_ELSE
==> (Excluded)
Exclude Annotation: VC_COV_UNR
153 end
154
155 LinkPowered: begin
156 if (ev_reset) begin
-4-
157 link_state_d = LinkActiveNoSOF;
==>
158 end else if (resume_link_active_i) begin
-5-
159 // Software-directed jump to resume from LinkSuspended, in case
160 // this module was previously powered down.
161 link_state_d = LinkResuming;
==>
162 end else if (ev_bus_inactive) begin
-6-
163 link_state_d = LinkPoweredSuspended;
==>
164 end
MISSING_ELSE
==>
165 end
166
167 LinkPoweredSuspended: begin
168 if (ev_reset) begin
-7-
169 link_state_d = LinkActiveNoSOF;
==> (Excluded)
Exclude Annotation: Signal `ev_reset` is delayed relative to the signal `ev_bus_active` which also triggers.
170 end else if (ev_bus_active) begin
-8-
171 link_resume_o = 1;
==>
172 link_state_d = LinkPowered;
173 end
MISSING_ELSE
==>
174 end
175
176 // An event occurred that brought the link out of LinkSuspended, but
177 // the end-of-resume signaling may not have occurred yet.
178 // Park here before starting to count towards not seeing SOF. Wait for
179 // the end of resume signaling before expecting SOF. The host will
180 // return the link to idle after a low-speed EOP. Instead of trying to
181 // capture the termination of resume signaling direclty, wait for
182 // any J / idle symbol (or a bus reset).
183 LinkResuming: begin
184 if (rx_j_det_i | ev_reset) begin
-9-
185 link_resume_o = 1;
==>
186 link_state_d = LinkActiveNoSOF;
187 end
MISSING_ELSE
==>
188 end
189
190 // Active but not yet seen a frame
191 // One reason for getting stuck here is the host thinks it is a LS link
192 // which could happen if the flipped bit does not match the actual pins
193 // Annother is the SI is bad so good data is not recovered from the link
194 LinkActiveNoSOF: begin
195 if (ev_bus_inactive) begin
-10-
196 link_state_d = LinkSuspended;
==>
197 end else if (sof_detected_i) begin
-11-
198 link_state_d = LinkActive;
==>
199 end
MISSING_ELSE
==>
200 end
201
202 // Active (USB spec: Default / Address / Configured)
203 LinkActive: begin
204 if (ev_bus_inactive) begin
-12-
205 link_state_d = LinkSuspended;
==>
206 end else if (ev_reset) begin
-13-
207 link_state_d = LinkActiveNoSOF;
==>
208 end
MISSING_ELSE
==>
209 end
210
211 LinkSuspended: begin
212 if (ev_reset) begin
-14-
213 link_resume_o = 1;
==> (Excluded)
Exclude Annotation: Signal `ev_reset` is delayed relative to the signal `ev_bus_active` which also triggers.
214 link_state_d = LinkActiveNoSOF;
215 end else if (ev_bus_active) begin
-15-
216 link_state_d = LinkResuming;
==>
217 end
MISSING_ELSE
==>
218 end
219
220 default: begin
221 link_state_d = LinkDisconnected;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | Status | Tests | Exclude Annotation |
| 1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| 0 |
LinkDisconnected |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| 0 |
LinkDisconnected |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
| 0 |
LinkPowered |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| 0 |
LinkPowered |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T70,T96,T73 |
|
| 0 |
LinkPowered |
- |
0 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T73,T97,T98 |
|
| 0 |
LinkPowered |
- |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| 0 |
LinkPoweredSuspended |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
Signal `ev_reset` is delayed relative to the signal `ev_bus_active` which also triggers. |
| 0 |
LinkPoweredSuspended |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T73,T97,T99 |
|
| 0 |
LinkPoweredSuspended |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T73,T97,T98 |
|
| 0 |
LinkResuming |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T8,T68,T70 |
|
| 0 |
LinkResuming |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T8,T68,T70 |
|
| 0 |
LinkActiveNoSOF |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T7,T8,T9 |
|
| 0 |
LinkActiveNoSOF |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
Covered |
T41,T7,T100 |
|
| 0 |
LinkActiveNoSOF |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| 0 |
LinkActive |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T62,T101,T11 |
|
| 0 |
LinkActive |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
Covered |
T10,T102,T103 |
|
| 0 |
LinkActive |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
Covered |
T41,T7,T100 |
|
| 0 |
LinkSuspended |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Excluded |
|
Signal `ev_reset` is delayed relative to the signal `ev_bus_active` which also triggers. |
| 0 |
LinkSuspended |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
Covered |
T8,T68,T101 |
|
| 0 |
LinkSuspended |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
Covered |
T7,T8,T62 |
|
| 0 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
231 if (!rst_ni) begin
-1-
232 link_state_q <= LinkDisconnected;
==>
233 end else begin
234 link_state_q <= link_state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
250 unique case (link_rst_state_q)
-1-
251 // No reset signal detected
252 NoRst: begin
253 if (see_se0) begin
-2-
254 link_rst_state_d = RstCnt;
==>
255 link_rst_timer_d = 0;
256 end
MISSING_ELSE
==>
257 end
258
259 // Reset signal detected -> counting
260 RstCnt: begin
261 if (!see_se0) begin
-3-
262 link_rst_state_d = NoRst;
==>
263 end else begin
264 if (us_tick_i) begin
-4-
265 if (link_rst_timer_q == RESET_TIMEOUT) begin
-5-
266 link_rst_state_d = RstPend;
==>
267 end else begin
268 link_rst_timer_d = link_rst_timer_q + 1;
==>
269 end
270 end
MISSING_ELSE
==>
271 end
272 end
273
274 // Detected reset -> wait for falling edge
275 RstPend: begin
276 if (!see_se0) begin
-6-
277 link_rst_state_d = NoRst;
==>
278 ev_reset = 1'b1;
279 end
MISSING_ELSE
==>
280 link_reset = 1'b1;
281 end
282
283 default : link_rst_state_d = NoRst;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests | Exclude Annotation |
| NoRst |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| NoRst |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| RstCnt |
- |
1 |
- |
- |
- |
Covered |
T1,T2,T28 |
|
| RstCnt |
- |
0 |
1 |
1 |
- |
Covered |
T1,T2,T3 |
|
| RstCnt |
- |
0 |
1 |
0 |
- |
Covered |
T1,T2,T3 |
|
| RstCnt |
- |
0 |
0 |
- |
- |
Covered |
T1,T2,T3 |
|
| RstPend |
- |
- |
- |
- |
1 |
Covered |
T1,T2,T3 |
|
| RstPend |
- |
- |
- |
- |
0 |
Covered |
T1,T2,T3 |
|
| default |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
292 if (!rst_ni) begin
-1-
293 link_rst_state_q <= NoRst;
==>
294 link_rst_timer_q <= 0;
295 end else begin
296 link_rst_state_q <= link_rst_state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
311 unique case (link_inac_state_q)
-1-
312 // Active or disabled
313 Active: begin
314 link_inac_timer_d = 0;
315 if (!ev_bus_active && monitor_inac) begin
-2-
316 link_inac_state_d = InactCnt;
==>
317 end
MISSING_ELSE
==>
318 end
319
320 // Got an inactivity signal -> count duration
321 InactCnt: begin
322 if (ev_bus_active || !monitor_inac) begin
-3-
323 link_inac_state_d = Active;
==>
324 end else if (us_tick_i) begin
-4-
325 if (link_inac_timer_q == SUSPEND_TIMEOUT) begin
-5-
326 link_inac_state_d = InactPend;
==>
327 ev_bus_inactive = 1;
328 end else begin
329 link_inac_timer_d = link_inac_timer_q + 1;
==>
330 end
331 end
MISSING_ELSE
==>
332 end
333
334 // Counter expired & event sent, wait here
335 InactPend: begin
336 if (ev_bus_active || !monitor_inac) begin
-6-
337 link_inac_state_d = Active;
==>
338 end
MISSING_ELSE
==>
339 end
340
341 default : link_inac_state_d = Active;
==> (Excluded)
Exclude Annotation: VC_COV_UNR
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests | Exclude Annotation |
| Active |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| Active |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| InactCnt |
- |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| InactCnt |
- |
0 |
1 |
1 |
- |
Covered |
T7,T8,T62 |
|
| InactCnt |
- |
0 |
1 |
0 |
- |
Covered |
T1,T2,T3 |
|
| InactCnt |
- |
0 |
0 |
- |
- |
Covered |
T1,T2,T3 |
|
| InactPend |
- |
- |
- |
- |
1 |
Covered |
T7,T8,T62 |
|
| InactPend |
- |
- |
- |
- |
0 |
Not Covered |
|
|
| default |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
348 if (!rst_ni) begin
-1-
349 link_inac_state_q <= Active;
==>
350 link_inac_timer_q <= 0;
351 end else begin
352 link_inac_state_q <= link_inac_state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
367 if (!rst_ni) begin
-1-
368 missed_sof_count <= '0;
==>
369 end else begin
370 if (sof_detected_i || !link_active_o || link_reset) begin
-2-
371 missed_sof_count <= '0;
==>
372 end else if (sof_missed_o && !host_lost_o) begin
-3-
373 missed_sof_count <= missed_sof_count + 1;
==>
374 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T7,T8,T49 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
380 if (!rst_ni) begin
-1-
381 missing_sof_timer <= '0;
==>
382 end else begin
383 if (sof_missed_o || sof_detected_i || !link_active_o || link_reset) begin
-2-
384 missing_sof_timer <= '0;
==>
385 end else if (us_tick_i) begin
-3-
386 missing_sof_timer <= missing_sof_timer + 1;
==>
387 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.usbdev_impl.u_usbdev_linkstate
Assertion Details
LincInacStateValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
580384169 |
580090083 |
0 |
0 |
| T1 |
7293 |
7243 |
0 |
0 |
| T2 |
7698 |
7601 |
0 |
0 |
| T3 |
6346 |
6265 |
0 |
0 |
| T28 |
8471 |
8384 |
0 |
0 |
| T29 |
21708 |
21622 |
0 |
0 |
| T30 |
38925 |
38834 |
0 |
0 |
| T31 |
7561 |
7478 |
0 |
0 |
| T32 |
48746 |
48670 |
0 |
0 |
| T41 |
7600 |
7502 |
0 |
0 |
| T42 |
1581 |
1491 |
0 |
0 |
LinkRstStateValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
580384169 |
580090083 |
0 |
0 |
| T1 |
7293 |
7243 |
0 |
0 |
| T2 |
7698 |
7601 |
0 |
0 |
| T3 |
6346 |
6265 |
0 |
0 |
| T28 |
8471 |
8384 |
0 |
0 |
| T29 |
21708 |
21622 |
0 |
0 |
| T30 |
38925 |
38834 |
0 |
0 |
| T31 |
7561 |
7478 |
0 |
0 |
| T32 |
48746 |
48670 |
0 |
0 |
| T41 |
7600 |
7502 |
0 |
0 |
| T42 |
1581 |
1491 |
0 |
0 |
LinkStateValid_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
580384169 |
580090083 |
0 |
0 |
| T1 |
7293 |
7243 |
0 |
0 |
| T2 |
7698 |
7601 |
0 |
0 |
| T3 |
6346 |
6265 |
0 |
0 |
| T28 |
8471 |
8384 |
0 |
0 |
| T29 |
21708 |
21622 |
0 |
0 |
| T30 |
38925 |
38834 |
0 |
0 |
| T31 |
7561 |
7478 |
0 |
0 |
| T32 |
48746 |
48670 |
0 |
0 |
| T41 |
7600 |
7502 |
0 |
0 |
| T42 |
1581 |
1491 |
0 |
0 |