Unified Coverage Report :: Module

Line Coverage for Module : prim_subreg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00



55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T1 T2 T3 
65         1/1            assign qe = wr_en;
           Tests:       T1 T2 T3 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T1 T2 T3

Cond Coverage for Module : prim_subreg ( parameter DW=7,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_usbctrl_device_address

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_0_size_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_1_size_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_2_size_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_3_size_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_4_size_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_5_size_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_6_size_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_7_size_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_8_size_8

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_9_size_9

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_10_size_10

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_11_size_11

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_intr_state_pkt_received

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_intr_state_pkt_sent

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_intr_state_av_out_empty

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_intr_state_rx_full

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_intr_state_av_setup_empty

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_wake_events_module_active

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_wake_events_disconnected

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_wake_events_bus_reset

SCORE	COND
95.24	100.00

tb.dut.u_reg.u_wake_events_bus_not_idle

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_disconnected

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_host_lost

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_link_reset

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_link_suspend

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_link_resume

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_av_overflow

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_link_in_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_rx_crc_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_rx_pid_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_rx_bitstuff_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_frame

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_powered

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_state_link_out_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_sent_sent_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_sent_sent_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_sent_sent_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_sent_sent_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_sent_sent_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_sent_sent_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_sent_sent_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_sent_sent_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_sent_sent_8

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_sent_sent_9

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_sent_sent_10

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_sent_sent_11

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_0_sending_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_0_pend_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_1_sending_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_1_pend_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_2_sending_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_2_pend_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_3_sending_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_3_pend_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_4_sending_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_4_pend_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_5_sending_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_5_pend_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_6_sending_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_6_pend_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_7_sending_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_7_pend_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_8_sending_8

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_8_pend_8

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_9_sending_9

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_9_pend_9

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_10_sending_10

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_10_pend_10

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_11_sending_11

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_11_pend_11

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_pkt_received

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_pkt_sent

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_disconnected

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_host_lost

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_link_reset

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_link_suspend

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_link_resume

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_av_out_empty

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_full

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_av_overflow

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_link_in_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_crc_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_pid_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_rx_bitstuff_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_frame

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_powered

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_link_out_err

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_intr_enable_av_setup_empty

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_usbctrl_enable

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_usbctrl_resume_link_active

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_out_enable_enable_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_out_enable_enable_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_out_enable_enable_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_out_enable_enable_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_out_enable_enable_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_out_enable_enable_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_out_enable_enable_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_out_enable_enable_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_out_enable_enable_8

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_out_enable_enable_9

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_out_enable_enable_10

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_out_enable_enable_11

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_in_enable_enable_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_in_enable_enable_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_in_enable_enable_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_in_enable_enable_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_in_enable_enable_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_in_enable_enable_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_in_enable_enable_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_in_enable_enable_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_in_enable_enable_8

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_in_enable_enable_9

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_in_enable_enable_10

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_ep_in_enable_enable_11

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_setup_setup_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_setup_setup_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_setup_setup_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_setup_setup_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_setup_setup_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_setup_setup_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_setup_setup_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_setup_setup_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_setup_setup_8

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_setup_setup_9

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_setup_setup_10

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_setup_setup_11

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_out_out_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_out_out_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_out_out_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_out_out_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_out_out_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_out_out_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_out_out_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_out_out_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_out_out_8

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_out_out_9

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_out_out_10

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_rxenable_out_out_11

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_set_nak_out_enable_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_set_nak_out_enable_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_set_nak_out_enable_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_set_nak_out_enable_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_set_nak_out_enable_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_set_nak_out_enable_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_set_nak_out_enable_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_set_nak_out_enable_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_set_nak_out_enable_8

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_set_nak_out_enable_9

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_set_nak_out_enable_10

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_set_nak_out_enable_11

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_stall_endpoint_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_stall_endpoint_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_stall_endpoint_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_stall_endpoint_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_stall_endpoint_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_stall_endpoint_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_stall_endpoint_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_stall_endpoint_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_stall_endpoint_8

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_stall_endpoint_9

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_stall_endpoint_10

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_stall_endpoint_11

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_stall_endpoint_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_stall_endpoint_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_stall_endpoint_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_stall_endpoint_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_stall_endpoint_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_stall_endpoint_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_stall_endpoint_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_stall_endpoint_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_stall_endpoint_8

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_stall_endpoint_9

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_stall_endpoint_10

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_stall_endpoint_11

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_0_rdy_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_1_rdy_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_2_rdy_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_3_rdy_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_4_rdy_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_5_rdy_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_6_rdy_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_7_rdy_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_8_rdy_8

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_9_rdy_9

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_10_rdy_10

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_11_rdy_11

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_iso_iso_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_iso_iso_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_iso_iso_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_iso_iso_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_iso_iso_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_iso_iso_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_iso_iso_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_iso_iso_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_iso_iso_8

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_iso_iso_9

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_iso_iso_10

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_out_iso_iso_11

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_iso_iso_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_iso_iso_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_iso_iso_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_iso_iso_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_iso_iso_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_iso_iso_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_iso_iso_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_iso_iso_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_iso_iso_8

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_iso_iso_9

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_iso_iso_10

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_in_iso_iso_11

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_phy_pins_drive_dp_o

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_phy_pins_drive_dn_o

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_phy_pins_drive_d_o

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_phy_pins_drive_se0_o

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_phy_pins_drive_oe_o

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_phy_pins_drive_rx_enable_o

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_phy_pins_drive_dp_pullup_en_o

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_phy_pins_drive_dn_pullup_en_o

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_phy_pins_drive_en

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_phy_config_use_diff_rcvr

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_phy_config_tx_use_d_se0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_phy_config_eop_single_bit

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_phy_config_pinflip

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_phy_config_usb_ref_disable

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_phy_config_tx_osc_test_mode

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_avout_rst

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_avsetup_rst

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_fifo_ctrl_rx_rst

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=5,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_0_buffer_0

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_1_buffer_1

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_2_buffer_2

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_3_buffer_3

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_4_buffer_4

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_5_buffer_5

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_6_buffer_6

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_7_buffer_7

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_8_buffer_8

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_9_buffer_9

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_10_buffer_10

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_configin_11_buffer_11

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T32,T88

Branch Coverage for Module : prim_subreg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_intr_state_pkt_received	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_intr_state_pkt_sent	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_intr_state_av_out_empty	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_intr_state_rx_full	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_intr_state_av_setup_empty	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_wake_events_module_active	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_wake_events_disconnected	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_wake_events_bus_reset	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_wake_events_bus_not_idle	95.24	85.71	100.00			100.00
tb.dut.u_reg.u_intr_state_disconnected	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_state_host_lost	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_state_link_reset	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_state_link_suspend	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_state_link_resume	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_state_av_overflow	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_state_link_in_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_state_rx_crc_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_state_rx_pid_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_state_rx_bitstuff_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_state_frame	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_state_powered	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_state_link_out_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_pkt_received	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_pkt_sent	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_disconnected	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_host_lost	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_link_reset	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_link_suspend	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_link_resume	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_av_out_empty	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_rx_full	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_av_overflow	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_link_in_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_rx_crc_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_rx_pid_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_rx_bitstuff_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_frame	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_powered	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_link_out_err	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_intr_enable_av_setup_empty	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_usbctrl_enable	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_usbctrl_resume_link_active	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_usbctrl_device_address	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_out_enable_enable_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_out_enable_enable_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_out_enable_enable_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_out_enable_enable_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_out_enable_enable_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_out_enable_enable_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_out_enable_enable_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_out_enable_enable_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_out_enable_enable_8	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_out_enable_enable_9	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_out_enable_enable_10	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_out_enable_enable_11	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_in_enable_enable_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_in_enable_enable_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_in_enable_enable_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_in_enable_enable_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_in_enable_enable_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_in_enable_enable_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_in_enable_enable_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_in_enable_enable_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_in_enable_enable_8	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_in_enable_enable_9	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_in_enable_enable_10	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_ep_in_enable_enable_11	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_setup_setup_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_setup_setup_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_setup_setup_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_setup_setup_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_setup_setup_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_setup_setup_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_setup_setup_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_setup_setup_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_setup_setup_8	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_setup_setup_9	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_setup_setup_10	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_setup_setup_11	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_out_out_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_out_out_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_out_out_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_out_out_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_out_out_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_out_out_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_out_out_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_out_out_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_out_out_8	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_out_out_9	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_out_out_10	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_rxenable_out_out_11	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_set_nak_out_enable_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_set_nak_out_enable_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_set_nak_out_enable_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_set_nak_out_enable_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_set_nak_out_enable_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_set_nak_out_enable_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_set_nak_out_enable_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_set_nak_out_enable_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_set_nak_out_enable_8	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_set_nak_out_enable_9	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_set_nak_out_enable_10	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_set_nak_out_enable_11	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_sent_sent_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_sent_sent_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_sent_sent_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_sent_sent_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_sent_sent_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_sent_sent_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_sent_sent_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_sent_sent_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_sent_sent_8	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_sent_sent_9	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_sent_sent_10	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_sent_sent_11	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_stall_endpoint_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_stall_endpoint_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_stall_endpoint_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_stall_endpoint_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_stall_endpoint_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_stall_endpoint_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_stall_endpoint_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_stall_endpoint_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_stall_endpoint_8	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_stall_endpoint_9	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_stall_endpoint_10	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_stall_endpoint_11	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_stall_endpoint_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_stall_endpoint_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_stall_endpoint_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_stall_endpoint_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_stall_endpoint_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_stall_endpoint_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_stall_endpoint_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_stall_endpoint_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_stall_endpoint_8	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_stall_endpoint_9	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_stall_endpoint_10	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_stall_endpoint_11	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_0_buffer_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_0_size_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_0_sending_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_0_pend_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_0_rdy_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_1_buffer_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_1_size_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_1_sending_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_1_pend_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_1_rdy_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_2_buffer_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_2_size_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_2_sending_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_2_pend_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_2_rdy_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_3_buffer_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_3_size_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_3_sending_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_3_pend_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_3_rdy_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_4_buffer_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_4_size_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_4_sending_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_4_pend_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_4_rdy_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_5_buffer_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_5_size_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_5_sending_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_5_pend_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_5_rdy_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_6_buffer_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_6_size_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_6_sending_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_6_pend_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_6_rdy_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_7_buffer_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_7_size_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_7_sending_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_7_pend_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_7_rdy_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_8_buffer_8	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_8_size_8	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_8_sending_8	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_8_pend_8	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_8_rdy_8	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_9_buffer_9	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_9_size_9	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_9_sending_9	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_9_pend_9	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_9_rdy_9	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_10_buffer_10	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_10_size_10	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_10_sending_10	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_10_pend_10	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_10_rdy_10	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_11_buffer_11	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_11_size_11	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_11_sending_11	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_11_pend_11	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_configin_11_rdy_11	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_iso_iso_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_iso_iso_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_iso_iso_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_iso_iso_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_iso_iso_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_iso_iso_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_iso_iso_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_iso_iso_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_iso_iso_8	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_iso_iso_9	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_iso_iso_10	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_out_iso_iso_11	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_iso_iso_0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_iso_iso_1	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_iso_iso_2	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_iso_iso_3	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_iso_iso_4	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_iso_iso_5	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_iso_iso_6	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_iso_iso_7	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_iso_iso_8	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_iso_iso_9	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_iso_iso_10	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_in_iso_iso_11	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_phy_pins_drive_dp_o	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_phy_pins_drive_dn_o	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_phy_pins_drive_d_o	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_phy_pins_drive_se0_o	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_phy_pins_drive_oe_o	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_phy_pins_drive_rx_enable_o	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_phy_pins_drive_dp_pullup_en_o	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_phy_pins_drive_dn_pullup_en_o	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_phy_pins_drive_en	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_phy_config_use_diff_rcvr	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_phy_config_tx_use_d_se0	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_phy_config_eop_single_bit	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_phy_config_pinflip	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_phy_config_usb_ref_disable	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_phy_config_tx_osc_test_mode	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fifo_ctrl_avout_rst	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fifo_ctrl_avsetup_rst	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_fifo_ctrl_rx_rst	100.00	100.00	100.00			100.00