Unified Coverage Report :: Module Instance :: tb.dut.usbdev

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T1 T87 T88 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T1 T87 T88 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T1 T87 T88

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T63,T64,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T87,T88

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T64,T65,T91
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T87,T88

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		DUT shall not read from empty FIFO
1	0	1	Covered	T1,T87,T88
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T18,T24

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T87,T88
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	580384169	131018502	0	0
DataKnown_AKnownEnable	580384169	580090083	0	0
DepthKnown_A	580384169	580090083	0	0
RvalidKnown_A	580384169	580090083	0	0
WreadyKnown_A	580384169	580090083	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	580384169	131018502	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	580384169	131018502
T1	7293	1233
T2	7698	0
T3	6346	0
T18	0	584
T24	0	573
T28	8471	0
T29	21708	0
T30	38925	0
T31	7561	0
T32	48746	0
T41	7600	0
T42	1581	0
T50	0	572
T51	0	560
T63	0	3603
T77	0	2377
T87	0	40777
T88	0	29511
T90	0	562

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

DepthKnown_A

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

RvalidKnown_A

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

WreadyKnown_A

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	580384169	131018502
T1	7293	1233
T2	7698	0
T3	6346	0
T18	0	584
T24	0	573
T28	8471	0
T29	21708	0
T30	38925	0
T31	7561	0
T32	48746	0
T41	7600	0
T42	1581	0
T50	0	572
T51	0	560
T63	0	3603
T77	0	2377
T87	0	40777
T88	0	29511
T90	0	562

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T2 T3 T28 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T2 T3 T28 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T2 T3 T28

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T31,T63
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T28

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T92
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T2,T3,T28

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		DUT shall not read from empty FIFO
1	0	1	Covered	T2,T3,T28
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T28,T29,T30

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T28
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	580384169	275372083	0	0
DataKnown_AKnownEnable	580384169	580090083	0	0
DepthKnown_A	580384169	580090083	0	0
RvalidKnown_A	580384169	580090083	0	0
WreadyKnown_A	580384169	580090083	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	580384169	275372083	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	580384169	275372083
T2	7698	1271
T3	6346	910
T28	8471	544
T29	21708	10686
T30	38925	14650
T31	7561	1856
T32	48746	19428
T41	7600	830
T42	1581	0
T87	46813	34498
T88	0	28880

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

DepthKnown_A

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

RvalidKnown_A

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

WreadyKnown_A

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	580384169	275372083
T2	7698	1271
T3	6346	910
T28	8471	544
T29	21708	10686
T30	38925	14650
T31	7561	1856
T32	48746	19428
T41	7600	830
T42	1581	0
T87	46813	34498
T88	0	28880

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T1 T28 T29 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T1 T28 T29 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T53,T54,T55
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T28,T29

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T28,T29

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T1,T28,T29
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T28,T29,T30

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T28,T29
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T28,T29



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T28,T29
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	580384169	42573197	0	0
DataKnown_AKnownEnable	580384169	580090083	0	0
DepthKnown_A	580384169	580090083	0	0
RvalidKnown_A	580384169	580090083	0	0
WreadyKnown_A	580384169	580090083	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	580384169	42573197	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	580384169	42573197
T1	7293	755
T2	7698	0
T3	6346	0
T28	8471	106
T29	21708	623
T30	38925	637
T31	7561	859
T32	48746	1068
T34	0	10172
T35	0	2289
T36	0	89
T37	0	1255
T41	7600	0
T42	1581	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

DepthKnown_A

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

RvalidKnown_A

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

WreadyKnown_A

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	580384169	42573197
T1	7293	755
T2	7698	0
T3	6346	0
T28	8471	106
T29	21708	623
T30	38925	637
T31	7561	859
T32	48746	1068
T34	0	10172
T35	0	2289
T36	0	89
T37	0	1255
T41	7600	0
T42	1581	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	582225092	21081066	0	0
DataKnown_AKnownEnable	582225092	581894165	0	0
DepthKnown_A	582225092	581894165	0	0
RvalidKnown_A	582225092	581894165	0	0
WreadyKnown_A	582225092	581894165	0	0
gen_passthru_fifo.paramCheckPass	3837	3837	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	582225092	21081066
T1	7293	20
T2	7698	12
T3	6346	22
T28	8471	14
T29	21708	139
T30	38925	247
T31	7561	19
T32	48746	253
T41	7600	11
T42	1581	7

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

DepthKnown_A

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

RvalidKnown_A

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

WreadyKnown_A

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	3837	3837
T1	1	1
T2	1	1
T3	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T41	1	1
T42	1	1

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	582225092	29020347	0	0
DataKnown_AKnownEnable	582225092	581894165	0	0
DepthKnown_A	582225092	581894165	0	0
RvalidKnown_A	582225092	581894165	0	0
WreadyKnown_A	582225092	581894165	0	0
gen_passthru_fifo.paramCheckPass	3837	3837	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	582225092	29020347
T1	7293	20
T2	7698	12
T3	6346	22
T28	8471	43
T29	21708	139
T30	38925	247
T31	7561	19
T32	48746	253
T41	7600	11
T42	1581	7

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

DepthKnown_A

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

RvalidKnown_A

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

WreadyKnown_A

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	3837	3837
T1	1	1
T2	1	1
T3	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T41	1	1
T42	1	1

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	582225092	937596	0	0
DataKnown_AKnownEnable	582225092	581894165	0	0
DepthKnown_A	582225092	581894165	0	0
RvalidKnown_A	582225092	581894165	0	0
WreadyKnown_A	582225092	581894165	0	0
gen_passthru_fifo.paramCheckPass	3837	3837	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	582225092	937596
T21	0	12
T23	0	12
T28	8471	2
T29	21708	69
T30	38925	57
T31	7561	0
T32	48746	126
T36	0	11
T41	7600	0
T42	1581	0
T63	9992	0
T87	46813	14
T88	35206	8
T89	0	16

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

DepthKnown_A

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

RvalidKnown_A

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

WreadyKnown_A

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	3837	3837
T1	1	1
T2	1	1
T3	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T41	1	1
T42	1	1

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	582225092	1649708	0	0
DataKnown_AKnownEnable	582225092	581894165	0	0
DepthKnown_A	582225092	581894165	0	0
RvalidKnown_A	582225092	581894165	0	0
WreadyKnown_A	582225092	581894165	0	0
gen_passthru_fifo.paramCheckPass	3837	3837	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	582225092	1649708
T21	0	12
T23	0	12
T28	8471	3
T29	21708	69
T30	38925	57
T31	7561	0
T32	48746	126
T36	0	11
T41	7600	0
T42	1581	0
T63	9992	0
T87	46813	14
T88	35206	28
T89	0	16

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

DepthKnown_A

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

RvalidKnown_A

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

WreadyKnown_A

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	3837	3837
T1	1	1
T2	1	1
T3	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T41	1	1
T42	1	1

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	582225092	20087011	0	0
DataKnown_AKnownEnable	582225092	581894165	0	0
DepthKnown_A	582225092	581894165	0	0
RvalidKnown_A	582225092	581894165	0	0
WreadyKnown_A	582225092	581894165	0	0
gen_passthru_fifo.paramCheckPass	3837	3837	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	582225092	20087011
T1	7293	20
T2	7698	12
T3	6346	22
T28	8471	12
T29	21708	70
T30	38925	190
T31	7561	19
T32	48746	127
T41	7600	11
T42	1581	7

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

DepthKnown_A

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

RvalidKnown_A

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

WreadyKnown_A

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	3837	3837
T1	1	1
T2	1	1
T3	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T41	1	1
T42	1	1

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	582225092	27370639	0	0
DataKnown_AKnownEnable	582225092	581894165	0	0
DepthKnown_A	582225092	581894165	0	0
RvalidKnown_A	582225092	581894165	0	0
WreadyKnown_A	582225092	581894165	0	0
gen_passthru_fifo.paramCheckPass	3837	3837	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	582225092	27370639
T1	7293	20
T2	7698	12
T3	6346	22
T28	8471	40
T29	21708	70
T30	38925	190
T31	7561	19
T32	48746	127
T41	7600	11
T42	1581	7

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

DepthKnown_A

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

RvalidKnown_A

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

WreadyKnown_A

Name	Attempts	Real Successes
Total	582225092	581894165
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	3837	3837
T1	1	1
T2	1	1
T3	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T41	1	1
T42	1	1

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T28 T29 T30 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T28 T29 T30 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T28 T29 T30 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T28,T29,T30

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T28,T29,T30

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T28,T88,T36
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T28,T29,T30

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T28,T29,T30
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T28,T29,T30



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T28,T29,T30
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	580384169	1601424	0	0
DataKnown_AKnownEnable	580384169	580090083	0	0
DepthKnown_A	580384169	580090083	0	0
RvalidKnown_A	580384169	580090083	0	0
WreadyKnown_A	580384169	580090083	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	580384169	1601424	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	580384169	1601424
T21	0	12
T23	0	12
T28	8471	3
T29	21708	69
T30	38925	57
T31	7561	0
T32	48746	126
T36	0	11
T41	7600	0
T42	1581	0
T63	9992	0
T87	46813	14
T88	35206	28
T89	0	16

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

DepthKnown_A

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

RvalidKnown_A

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

WreadyKnown_A

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	580384169	1601424
T21	0	12
T23	0	12
T28	8471	3
T29	21708	69
T30	38925	57
T31	7561	0
T32	48746	126
T36	0	11
T41	7600	0
T42	1581	0
T63	9992	0
T87	46813	14
T88	35206	28
T89	0	16

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T28 T29 T30 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T28 T29 T30 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T28 T29 T30 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T28,T29,T30

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T28,T29,T30

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T28,T29,T30

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T28,T29,T30
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T28,T29,T30



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T28,T29,T30
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	580384169	597821	0	0
DataKnown_AKnownEnable	580384169	580090083	0	0
DepthKnown_A	580384169	580090083	0	0
RvalidKnown_A	580384169	580090083	0	0
WreadyKnown_A	580384169	580090083	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	580384169	597821	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	580384169	597821
T21	0	12
T23	0	12
T24	0	18
T28	8471	2
T29	21708	69
T30	38925	57
T31	7561	0
T32	48746	126
T36	0	11
T41	7600	0
T42	1581	0
T50	0	18
T63	9992	0
T87	46813	0
T88	35206	0
T89	0	16

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

DepthKnown_A

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

RvalidKnown_A

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

WreadyKnown_A

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	580384169	597821
T21	0	12
T23	0	12
T24	0	18
T28	8471	2
T29	21708	69
T30	38925	57
T31	7561	0
T32	48746	126
T36	0	11
T41	7600	0
T42	1581	0
T50	0	18
T63	9992	0
T87	46813	0
T88	35206	0
T89	0	16

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00



68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T28 T29 T30 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T28 T29 T30 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130        1/1                assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
           Tests:       T1 T2 T3 
131        1/1                assign empty = fifo_empty & ~wvalid_i;
           Tests:       T1 T2 T3 
132                         end else begin : gen_nopass
133                           assign rdata_int = storage_rdata;
134                           assign empty = fifo_empty;
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	18	18	100.00
Logical	18	18	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T28,T24,T86
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T28,T29,T30

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T28,T29,T30

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T28,T36,T21
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T28,T29,T30

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T29,T30

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T28,T29,T30

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T28,T24,T86
1	0	Covered	T28,T29,T30
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T28,T29,T30
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00



130              assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T28,T29,T30
0	Covered	T1,T2,T3



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T28,T29,T30



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T28,T29,T30
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	580384169	998040	0	0
DataKnown_AKnownEnable	580384169	580090083	0	0
DepthKnown_A	580384169	580090083	0	0
RvalidKnown_A	580384169	580090083	0	0
WreadyKnown_A	580384169	580090083	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	580384169	998040	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	580384169	998040
T21	0	12
T23	0	12
T24	0	84
T28	8471	3
T29	21708	69
T30	38925	57
T31	7561	0
T32	48746	126
T36	0	11
T41	7600	0
T42	1581	0
T50	0	18
T63	9992	0
T87	46813	0
T88	35206	0
T89	0	16

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

DepthKnown_A

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

RvalidKnown_A

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

WreadyKnown_A

Name	Attempts	Real Successes
Total	580384169	580090083
T1	7293	7243
T2	7698	7601
T3	6346	6265
T28	8471	8384
T29	21708	21622
T30	38925	38834
T31	7561	7478
T32	48746	48670
T41	7600	7502
T42	1581	1491

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes
Total	580384169	998040
T21	0	12
T23	0	12
T24	0	84
T28	8471	3
T29	21708	69
T30	38925	57
T31	7561	0
T32	48746	126
T36	0	11
T41	7600	0
T42	1581	0
T50	0	18
T63	9992	0
T87	46813	0
T88	35206	0
T89	0	16

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00