Unified Coverage Report :: Module :: usbdev_reg_top

Module : usbdev_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.47	99.76	98.11			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.47	99.76	98.11			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.47	99.76	98.11			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.26	98.85	98.83	100.00		99.48	94.12

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_avoutbuffer	100.00	100.00
u_avsetupbuffer	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_configin_0_buffer_0	100.00	100.00	100.00			100.00
u_configin_0_pend_0	100.00	100.00	100.00			100.00
u_configin_0_rdy_0	100.00	100.00	100.00			100.00
u_configin_0_sending_0	100.00	100.00	100.00			100.00
u_configin_0_size_0	100.00	100.00	100.00			100.00
u_configin_10_buffer_10	100.00	100.00	100.00			100.00
u_configin_10_pend_10	100.00	100.00	100.00			100.00
u_configin_10_rdy_10	100.00	100.00	100.00			100.00
u_configin_10_sending_10	100.00	100.00	100.00			100.00
u_configin_10_size_10	100.00	100.00	100.00			100.00
u_configin_11_buffer_11	100.00	100.00	100.00			100.00
u_configin_11_pend_11	100.00	100.00	100.00			100.00
u_configin_11_rdy_11	100.00	100.00	100.00			100.00
u_configin_11_sending_11	100.00	100.00	100.00			100.00
u_configin_11_size_11	100.00	100.00	100.00			100.00
u_configin_1_buffer_1	100.00	100.00	100.00			100.00
u_configin_1_pend_1	100.00	100.00	100.00			100.00
u_configin_1_rdy_1	100.00	100.00	100.00			100.00
u_configin_1_sending_1	100.00	100.00	100.00			100.00
u_configin_1_size_1	100.00	100.00	100.00			100.00
u_configin_2_buffer_2	100.00	100.00	100.00			100.00
u_configin_2_pend_2	100.00	100.00	100.00			100.00
u_configin_2_rdy_2	100.00	100.00	100.00			100.00
u_configin_2_sending_2	100.00	100.00	100.00			100.00
u_configin_2_size_2	100.00	100.00	100.00			100.00
u_configin_3_buffer_3	100.00	100.00	100.00			100.00
u_configin_3_pend_3	100.00	100.00	100.00			100.00
u_configin_3_rdy_3	100.00	100.00	100.00			100.00
u_configin_3_sending_3	100.00	100.00	100.00			100.00
u_configin_3_size_3	100.00	100.00	100.00			100.00
u_configin_4_buffer_4	100.00	100.00	100.00			100.00
u_configin_4_pend_4	100.00	100.00	100.00			100.00
u_configin_4_rdy_4	100.00	100.00	100.00			100.00
u_configin_4_sending_4	100.00	100.00	100.00			100.00
u_configin_4_size_4	100.00	100.00	100.00			100.00
u_configin_5_buffer_5	100.00	100.00	100.00			100.00
u_configin_5_pend_5	100.00	100.00	100.00			100.00
u_configin_5_rdy_5	100.00	100.00	100.00			100.00
u_configin_5_sending_5	100.00	100.00	100.00			100.00
u_configin_5_size_5	100.00	100.00	100.00			100.00
u_configin_6_buffer_6	100.00	100.00	100.00			100.00
u_configin_6_pend_6	100.00	100.00	100.00			100.00
u_configin_6_rdy_6	100.00	100.00	100.00			100.00
u_configin_6_sending_6	100.00	100.00	100.00			100.00
u_configin_6_size_6	100.00	100.00	100.00			100.00
u_configin_7_buffer_7	100.00	100.00	100.00			100.00
u_configin_7_pend_7	100.00	100.00	100.00			100.00
u_configin_7_rdy_7	100.00	100.00	100.00			100.00
u_configin_7_sending_7	100.00	100.00	100.00			100.00
u_configin_7_size_7	100.00	100.00	100.00			100.00
u_configin_8_buffer_8	100.00	100.00	100.00			100.00
u_configin_8_pend_8	100.00	100.00	100.00			100.00
u_configin_8_rdy_8	100.00	100.00	100.00			100.00
u_configin_8_sending_8	100.00	100.00	100.00			100.00
u_configin_8_size_8	100.00	100.00	100.00			100.00
u_configin_9_buffer_9	100.00	100.00	100.00			100.00
u_configin_9_pend_9	100.00	100.00	100.00			100.00
u_configin_9_rdy_9	100.00	100.00	100.00			100.00
u_configin_9_sending_9	100.00	100.00	100.00			100.00
u_configin_9_size_9	100.00	100.00	100.00			100.00
u_count_errors_bitstuff	100.00	100.00
u_count_errors_count	100.00	100.00
u_count_errors_crc16	100.00	100.00
u_count_errors_crc5	100.00	100.00
u_count_errors_pid_invalid	100.00	100.00
u_count_errors_rst	100.00	100.00
u_count_in_count	100.00	100.00
u_count_in_endpoints	100.00	100.00
u_count_in_nak	100.00	100.00
u_count_in_nodata	100.00	100.00
u_count_in_rst	100.00	100.00
u_count_in_timeout	100.00	100.00
u_count_nodata_in_count	100.00	100.00
u_count_nodata_in_endpoints	100.00	100.00
u_count_nodata_in_rst	100.00	100.00
u_count_out_count	100.00	100.00
u_count_out_datatog_out	100.00	100.00
u_count_out_drop_avout	100.00	100.00
u_count_out_drop_rx	100.00	100.00
u_count_out_endpoints	100.00	100.00
u_count_out_ign_avsetup	100.00	100.00
u_count_out_rst	100.00	100.00
u_ep_in_enable_enable_0	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_1	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_10	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_11	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_2	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_3	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_4	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_5	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_6	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_7	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_8	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_9	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_0	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_1	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_10	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_11	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_2	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_3	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_4	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_5	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_6	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_7	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_8	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_9	100.00	100.00	100.00			100.00
u_fifo_ctrl0_qe	100.00	100.00				100.00
u_fifo_ctrl_avout_rst	100.00	100.00	100.00			100.00
u_fifo_ctrl_avsetup_rst	100.00	100.00	100.00			100.00
u_fifo_ctrl_rx_rst	100.00	100.00	100.00			100.00
u_in_data_toggle_mask	60.00	60.00
u_in_data_toggle_status	100.00	100.00
u_in_iso_iso_0	100.00	100.00	100.00			100.00
u_in_iso_iso_1	100.00	100.00	100.00			100.00
u_in_iso_iso_10	100.00	100.00	100.00			100.00
u_in_iso_iso_11	100.00	100.00	100.00			100.00
u_in_iso_iso_2	100.00	100.00	100.00			100.00
u_in_iso_iso_3	100.00	100.00	100.00			100.00
u_in_iso_iso_4	100.00	100.00	100.00			100.00
u_in_iso_iso_5	100.00	100.00	100.00			100.00
u_in_iso_iso_6	100.00	100.00	100.00			100.00
u_in_iso_iso_7	100.00	100.00	100.00			100.00
u_in_iso_iso_8	100.00	100.00	100.00			100.00
u_in_iso_iso_9	100.00	100.00	100.00			100.00
u_in_sent_sent_0	100.00	100.00	100.00			100.00
u_in_sent_sent_1	100.00	100.00	100.00			100.00
u_in_sent_sent_10	100.00	100.00	100.00			100.00
u_in_sent_sent_11	100.00	100.00	100.00			100.00
u_in_sent_sent_2	100.00	100.00	100.00			100.00
u_in_sent_sent_3	100.00	100.00	100.00			100.00
u_in_sent_sent_4	100.00	100.00	100.00			100.00
u_in_sent_sent_5	100.00	100.00	100.00			100.00
u_in_sent_sent_6	100.00	100.00	100.00			100.00
u_in_sent_sent_7	100.00	100.00	100.00			100.00
u_in_sent_sent_8	100.00	100.00	100.00			100.00
u_in_sent_sent_9	100.00	100.00	100.00			100.00
u_in_stall_endpoint_0	100.00	100.00	100.00			100.00
u_in_stall_endpoint_1	100.00	100.00	100.00			100.00
u_in_stall_endpoint_10	100.00	100.00	100.00			100.00
u_in_stall_endpoint_11	100.00	100.00	100.00			100.00
u_in_stall_endpoint_2	100.00	100.00	100.00			100.00
u_in_stall_endpoint_3	100.00	100.00	100.00			100.00
u_in_stall_endpoint_4	100.00	100.00	100.00			100.00
u_in_stall_endpoint_5	100.00	100.00	100.00			100.00
u_in_stall_endpoint_6	100.00	100.00	100.00			100.00
u_in_stall_endpoint_7	100.00	100.00	100.00			100.00
u_in_stall_endpoint_8	100.00	100.00	100.00			100.00
u_in_stall_endpoint_9	100.00	100.00	100.00			100.00
u_intr_enable_av_out_empty	100.00	100.00	100.00			100.00
u_intr_enable_av_overflow	100.00	100.00	100.00			100.00
u_intr_enable_av_setup_empty	100.00	100.00	100.00			100.00
u_intr_enable_disconnected	100.00	100.00	100.00			100.00
u_intr_enable_frame	100.00	100.00	100.00			100.00
u_intr_enable_host_lost	100.00	100.00	100.00			100.00
u_intr_enable_link_in_err	100.00	100.00	100.00			100.00
u_intr_enable_link_out_err	100.00	100.00	100.00			100.00
u_intr_enable_link_reset	100.00	100.00	100.00			100.00
u_intr_enable_link_resume	100.00	100.00	100.00			100.00
u_intr_enable_link_suspend	100.00	100.00	100.00			100.00
u_intr_enable_pkt_received	100.00	100.00	100.00			100.00
u_intr_enable_pkt_sent	100.00	100.00	100.00			100.00
u_intr_enable_powered	100.00	100.00	100.00			100.00
u_intr_enable_rx_bitstuff_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_crc_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_full	100.00	100.00	100.00			100.00
u_intr_enable_rx_pid_err	100.00	100.00	100.00			100.00
u_intr_state_av_out_empty	92.59	77.78	100.00			100.00
u_intr_state_av_overflow	100.00	100.00	100.00			100.00
u_intr_state_av_setup_empty	92.59	77.78	100.00			100.00
u_intr_state_disconnected	100.00	100.00	100.00			100.00
u_intr_state_frame	100.00	100.00	100.00			100.00
u_intr_state_host_lost	100.00	100.00	100.00			100.00
u_intr_state_link_in_err	100.00	100.00	100.00			100.00
u_intr_state_link_out_err	100.00	100.00	100.00			100.00
u_intr_state_link_reset	100.00	100.00	100.00			100.00
u_intr_state_link_resume	100.00	100.00	100.00			100.00
u_intr_state_link_suspend	100.00	100.00	100.00			100.00
u_intr_state_pkt_received	92.59	77.78	100.00			100.00
u_intr_state_pkt_sent	92.59	77.78	100.00			100.00
u_intr_state_powered	100.00	100.00	100.00			100.00
u_intr_state_rx_bitstuff_err	100.00	100.00	100.00			100.00
u_intr_state_rx_crc_err	100.00	100.00	100.00			100.00
u_intr_state_rx_full	92.59	77.78	100.00			100.00
u_intr_state_rx_pid_err	100.00	100.00	100.00			100.00
u_intr_test_av_out_empty	100.00	100.00
u_intr_test_av_overflow	100.00	100.00
u_intr_test_av_setup_empty	100.00	100.00
u_intr_test_disconnected	100.00	100.00
u_intr_test_frame	100.00	100.00
u_intr_test_host_lost	100.00	100.00
u_intr_test_link_in_err	100.00	100.00
u_intr_test_link_out_err	100.00	100.00
u_intr_test_link_reset	100.00	100.00
u_intr_test_link_resume	100.00	100.00
u_intr_test_link_suspend	100.00	100.00
u_intr_test_pkt_received	100.00	100.00
u_intr_test_pkt_sent	100.00	100.00
u_intr_test_powered	100.00	100.00
u_intr_test_rx_bitstuff_err	100.00	100.00
u_intr_test_rx_crc_err	100.00	100.00
u_intr_test_rx_full	100.00	100.00
u_intr_test_rx_pid_err	100.00	100.00
u_out_data_toggle_mask	60.00	60.00
u_out_data_toggle_status	100.00	100.00
u_out_iso_iso_0	100.00	100.00	100.00			100.00
u_out_iso_iso_1	100.00	100.00	100.00			100.00
u_out_iso_iso_10	100.00	100.00	100.00			100.00
u_out_iso_iso_11	100.00	100.00	100.00			100.00
u_out_iso_iso_2	100.00	100.00	100.00			100.00
u_out_iso_iso_3	100.00	100.00	100.00			100.00
u_out_iso_iso_4	100.00	100.00	100.00			100.00
u_out_iso_iso_5	100.00	100.00	100.00			100.00
u_out_iso_iso_6	100.00	100.00	100.00			100.00
u_out_iso_iso_7	100.00	100.00	100.00			100.00
u_out_iso_iso_8	100.00	100.00	100.00			100.00
u_out_iso_iso_9	100.00	100.00	100.00			100.00
u_out_stall_endpoint_0	100.00	100.00	100.00			100.00
u_out_stall_endpoint_1	100.00	100.00	100.00			100.00
u_out_stall_endpoint_10	100.00	100.00	100.00			100.00
u_out_stall_endpoint_11	100.00	100.00	100.00			100.00
u_out_stall_endpoint_2	100.00	100.00	100.00			100.00
u_out_stall_endpoint_3	100.00	100.00	100.00			100.00
u_out_stall_endpoint_4	100.00	100.00	100.00			100.00
u_out_stall_endpoint_5	100.00	100.00	100.00			100.00
u_out_stall_endpoint_6	100.00	100.00	100.00			100.00
u_out_stall_endpoint_7	100.00	100.00	100.00			100.00
u_out_stall_endpoint_8	100.00	100.00	100.00			100.00
u_out_stall_endpoint_9	100.00	100.00	100.00			100.00
u_phy_config_eop_single_bit	100.00	100.00	100.00			100.00
u_phy_config_pinflip	100.00	100.00	100.00			100.00
u_phy_config_tx_osc_test_mode	100.00	100.00	100.00			100.00
u_phy_config_tx_use_d_se0	100.00	100.00	100.00			100.00
u_phy_config_usb_ref_disable	100.00	100.00	100.00			100.00
u_phy_config_use_diff_rcvr	100.00	100.00	100.00			100.00
u_phy_pins_drive_d_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dn_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dn_pullup_en_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dp_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dp_pullup_en_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_en	100.00	100.00	100.00			100.00
u_phy_pins_drive_oe_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_rx_enable_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_se0_o	100.00	100.00	100.00			100.00
u_phy_pins_sense_pwr_sense	100.00	100.00
u_phy_pins_sense_rx_d_i	100.00	100.00
u_phy_pins_sense_rx_dn_i	100.00	100.00
u_phy_pins_sense_rx_dp_i	100.00	100.00
u_phy_pins_sense_tx_d_o	100.00	100.00
u_phy_pins_sense_tx_dn_o	100.00	100.00
u_phy_pins_sense_tx_dp_o	100.00	100.00
u_phy_pins_sense_tx_oe_o	100.00	100.00
u_phy_pins_sense_tx_se0_o	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.98	97.14	98.80			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_rxenable_out_out_0	96.30	100.00	88.89			100.00
u_rxenable_out_out_1	100.00	100.00	100.00			100.00
u_rxenable_out_out_10	100.00	100.00	100.00			100.00
u_rxenable_out_out_11	100.00	100.00	100.00			100.00
u_rxenable_out_out_2	100.00	100.00	100.00			100.00
u_rxenable_out_out_3	100.00	100.00	100.00			100.00
u_rxenable_out_out_4	100.00	100.00	100.00			100.00
u_rxenable_out_out_5	100.00	100.00	100.00			100.00
u_rxenable_out_out_6	100.00	100.00	100.00			100.00
u_rxenable_out_out_7	100.00	100.00	100.00			100.00
u_rxenable_out_out_8	100.00	100.00	100.00			100.00
u_rxenable_out_out_9	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_0	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_1	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_10	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_11	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_2	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_3	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_4	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_5	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_6	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_7	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_8	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_9	100.00	100.00	100.00			100.00
u_rxfifo_buffer	100.00	100.00
u_rxfifo_ep	100.00	100.00
u_rxfifo_setup	100.00	100.00
u_rxfifo_size	100.00	100.00
u_set_nak_out_enable_0	100.00	100.00	100.00			100.00
u_set_nak_out_enable_1	100.00	100.00	100.00			100.00
u_set_nak_out_enable_10	100.00	100.00	100.00			100.00
u_set_nak_out_enable_11	100.00	100.00	100.00			100.00
u_set_nak_out_enable_2	100.00	100.00	100.00			100.00
u_set_nak_out_enable_3	100.00	100.00	100.00			100.00
u_set_nak_out_enable_4	100.00	100.00	100.00			100.00
u_set_nak_out_enable_5	100.00	100.00	100.00			100.00
u_set_nak_out_enable_6	100.00	100.00	100.00			100.00
u_set_nak_out_enable_7	100.00	100.00	100.00			100.00
u_set_nak_out_enable_8	100.00	100.00	100.00			100.00
u_set_nak_out_enable_9	100.00	100.00	100.00			100.00
u_socket	99.69	98.75	100.00			100.00	100.00
u_usbctrl0_qe	100.00	100.00				100.00
u_usbctrl_device_address	100.00	100.00	100.00			100.00
u_usbctrl_enable	100.00	100.00	100.00			100.00
u_usbctrl_resume_link_active	100.00	100.00	100.00			100.00
u_usbstat_av_out_depth	100.00	100.00
u_usbstat_av_out_full	100.00	100.00
u_usbstat_av_setup_depth	100.00	100.00
u_usbstat_av_setup_full	100.00	100.00
u_usbstat_frame	100.00	100.00
u_usbstat_host_lost	100.00	100.00
u_usbstat_link_state	100.00	100.00
u_usbstat_rx_depth	100.00	100.00
u_usbstat_rx_empty	100.00	100.00
u_usbstat_sense	100.00	100.00
u_wake_control_cdc	98.13	96.08	96.43			100.00	100.00
u_wake_control_suspend_req	100.00	100.00
u_wake_control_wake_ack	100.00	100.00
u_wake_events_bus_not_idle	92.59	77.78	100.00			100.00
u_wake_events_bus_reset	92.59	77.78	100.00			100.00
u_wake_events_cdc	74.50	90.62	63.16			84.21	60.00
u_wake_events_disconnected	92.59	77.78	100.00			100.00
u_wake_events_module_active	92.59	77.78	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usbdev_reg_top

	Line No.	Total	Covered	Percent
TOTAL		818	816	99.76
ALWAYS	75	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
ALWAYS	132	3	3	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
ALWAYS	789	1	0	0.00
CONT_ASSIGN	816	1	1	100.00
ALWAYS	832	10	10	100.00
CONT_ASSIGN	1849	1	1	100.00
CONT_ASSIGN	1864	1	1	100.00
CONT_ASSIGN	1880	1	1	100.00
CONT_ASSIGN	1896	1	1	100.00
CONT_ASSIGN	1912	1	1	100.00
CONT_ASSIGN	1928	1	1	100.00
CONT_ASSIGN	1944	1	1	100.00
CONT_ASSIGN	1960	1	1	100.00
CONT_ASSIGN	1976	1	1	100.00
CONT_ASSIGN	1992	1	1	100.00
CONT_ASSIGN	2008	1	1	100.00
CONT_ASSIGN	2024	1	1	100.00
CONT_ASSIGN	2040	1	1	100.00
CONT_ASSIGN	2056	1	1	100.00
CONT_ASSIGN	2072	1	1	100.00
CONT_ASSIGN	2088	1	1	100.00
CONT_ASSIGN	2104	1	1	100.00
CONT_ASSIGN	2120	1	1	100.00
CONT_ASSIGN	2136	1	1	100.00
CONT_ASSIGN	2142	1	1	100.00
CONT_ASSIGN	2156	1	1	100.00
CONT_ASSIGN	2224	1	1	100.00
CONT_ASSIGN	3063	1	1	100.00
CONT_ASSIGN	3077	1	1	100.00
CONT_ASSIGN	3083	1	1	100.00
CONT_ASSIGN	3097	1	1	100.00
CONT_ASSIGN	7437	1	1	100.00
CONT_ASSIGN	7452	1	1	100.00
CONT_ASSIGN	7468	1	1	100.00
CONT_ASSIGN	7474	1	1	100.00
CONT_ASSIGN	7489	1	1	100.00
CONT_ASSIGN	7505	1	1	100.00
CONT_ASSIGN	8057	1	1	100.00
CONT_ASSIGN	8072	1	1	100.00
CONT_ASSIGN	8088	1	1	100.00
CONT_ASSIGN	8093	1	0	0.00
CONT_ASSIGN	8241	1	1	100.00
CONT_ASSIGN	8269	1	1	100.00
CONT_ASSIGN	8297	1	1	100.00
CONT_ASSIGN	8305	0	0
CONT_ASSIGN	8306	1	1	100.00
CONT_ASSIGN	8336	1	1	100.00
CONT_ASSIGN	8352	1	1	100.00
CONT_ASSIGN	8368	1	1	100.00
CONT_ASSIGN	8384	1	1	100.00
CONT_ASSIGN	8400	1	1	100.00
CONT_ASSIGN	8416	1	1	100.00
CONT_ASSIGN	8424	0	0
CONT_ASSIGN	8425	1	1	100.00
CONT_ASSIGN	8455	1	1	100.00
CONT_ASSIGN	8471	1	1	100.00
CONT_ASSIGN	8487	1	1	100.00
CONT_ASSIGN	8503	1	1	100.00
CONT_ASSIGN	8519	1	1	100.00
CONT_ASSIGN	8527	0	0
CONT_ASSIGN	8528	1	1	100.00
CONT_ASSIGN	8558	1	1	100.00
CONT_ASSIGN	8574	1	1	100.00
CONT_ASSIGN	8582	0	0
CONT_ASSIGN	8583	1	1	100.00
CONT_ASSIGN	8613	1	1	100.00
CONT_ASSIGN	8629	1	1	100.00
CONT_ASSIGN	8645	1	1	100.00
CONT_ASSIGN	8661	1	1	100.00
CONT_ASSIGN	8677	1	1	100.00
ALWAYS	8683	44	44	100.00
CONT_ASSIGN	8729	1	1	100.00
ALWAYS	8733	1	1	100.00
CONT_ASSIGN	8780	1	1	100.00
CONT_ASSIGN	8782	1	1	100.00
CONT_ASSIGN	8784	1	1	100.00
CONT_ASSIGN	8786	1	1	100.00
CONT_ASSIGN	8788	1	1	100.00
CONT_ASSIGN	8790	1	1	100.00
CONT_ASSIGN	8792	1	1	100.00
CONT_ASSIGN	8794	1	1	100.00
CONT_ASSIGN	8796	1	1	100.00
CONT_ASSIGN	8798	1	1	100.00
CONT_ASSIGN	8800	1	1	100.00
CONT_ASSIGN	8802	1	1	100.00
CONT_ASSIGN	8804	1	1	100.00
CONT_ASSIGN	8806	1	1	100.00
CONT_ASSIGN	8807	1	1	100.00
CONT_ASSIGN	8809	1	1	100.00
CONT_ASSIGN	8811	1	1	100.00
CONT_ASSIGN	8813	1	1	100.00
CONT_ASSIGN	8815	1	1	100.00
CONT_ASSIGN	8817	1	1	100.00
CONT_ASSIGN	8819	1	1	100.00
CONT_ASSIGN	8821	1	1	100.00
CONT_ASSIGN	8823	1	1	100.00
CONT_ASSIGN	8825	1	1	100.00
CONT_ASSIGN	8827	1	1	100.00
CONT_ASSIGN	8829	1	1	100.00
CONT_ASSIGN	8831	1	1	100.00
CONT_ASSIGN	8833	1	1	100.00
CONT_ASSIGN	8835	1	1	100.00
CONT_ASSIGN	8837	1	1	100.00
CONT_ASSIGN	8839	1	1	100.00
CONT_ASSIGN	8841	1	1	100.00
CONT_ASSIGN	8843	1	1	100.00
CONT_ASSIGN	8844	1	1	100.00
CONT_ASSIGN	8846	1	1	100.00
CONT_ASSIGN	8848	1	1	100.00
CONT_ASSIGN	8850	1	1	100.00
CONT_ASSIGN	8852	1	1	100.00
CONT_ASSIGN	8854	1	1	100.00
CONT_ASSIGN	8856	1	1	100.00
CONT_ASSIGN	8858	1	1	100.00
CONT_ASSIGN	8860	1	1	100.00
CONT_ASSIGN	8862	1	1	100.00
CONT_ASSIGN	8864	1	1	100.00
CONT_ASSIGN	8866	1	1	100.00
CONT_ASSIGN	8868	1	1	100.00
CONT_ASSIGN	8870	1	1	100.00
CONT_ASSIGN	8872	1	1	100.00
CONT_ASSIGN	8874	1	1	100.00
CONT_ASSIGN	8876	1	1	100.00
CONT_ASSIGN	8878	1	1	100.00
CONT_ASSIGN	8880	1	1	100.00
CONT_ASSIGN	8881	1	1	100.00
CONT_ASSIGN	8883	1	1	100.00
CONT_ASSIGN	8884	1	1	100.00
CONT_ASSIGN	8886	1	1	100.00
CONT_ASSIGN	8888	1	1	100.00
CONT_ASSIGN	8890	1	1	100.00
CONT_ASSIGN	8891	1	1	100.00
CONT_ASSIGN	8893	1	1	100.00
CONT_ASSIGN	8895	1	1	100.00
CONT_ASSIGN	8897	1	1	100.00
CONT_ASSIGN	8899	1	1	100.00
CONT_ASSIGN	8901	1	1	100.00
CONT_ASSIGN	8903	1	1	100.00
CONT_ASSIGN	8905	1	1	100.00
CONT_ASSIGN	8907	1	1	100.00
CONT_ASSIGN	8909	1	1	100.00
CONT_ASSIGN	8911	1	1	100.00
CONT_ASSIGN	8913	1	1	100.00
CONT_ASSIGN	8915	1	1	100.00
CONT_ASSIGN	8916	1	1	100.00
CONT_ASSIGN	8918	1	1	100.00
CONT_ASSIGN	8920	1	1	100.00
CONT_ASSIGN	8922	1	1	100.00
CONT_ASSIGN	8924	1	1	100.00
CONT_ASSIGN	8926	1	1	100.00
CONT_ASSIGN	8928	1	1	100.00
CONT_ASSIGN	8930	1	1	100.00
CONT_ASSIGN	8932	1	1	100.00
CONT_ASSIGN	8934	1	1	100.00
CONT_ASSIGN	8936	1	1	100.00
CONT_ASSIGN	8938	1	1	100.00
CONT_ASSIGN	8940	1	1	100.00
CONT_ASSIGN	8941	1	1	100.00
CONT_ASSIGN	8942	1	1	100.00
CONT_ASSIGN	8944	1	1	100.00
CONT_ASSIGN	8945	1	1	100.00
CONT_ASSIGN	8947	1	1	100.00
CONT_ASSIGN	8948	1	1	100.00
CONT_ASSIGN	8949	1	1	100.00
CONT_ASSIGN	8951	1	1	100.00
CONT_ASSIGN	8953	1	1	100.00
CONT_ASSIGN	8955	1	1	100.00
CONT_ASSIGN	8957	1	1	100.00
CONT_ASSIGN	8959	1	1	100.00
CONT_ASSIGN	8961	1	1	100.00
CONT_ASSIGN	8963	1	1	100.00
CONT_ASSIGN	8965	1	1	100.00
CONT_ASSIGN	8967	1	1	100.00
CONT_ASSIGN	8969	1	1	100.00
CONT_ASSIGN	8971	1	1	100.00
CONT_ASSIGN	8973	1	1	100.00
CONT_ASSIGN	8974	1	1	100.00
CONT_ASSIGN	8976	1	1	100.00
CONT_ASSIGN	8978	1	1	100.00
CONT_ASSIGN	8980	1	1	100.00
CONT_ASSIGN	8982	1	1	100.00
CONT_ASSIGN	8984	1	1	100.00
CONT_ASSIGN	8986	1	1	100.00
CONT_ASSIGN	8988	1	1	100.00
CONT_ASSIGN	8990	1	1	100.00
CONT_ASSIGN	8992	1	1	100.00
CONT_ASSIGN	8994	1	1	100.00
CONT_ASSIGN	8996	1	1	100.00
CONT_ASSIGN	8998	1	1	100.00
CONT_ASSIGN	8999	1	1	100.00
CONT_ASSIGN	9001	1	1	100.00
CONT_ASSIGN	9003	1	1	100.00
CONT_ASSIGN	9005	1	1	100.00
CONT_ASSIGN	9007	1	1	100.00
CONT_ASSIGN	9009	1	1	100.00
CONT_ASSIGN	9011	1	1	100.00
CONT_ASSIGN	9013	1	1	100.00
CONT_ASSIGN	9015	1	1	100.00
CONT_ASSIGN	9017	1	1	100.00
CONT_ASSIGN	9019	1	1	100.00
CONT_ASSIGN	9021	1	1	100.00
CONT_ASSIGN	9023	1	1	100.00
CONT_ASSIGN	9024	1	1	100.00
CONT_ASSIGN	9026	1	1	100.00
CONT_ASSIGN	9028	1	1	100.00
CONT_ASSIGN	9030	1	1	100.00
CONT_ASSIGN	9032	1	1	100.00
CONT_ASSIGN	9034	1	1	100.00
CONT_ASSIGN	9036	1	1	100.00
CONT_ASSIGN	9038	1	1	100.00
CONT_ASSIGN	9040	1	1	100.00
CONT_ASSIGN	9042	1	1	100.00
CONT_ASSIGN	9044	1	1	100.00
CONT_ASSIGN	9046	1	1	100.00
CONT_ASSIGN	9048	1	1	100.00
CONT_ASSIGN	9049	1	1	100.00
CONT_ASSIGN	9051	1	1	100.00
CONT_ASSIGN	9053	1	1	100.00
CONT_ASSIGN	9055	1	1	100.00
CONT_ASSIGN	9057	1	1	100.00
CONT_ASSIGN	9059	1	1	100.00
CONT_ASSIGN	9061	1	1	100.00
CONT_ASSIGN	9063	1	1	100.00
CONT_ASSIGN	9065	1	1	100.00
CONT_ASSIGN	9067	1	1	100.00
CONT_ASSIGN	9069	1	1	100.00
CONT_ASSIGN	9071	1	1	100.00
CONT_ASSIGN	9073	1	1	100.00
CONT_ASSIGN	9074	1	1	100.00
CONT_ASSIGN	9076	1	1	100.00
CONT_ASSIGN	9078	1	1	100.00
CONT_ASSIGN	9080	1	1	100.00
CONT_ASSIGN	9082	1	1	100.00
CONT_ASSIGN	9084	1	1	100.00
CONT_ASSIGN	9086	1	1	100.00
CONT_ASSIGN	9088	1	1	100.00
CONT_ASSIGN	9090	1	1	100.00
CONT_ASSIGN	9092	1	1	100.00
CONT_ASSIGN	9094	1	1	100.00
CONT_ASSIGN	9096	1	1	100.00
CONT_ASSIGN	9098	1	1	100.00
CONT_ASSIGN	9099	1	1	100.00
CONT_ASSIGN	9101	1	1	100.00
CONT_ASSIGN	9103	1	1	100.00
CONT_ASSIGN	9105	1	1	100.00
CONT_ASSIGN	9107	1	1	100.00
CONT_ASSIGN	9109	1	1	100.00
CONT_ASSIGN	9110	1	1	100.00
CONT_ASSIGN	9112	1	1	100.00
CONT_ASSIGN	9114	1	1	100.00
CONT_ASSIGN	9116	1	1	100.00
CONT_ASSIGN	9118	1	1	100.00
CONT_ASSIGN	9120	1	1	100.00
CONT_ASSIGN	9121	1	1	100.00
CONT_ASSIGN	9123	1	1	100.00
CONT_ASSIGN	9125	1	1	100.00
CONT_ASSIGN	9127	1	1	100.00
CONT_ASSIGN	9129	1	1	100.00
CONT_ASSIGN	9131	1	1	100.00
CONT_ASSIGN	9132	1	1	100.00
CONT_ASSIGN	9134	1	1	100.00
CONT_ASSIGN	9136	1	1	100.00
CONT_ASSIGN	9138	1	1	100.00
CONT_ASSIGN	9140	1	1	100.00
CONT_ASSIGN	9142	1	1	100.00
CONT_ASSIGN	9143	1	1	100.00
CONT_ASSIGN	9145	1	1	100.00
CONT_ASSIGN	9147	1	1	100.00
CONT_ASSIGN	9149	1	1	100.00
CONT_ASSIGN	9151	1	1	100.00
CONT_ASSIGN	9153	1	1	100.00
CONT_ASSIGN	9154	1	1	100.00
CONT_ASSIGN	9156	1	1	100.00
CONT_ASSIGN	9158	1	1	100.00
CONT_ASSIGN	9160	1	1	100.00
CONT_ASSIGN	9162	1	1	100.00
CONT_ASSIGN	9164	1	1	100.00
CONT_ASSIGN	9165	1	1	100.00
CONT_ASSIGN	9167	1	1	100.00
CONT_ASSIGN	9169	1	1	100.00
CONT_ASSIGN	9171	1	1	100.00
CONT_ASSIGN	9173	1	1	100.00
CONT_ASSIGN	9175	1	1	100.00
CONT_ASSIGN	9176	1	1	100.00
CONT_ASSIGN	9178	1	1	100.00
CONT_ASSIGN	9180	1	1	100.00
CONT_ASSIGN	9182	1	1	100.00
CONT_ASSIGN	9184	1	1	100.00
CONT_ASSIGN	9186	1	1	100.00
CONT_ASSIGN	9187	1	1	100.00
CONT_ASSIGN	9189	1	1	100.00
CONT_ASSIGN	9191	1	1	100.00
CONT_ASSIGN	9193	1	1	100.00
CONT_ASSIGN	9195	1	1	100.00
CONT_ASSIGN	9197	1	1	100.00
CONT_ASSIGN	9198	1	1	100.00
CONT_ASSIGN	9200	1	1	100.00
CONT_ASSIGN	9202	1	1	100.00
CONT_ASSIGN	9204	1	1	100.00
CONT_ASSIGN	9206	1	1	100.00
CONT_ASSIGN	9208	1	1	100.00
CONT_ASSIGN	9209	1	1	100.00
CONT_ASSIGN	9211	1	1	100.00
CONT_ASSIGN	9213	1	1	100.00
CONT_ASSIGN	9215	1	1	100.00
CONT_ASSIGN	9217	1	1	100.00
CONT_ASSIGN	9219	1	1	100.00
CONT_ASSIGN	9220	1	1	100.00
CONT_ASSIGN	9222	1	1	100.00
CONT_ASSIGN	9224	1	1	100.00
CONT_ASSIGN	9226	1	1	100.00
CONT_ASSIGN	9228	1	1	100.00
CONT_ASSIGN	9230	1	1	100.00
CONT_ASSIGN	9231	1	1	100.00
CONT_ASSIGN	9233	1	1	100.00
CONT_ASSIGN	9235	1	1	100.00
CONT_ASSIGN	9237	1	1	100.00
CONT_ASSIGN	9239	1	1	100.00
CONT_ASSIGN	9241	1	1	100.00
CONT_ASSIGN	9243	1	1	100.00
CONT_ASSIGN	9245	1	1	100.00
CONT_ASSIGN	9247	1	1	100.00
CONT_ASSIGN	9249	1	1	100.00
CONT_ASSIGN	9251	1	1	100.00
CONT_ASSIGN	9253	1	1	100.00
CONT_ASSIGN	9255	1	1	100.00
CONT_ASSIGN	9256	1	1	100.00
CONT_ASSIGN	9258	1	1	100.00
CONT_ASSIGN	9260	1	1	100.00
CONT_ASSIGN	9262	1	1	100.00
CONT_ASSIGN	9264	1	1	100.00
CONT_ASSIGN	9266	1	1	100.00
CONT_ASSIGN	9268	1	1	100.00
CONT_ASSIGN	9270	1	1	100.00
CONT_ASSIGN	9272	1	1	100.00
CONT_ASSIGN	9274	1	1	100.00
CONT_ASSIGN	9276	1	1	100.00
CONT_ASSIGN	9278	1	1	100.00
CONT_ASSIGN	9280	1	1	100.00
CONT_ASSIGN	9281	1	1	100.00
CONT_ASSIGN	9282	1	1	100.00
CONT_ASSIGN	9284	1	1	100.00
CONT_ASSIGN	9286	1	1	100.00
CONT_ASSIGN	9287	1	1	100.00
CONT_ASSIGN	9288	1	1	100.00
CONT_ASSIGN	9290	1	1	100.00
CONT_ASSIGN	9292	1	1	100.00
CONT_ASSIGN	9293	1	1	100.00
CONT_ASSIGN	9294	1	1	100.00
CONT_ASSIGN	9296	1	1	100.00
CONT_ASSIGN	9298	1	1	100.00
CONT_ASSIGN	9300	1	1	100.00
CONT_ASSIGN	9302	1	1	100.00
CONT_ASSIGN	9304	1	1	100.00
CONT_ASSIGN	9306	1	1	100.00
CONT_ASSIGN	9308	1	1	100.00
CONT_ASSIGN	9310	1	1	100.00
CONT_ASSIGN	9312	1	1	100.00
CONT_ASSIGN	9313	1	1	100.00
CONT_ASSIGN	9315	1	1	100.00
CONT_ASSIGN	9317	1	1	100.00
CONT_ASSIGN	9319	1	1	100.00
CONT_ASSIGN	9321	1	1	100.00
CONT_ASSIGN	9323	1	1	100.00
CONT_ASSIGN	9325	1	1	100.00
CONT_ASSIGN	9326	1	1	100.00
CONT_ASSIGN	9329	1	1	100.00
CONT_ASSIGN	9331	1	1	100.00
CONT_ASSIGN	9333	1	1	100.00
CONT_ASSIGN	9335	1	1	100.00
CONT_ASSIGN	9336	1	1	100.00
CONT_ASSIGN	9337	1	1	100.00
CONT_ASSIGN	9339	1	1	100.00
CONT_ASSIGN	9341	1	1	100.00
CONT_ASSIGN	9343	1	1	100.00
CONT_ASSIGN	9345	1	1	100.00
CONT_ASSIGN	9347	1	1	100.00
CONT_ASSIGN	9349	1	1	100.00
CONT_ASSIGN	9350	1	1	100.00
CONT_ASSIGN	9351	1	1	100.00
CONT_ASSIGN	9353	1	1	100.00
CONT_ASSIGN	9355	1	1	100.00
CONT_ASSIGN	9357	1	1	100.00
CONT_ASSIGN	9359	1	1	100.00
CONT_ASSIGN	9361	1	1	100.00
CONT_ASSIGN	9362	1	1	100.00
CONT_ASSIGN	9363	1	1	100.00
CONT_ASSIGN	9365	1	1	100.00
CONT_ASSIGN	9367	1	1	100.00
CONT_ASSIGN	9368	1	1	100.00
CONT_ASSIGN	9369	1	1	100.00
CONT_ASSIGN	9371	1	1	100.00
CONT_ASSIGN	9373	1	1	100.00
CONT_ASSIGN	9375	1	1	100.00
CONT_ASSIGN	9377	1	1	100.00
CONT_ASSIGN	9379	1	1	100.00
ALWAYS	9383	44	44	100.00
ALWAYS	9431	311	311	100.00
CONT_ASSIGN	9881	1	1	100.00
ALWAYS	9883	4	4	100.00
CONT_ASSIGN	9904	1	1	100.00
CONT_ASSIGN	9905	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Module : usbdev_reg_top

	Total	Covered	Percent
Conditions	477	468	98.11
Logical	477	468	98.11
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
65-8916	100.00
8941-9881	94.58

---

Branch Coverage for Module : usbdev_reg_top

	Line No.	Total	Covered	Percent
Branches		56	56	100.00
TERNARY	8729	2	2	100.00
IF	75	3	3	100.00
TERNARY	132	2	2	100.00
IF	138	2	2	100.00
CASE	9432	44	44	100.00
CASE	9884	3	3	100.00

8729         assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

75             if (!rst_ni) begin
               -1-  
76               err_q <= '0;
                 ==>
77             end else if (intg_err || reg_we_err) begin
                        -2-  
78               err_q <= 1'b1;
                 ==>
79             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T201,T202,T203
0	0	Covered	T1,T2,T3

132            reg_steer =
                          
133                tl_i.a_address[AW-1:0] inside {[2048:4095]} ? 1'd0 :
                                                               -1-  
                                                               ==>  
                                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T28
0	Covered	T1,T2,T3

138            if (intg_err) begin
               -1-  
139              reg_steer = 1'd1;
                 ==>
140            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T206,T233,T240
0	Covered	T1,T2,T3

9432           unique case (1'b1)
                      -1-  
9433             addr_hit[0]: begin
9434               reg_rdata_next[0] = intr_state_pkt_received_qs;
                   ==>
9435               reg_rdata_next[1] = intr_state_pkt_sent_qs;
9436               reg_rdata_next[2] = intr_state_disconnected_qs;
9437               reg_rdata_next[3] = intr_state_host_lost_qs;
9438               reg_rdata_next[4] = intr_state_link_reset_qs;
9439               reg_rdata_next[5] = intr_state_link_suspend_qs;
9440               reg_rdata_next[6] = intr_state_link_resume_qs;
9441               reg_rdata_next[7] = intr_state_av_out_empty_qs;
9442               reg_rdata_next[8] = intr_state_rx_full_qs;
9443               reg_rdata_next[9] = intr_state_av_overflow_qs;
9444               reg_rdata_next[10] = intr_state_link_in_err_qs;
9445               reg_rdata_next[11] = intr_state_rx_crc_err_qs;
9446               reg_rdata_next[12] = intr_state_rx_pid_err_qs;
9447               reg_rdata_next[13] = intr_state_rx_bitstuff_err_qs;
9448               reg_rdata_next[14] = intr_state_frame_qs;
9449               reg_rdata_next[15] = intr_state_powered_qs;
9450               reg_rdata_next[16] = intr_state_link_out_err_qs;
9451               reg_rdata_next[17] = intr_state_av_setup_empty_qs;
9452             end
9453       
9454             addr_hit[1]: begin
9455               reg_rdata_next[0] = intr_enable_pkt_received_qs;
                   ==>
9456               reg_rdata_next[1] = intr_enable_pkt_sent_qs;
9457               reg_rdata_next[2] = intr_enable_disconnected_qs;
9458               reg_rdata_next[3] = intr_enable_host_lost_qs;
9459               reg_rdata_next[4] = intr_enable_link_reset_qs;
9460               reg_rdata_next[5] = intr_enable_link_suspend_qs;
9461               reg_rdata_next[6] = intr_enable_link_resume_qs;
9462               reg_rdata_next[7] = intr_enable_av_out_empty_qs;
9463               reg_rdata_next[8] = intr_enable_rx_full_qs;
9464               reg_rdata_next[9] = intr_enable_av_overflow_qs;
9465               reg_rdata_next[10] = intr_enable_link_in_err_qs;
9466               reg_rdata_next[11] = intr_enable_rx_crc_err_qs;
9467               reg_rdata_next[12] = intr_enable_rx_pid_err_qs;
9468               reg_rdata_next[13] = intr_enable_rx_bitstuff_err_qs;
9469               reg_rdata_next[14] = intr_enable_frame_qs;
9470               reg_rdata_next[15] = intr_enable_powered_qs;
9471               reg_rdata_next[16] = intr_enable_link_out_err_qs;
9472               reg_rdata_next[17] = intr_enable_av_setup_empty_qs;
9473             end
9474       
9475             addr_hit[2]: begin
9476               reg_rdata_next[0] = '0;
                   ==>
9477               reg_rdata_next[1] = '0;
9478               reg_rdata_next[2] = '0;
9479               reg_rdata_next[3] = '0;
9480               reg_rdata_next[4] = '0;
9481               reg_rdata_next[5] = '0;
9482               reg_rdata_next[6] = '0;
9483               reg_rdata_next[7] = '0;
9484               reg_rdata_next[8] = '0;
9485               reg_rdata_next[9] = '0;
9486               reg_rdata_next[10] = '0;
9487               reg_rdata_next[11] = '0;
9488               reg_rdata_next[12] = '0;
9489               reg_rdata_next[13] = '0;
9490               reg_rdata_next[14] = '0;
9491               reg_rdata_next[15] = '0;
9492               reg_rdata_next[16] = '0;
9493               reg_rdata_next[17] = '0;
9494             end
9495       
9496             addr_hit[3]: begin
9497               reg_rdata_next[0] = '0;
                   ==>
9498             end
9499       
9500             addr_hit[4]: begin
9501               reg_rdata_next[0] = usbctrl_enable_qs;
                   ==>
9502               reg_rdata_next[1] = '0;
9503               reg_rdata_next[22:16] = usbctrl_device_address_qs;
9504             end
9505       
9506             addr_hit[5]: begin
9507               reg_rdata_next[0] = ep_out_enable_enable_0_qs;
                   ==>
9508               reg_rdata_next[1] = ep_out_enable_enable_1_qs;
9509               reg_rdata_next[2] = ep_out_enable_enable_2_qs;
9510               reg_rdata_next[3] = ep_out_enable_enable_3_qs;
9511               reg_rdata_next[4] = ep_out_enable_enable_4_qs;
9512               reg_rdata_next[5] = ep_out_enable_enable_5_qs;
9513               reg_rdata_next[6] = ep_out_enable_enable_6_qs;
9514               reg_rdata_next[7] = ep_out_enable_enable_7_qs;
9515               reg_rdata_next[8] = ep_out_enable_enable_8_qs;
9516               reg_rdata_next[9] = ep_out_enable_enable_9_qs;
9517               reg_rdata_next[10] = ep_out_enable_enable_10_qs;
9518               reg_rdata_next[11] = ep_out_enable_enable_11_qs;
9519             end
9520       
9521             addr_hit[6]: begin
9522               reg_rdata_next[0] = ep_in_enable_enable_0_qs;
                   ==>
9523               reg_rdata_next[1] = ep_in_enable_enable_1_qs;
9524               reg_rdata_next[2] = ep_in_enable_enable_2_qs;
9525               reg_rdata_next[3] = ep_in_enable_enable_3_qs;
9526               reg_rdata_next[4] = ep_in_enable_enable_4_qs;
9527               reg_rdata_next[5] = ep_in_enable_enable_5_qs;
9528               reg_rdata_next[6] = ep_in_enable_enable_6_qs;
9529               reg_rdata_next[7] = ep_in_enable_enable_7_qs;
9530               reg_rdata_next[8] = ep_in_enable_enable_8_qs;
9531               reg_rdata_next[9] = ep_in_enable_enable_9_qs;
9532               reg_rdata_next[10] = ep_in_enable_enable_10_qs;
9533               reg_rdata_next[11] = ep_in_enable_enable_11_qs;
9534             end
9535       
9536             addr_hit[7]: begin
9537               reg_rdata_next[10:0] = usbstat_frame_qs;
                   ==>
9538               reg_rdata_next[11] = usbstat_host_lost_qs;
9539               reg_rdata_next[14:12] = usbstat_link_state_qs;
9540               reg_rdata_next[15] = usbstat_sense_qs;
9541               reg_rdata_next[19:16] = usbstat_av_out_depth_qs;
9542               reg_rdata_next[22:20] = usbstat_av_setup_depth_qs;
9543               reg_rdata_next[23] = usbstat_av_out_full_qs;
9544               reg_rdata_next[27:24] = usbstat_rx_depth_qs;
9545               reg_rdata_next[30] = usbstat_av_setup_full_qs;
9546               reg_rdata_next[31] = usbstat_rx_empty_qs;
9547             end
9548       
9549             addr_hit[8]: begin
9550               reg_rdata_next[4:0] = '0;
                   ==>
9551             end
9552       
9553             addr_hit[9]: begin
9554               reg_rdata_next[4:0] = '0;
                   ==>
9555             end
9556       
9557             addr_hit[10]: begin
9558               reg_rdata_next[4:0] = rxfifo_buffer_qs;
                   ==>
9559               reg_rdata_next[14:8] = rxfifo_size_qs;
9560               reg_rdata_next[19] = rxfifo_setup_qs;
9561               reg_rdata_next[23:20] = rxfifo_ep_qs;
9562             end
9563       
9564             addr_hit[11]: begin
9565               reg_rdata_next[0] = rxenable_setup_setup_0_qs;
                   ==>
9566               reg_rdata_next[1] = rxenable_setup_setup_1_qs;
9567               reg_rdata_next[2] = rxenable_setup_setup_2_qs;
9568               reg_rdata_next[3] = rxenable_setup_setup_3_qs;
9569               reg_rdata_next[4] = rxenable_setup_setup_4_qs;
9570               reg_rdata_next[5] = rxenable_setup_setup_5_qs;
9571               reg_rdata_next[6] = rxenable_setup_setup_6_qs;
9572               reg_rdata_next[7] = rxenable_setup_setup_7_qs;
9573               reg_rdata_next[8] = rxenable_setup_setup_8_qs;
9574               reg_rdata_next[9] = rxenable_setup_setup_9_qs;
9575               reg_rdata_next[10] = rxenable_setup_setup_10_qs;
9576               reg_rdata_next[11] = rxenable_setup_setup_11_qs;
9577             end
9578       
9579             addr_hit[12]: begin
9580               reg_rdata_next[0] = rxenable_out_out_0_qs;
                   ==>
9581               reg_rdata_next[1] = rxenable_out_out_1_qs;
9582               reg_rdata_next[2] = rxenable_out_out_2_qs;
9583               reg_rdata_next[3] = rxenable_out_out_3_qs;
9584               reg_rdata_next[4] = rxenable_out_out_4_qs;
9585               reg_rdata_next[5] = rxenable_out_out_5_qs;
9586               reg_rdata_next[6] = rxenable_out_out_6_qs;
9587               reg_rdata_next[7] = rxenable_out_out_7_qs;
9588               reg_rdata_next[8] = rxenable_out_out_8_qs;
9589               reg_rdata_next[9] = rxenable_out_out_9_qs;
9590               reg_rdata_next[10] = rxenable_out_out_10_qs;
9591               reg_rdata_next[11] = rxenable_out_out_11_qs;
9592             end
9593       
9594             addr_hit[13]: begin
9595               reg_rdata_next[0] = set_nak_out_enable_0_qs;
                   ==>
9596               reg_rdata_next[1] = set_nak_out_enable_1_qs;
9597               reg_rdata_next[2] = set_nak_out_enable_2_qs;
9598               reg_rdata_next[3] = set_nak_out_enable_3_qs;
9599               reg_rdata_next[4] = set_nak_out_enable_4_qs;
9600               reg_rdata_next[5] = set_nak_out_enable_5_qs;
9601               reg_rdata_next[6] = set_nak_out_enable_6_qs;
9602               reg_rdata_next[7] = set_nak_out_enable_7_qs;
9603               reg_rdata_next[8] = set_nak_out_enable_8_qs;
9604               reg_rdata_next[9] = set_nak_out_enable_9_qs;
9605               reg_rdata_next[10] = set_nak_out_enable_10_qs;
9606               reg_rdata_next[11] = set_nak_out_enable_11_qs;
9607             end
9608       
9609             addr_hit[14]: begin
9610               reg_rdata_next[0] = in_sent_sent_0_qs;
                   ==>
9611               reg_rdata_next[1] = in_sent_sent_1_qs;
9612               reg_rdata_next[2] = in_sent_sent_2_qs;
9613               reg_rdata_next[3] = in_sent_sent_3_qs;
9614               reg_rdata_next[4] = in_sent_sent_4_qs;
9615               reg_rdata_next[5] = in_sent_sent_5_qs;
9616               reg_rdata_next[6] = in_sent_sent_6_qs;
9617               reg_rdata_next[7] = in_sent_sent_7_qs;
9618               reg_rdata_next[8] = in_sent_sent_8_qs;
9619               reg_rdata_next[9] = in_sent_sent_9_qs;
9620               reg_rdata_next[10] = in_sent_sent_10_qs;
9621               reg_rdata_next[11] = in_sent_sent_11_qs;
9622             end
9623       
9624             addr_hit[15]: begin
9625               reg_rdata_next[0] = out_stall_endpoint_0_qs;
                   ==>
9626               reg_rdata_next[1] = out_stall_endpoint_1_qs;
9627               reg_rdata_next[2] = out_stall_endpoint_2_qs;
9628               reg_rdata_next[3] = out_stall_endpoint_3_qs;
9629               reg_rdata_next[4] = out_stall_endpoint_4_qs;
9630               reg_rdata_next[5] = out_stall_endpoint_5_qs;
9631               reg_rdata_next[6] = out_stall_endpoint_6_qs;
9632               reg_rdata_next[7] = out_stall_endpoint_7_qs;
9633               reg_rdata_next[8] = out_stall_endpoint_8_qs;
9634               reg_rdata_next[9] = out_stall_endpoint_9_qs;
9635               reg_rdata_next[10] = out_stall_endpoint_10_qs;
9636               reg_rdata_next[11] = out_stall_endpoint_11_qs;
9637             end
9638       
9639             addr_hit[16]: begin
9640               reg_rdata_next[0] = in_stall_endpoint_0_qs;
                   ==>
9641               reg_rdata_next[1] = in_stall_endpoint_1_qs;
9642               reg_rdata_next[2] = in_stall_endpoint_2_qs;
9643               reg_rdata_next[3] = in_stall_endpoint_3_qs;
9644               reg_rdata_next[4] = in_stall_endpoint_4_qs;
9645               reg_rdata_next[5] = in_stall_endpoint_5_qs;
9646               reg_rdata_next[6] = in_stall_endpoint_6_qs;
9647               reg_rdata_next[7] = in_stall_endpoint_7_qs;
9648               reg_rdata_next[8] = in_stall_endpoint_8_qs;
9649               reg_rdata_next[9] = in_stall_endpoint_9_qs;
9650               reg_rdata_next[10] = in_stall_endpoint_10_qs;
9651               reg_rdata_next[11] = in_stall_endpoint_11_qs;
9652             end
9653       
9654             addr_hit[17]: begin
9655               reg_rdata_next[4:0] = configin_0_buffer_0_qs;
                   ==>
9656               reg_rdata_next[14:8] = configin_0_size_0_qs;
9657               reg_rdata_next[29] = configin_0_sending_0_qs;
9658               reg_rdata_next[30] = configin_0_pend_0_qs;
9659               reg_rdata_next[31] = configin_0_rdy_0_qs;
9660             end
9661       
9662             addr_hit[18]: begin
9663               reg_rdata_next[4:0] = configin_1_buffer_1_qs;
                   ==>
9664               reg_rdata_next[14:8] = configin_1_size_1_qs;
9665               reg_rdata_next[29] = configin_1_sending_1_qs;
9666               reg_rdata_next[30] = configin_1_pend_1_qs;
9667               reg_rdata_next[31] = configin_1_rdy_1_qs;
9668             end
9669       
9670             addr_hit[19]: begin
9671               reg_rdata_next[4:0] = configin_2_buffer_2_qs;
                   ==>
9672               reg_rdata_next[14:8] = configin_2_size_2_qs;
9673               reg_rdata_next[29] = configin_2_sending_2_qs;
9674               reg_rdata_next[30] = configin_2_pend_2_qs;
9675               reg_rdata_next[31] = configin_2_rdy_2_qs;
9676             end
9677       
9678             addr_hit[20]: begin
9679               reg_rdata_next[4:0] = configin_3_buffer_3_qs;
                   ==>
9680               reg_rdata_next[14:8] = configin_3_size_3_qs;
9681               reg_rdata_next[29] = configin_3_sending_3_qs;
9682               reg_rdata_next[30] = configin_3_pend_3_qs;
9683               reg_rdata_next[31] = configin_3_rdy_3_qs;
9684             end
9685       
9686             addr_hit[21]: begin
9687               reg_rdata_next[4:0] = configin_4_buffer_4_qs;
                   ==>
9688               reg_rdata_next[14:8] = configin_4_size_4_qs;
9689               reg_rdata_next[29] = configin_4_sending_4_qs;
9690               reg_rdata_next[30] = configin_4_pend_4_qs;
9691               reg_rdata_next[31] = configin_4_rdy_4_qs;
9692             end
9693       
9694             addr_hit[22]: begin
9695               reg_rdata_next[4:0] = configin_5_buffer_5_qs;
                   ==>
9696               reg_rdata_next[14:8] = configin_5_size_5_qs;
9697               reg_rdata_next[29] = configin_5_sending_5_qs;
9698               reg_rdata_next[30] = configin_5_pend_5_qs;
9699               reg_rdata_next[31] = configin_5_rdy_5_qs;
9700             end
9701       
9702             addr_hit[23]: begin
9703               reg_rdata_next[4:0] = configin_6_buffer_6_qs;
                   ==>
9704               reg_rdata_next[14:8] = configin_6_size_6_qs;
9705               reg_rdata_next[29] = configin_6_sending_6_qs;
9706               reg_rdata_next[30] = configin_6_pend_6_qs;
9707               reg_rdata_next[31] = configin_6_rdy_6_qs;
9708             end
9709       
9710             addr_hit[24]: begin
9711               reg_rdata_next[4:0] = configin_7_buffer_7_qs;
                   ==>
9712               reg_rdata_next[14:8] = configin_7_size_7_qs;
9713               reg_rdata_next[29] = configin_7_sending_7_qs;
9714               reg_rdata_next[30] = configin_7_pend_7_qs;
9715               reg_rdata_next[31] = configin_7_rdy_7_qs;
9716             end
9717       
9718             addr_hit[25]: begin
9719               reg_rdata_next[4:0] = configin_8_buffer_8_qs;
                   ==>
9720               reg_rdata_next[14:8] = configin_8_size_8_qs;
9721               reg_rdata_next[29] = configin_8_sending_8_qs;
9722               reg_rdata_next[30] = configin_8_pend_8_qs;
9723               reg_rdata_next[31] = configin_8_rdy_8_qs;
9724             end
9725       
9726             addr_hit[26]: begin
9727               reg_rdata_next[4:0] = configin_9_buffer_9_qs;
                   ==>
9728               reg_rdata_next[14:8] = configin_9_size_9_qs;
9729               reg_rdata_next[29] = configin_9_sending_9_qs;
9730               reg_rdata_next[30] = configin_9_pend_9_qs;
9731               reg_rdata_next[31] = configin_9_rdy_9_qs;
9732             end
9733       
9734             addr_hit[27]: begin
9735               reg_rdata_next[4:0] = configin_10_buffer_10_qs;
                   ==>
9736               reg_rdata_next[14:8] = configin_10_size_10_qs;
9737               reg_rdata_next[29] = configin_10_sending_10_qs;
9738               reg_rdata_next[30] = configin_10_pend_10_qs;
9739               reg_rdata_next[31] = configin_10_rdy_10_qs;
9740             end
9741       
9742             addr_hit[28]: begin
9743               reg_rdata_next[4:0] = configin_11_buffer_11_qs;
                   ==>
9744               reg_rdata_next[14:8] = configin_11_size_11_qs;
9745               reg_rdata_next[29] = configin_11_sending_11_qs;
9746               reg_rdata_next[30] = configin_11_pend_11_qs;
9747               reg_rdata_next[31] = configin_11_rdy_11_qs;
9748             end
9749       
9750             addr_hit[29]: begin
9751               reg_rdata_next[0] = out_iso_iso_0_qs;
                   ==>
9752               reg_rdata_next[1] = out_iso_iso_1_qs;
9753               reg_rdata_next[2] = out_iso_iso_2_qs;
9754               reg_rdata_next[3] = out_iso_iso_3_qs;
9755               reg_rdata_next[4] = out_iso_iso_4_qs;
9756               reg_rdata_next[5] = out_iso_iso_5_qs;
9757               reg_rdata_next[6] = out_iso_iso_6_qs;
9758               reg_rdata_next[7] = out_iso_iso_7_qs;
9759               reg_rdata_next[8] = out_iso_iso_8_qs;
9760               reg_rdata_next[9] = out_iso_iso_9_qs;
9761               reg_rdata_next[10] = out_iso_iso_10_qs;
9762               reg_rdata_next[11] = out_iso_iso_11_qs;
9763             end
9764       
9765             addr_hit[30]: begin
9766               reg_rdata_next[0] = in_iso_iso_0_qs;
                   ==>
9767               reg_rdata_next[1] = in_iso_iso_1_qs;
9768               reg_rdata_next[2] = in_iso_iso_2_qs;
9769               reg_rdata_next[3] = in_iso_iso_3_qs;
9770               reg_rdata_next[4] = in_iso_iso_4_qs;
9771               reg_rdata_next[5] = in_iso_iso_5_qs;
9772               reg_rdata_next[6] = in_iso_iso_6_qs;
9773               reg_rdata_next[7] = in_iso_iso_7_qs;
9774               reg_rdata_next[8] = in_iso_iso_8_qs;
9775               reg_rdata_next[9] = in_iso_iso_9_qs;
9776               reg_rdata_next[10] = in_iso_iso_10_qs;
9777               reg_rdata_next[11] = in_iso_iso_11_qs;
9778             end
9779       
9780             addr_hit[31]: begin
9781               reg_rdata_next[11:0] = out_data_toggle_status_qs;
                   ==>
9782               reg_rdata_next[27:16] = out_data_toggle_mask_qs;
9783             end
9784       
9785             addr_hit[32]: begin
9786               reg_rdata_next[11:0] = in_data_toggle_status_qs;
                   ==>
9787               reg_rdata_next[27:16] = in_data_toggle_mask_qs;
9788             end
9789       
9790             addr_hit[33]: begin
9791               reg_rdata_next[0] = phy_pins_sense_rx_dp_i_qs;
                   ==>
9792               reg_rdata_next[1] = phy_pins_sense_rx_dn_i_qs;
9793               reg_rdata_next[2] = phy_pins_sense_rx_d_i_qs;
9794               reg_rdata_next[8] = phy_pins_sense_tx_dp_o_qs;
9795               reg_rdata_next[9] = phy_pins_sense_tx_dn_o_qs;
9796               reg_rdata_next[10] = phy_pins_sense_tx_d_o_qs;
9797               reg_rdata_next[11] = phy_pins_sense_tx_se0_o_qs;
9798               reg_rdata_next[12] = phy_pins_sense_tx_oe_o_qs;
9799               reg_rdata_next[16] = phy_pins_sense_pwr_sense_qs;
9800             end
9801       
9802             addr_hit[34]: begin
9803               reg_rdata_next[0] = phy_pins_drive_dp_o_qs;
                   ==>
9804               reg_rdata_next[1] = phy_pins_drive_dn_o_qs;
9805               reg_rdata_next[2] = phy_pins_drive_d_o_qs;
9806               reg_rdata_next[3] = phy_pins_drive_se0_o_qs;
9807               reg_rdata_next[4] = phy_pins_drive_oe_o_qs;
9808               reg_rdata_next[5] = phy_pins_drive_rx_enable_o_qs;
9809               reg_rdata_next[6] = phy_pins_drive_dp_pullup_en_o_qs;
9810               reg_rdata_next[7] = phy_pins_drive_dn_pullup_en_o_qs;
9811               reg_rdata_next[16] = phy_pins_drive_en_qs;
9812             end
9813       
9814             addr_hit[35]: begin
9815               reg_rdata_next[0] = phy_config_use_diff_rcvr_qs;
                   ==>
9816               reg_rdata_next[1] = phy_config_tx_use_d_se0_qs;
9817               reg_rdata_next[2] = phy_config_eop_single_bit_qs;
9818               reg_rdata_next[5] = phy_config_pinflip_qs;
9819               reg_rdata_next[6] = phy_config_usb_ref_disable_qs;
9820               reg_rdata_next[7] = phy_config_tx_osc_test_mode_qs;
9821             end
9822       
9823             addr_hit[36]: begin
9824               reg_rdata_next = DW'(wake_control_qs);
                   ==>
9825             end
9826             addr_hit[37]: begin
9827               reg_rdata_next = DW'(wake_events_qs);
                   ==>
9828             end
9829             addr_hit[38]: begin
9830               reg_rdata_next[0] = '0;
                   ==>
9831               reg_rdata_next[1] = '0;
9832               reg_rdata_next[2] = '0;
9833             end
9834       
9835             addr_hit[39]: begin
9836               reg_rdata_next[7:0] = count_out_count_qs;
                   ==>
9837               reg_rdata_next[12] = count_out_datatog_out_qs;
9838               reg_rdata_next[13] = count_out_drop_rx_qs;
9839               reg_rdata_next[14] = count_out_drop_avout_qs;
9840               reg_rdata_next[15] = count_out_ign_avsetup_qs;
9841               reg_rdata_next[27:16] = count_out_endpoints_qs;
9842               reg_rdata_next[31] = '0;
9843             end
9844       
9845             addr_hit[40]: begin
9846               reg_rdata_next[7:0] = count_in_count_qs;
                   ==>
9847               reg_rdata_next[13] = count_in_nodata_qs;
9848               reg_rdata_next[14] = count_in_nak_qs;
9849               reg_rdata_next[15] = count_in_timeout_qs;
9850               reg_rdata_next[27:16] = count_in_endpoints_qs;
9851               reg_rdata_next[31] = '0;
9852             end
9853       
9854             addr_hit[41]: begin
9855               reg_rdata_next[7:0] = count_nodata_in_count_qs;
                   ==>
9856               reg_rdata_next[27:16] = count_nodata_in_endpoints_qs;
9857               reg_rdata_next[31] = '0;
9858             end
9859       
9860             addr_hit[42]: begin
9861               reg_rdata_next[7:0] = count_errors_count_qs;
                   ==>
9862               reg_rdata_next[27] = count_errors_pid_invalid_qs;
9863               reg_rdata_next[28] = count_errors_bitstuff_qs;
9864               reg_rdata_next[29] = count_errors_crc16_qs;
9865               reg_rdata_next[30] = count_errors_crc5_qs;
9866               reg_rdata_next[31] = '0;
9867             end
9868       
9869             default: begin
9870               reg_rdata_next = '1;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T2,T29,T41
addr_hit[3]	Covered	T2,T29,T41
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T28
addr_hit[6]	Covered	T2,T29,T41
addr_hit[7]	Covered	T1,T2,T29
addr_hit[8]	Covered	T2,T3,T28
addr_hit[9]	Covered	T1,T2,T29
addr_hit[10]	Covered	T2,T28,T29
addr_hit[11]	Covered	T1,T2,T29
addr_hit[12]	Covered	T2,T28,T29
addr_hit[13]	Covered	T2,T29,T41
addr_hit[14]	Covered	T2,T29,T41
addr_hit[15]	Covered	T2,T29,T41
addr_hit[16]	Covered	T2,T29,T41
addr_hit[17]	Covered	T2,T29,T41
addr_hit[18]	Covered	T2,T28,T29
addr_hit[19]	Covered	T2,T29,T41
addr_hit[20]	Covered	T2,T29,T41
addr_hit[21]	Covered	T2,T29,T41
addr_hit[22]	Covered	T2,T29,T41
addr_hit[23]	Covered	T2,T29,T41
addr_hit[24]	Covered	T2,T29,T41
addr_hit[25]	Covered	T2,T29,T41
addr_hit[26]	Covered	T2,T29,T41
addr_hit[27]	Covered	T2,T29,T41
addr_hit[28]	Covered	T2,T29,T41
addr_hit[29]	Covered	T2,T29,T41
addr_hit[30]	Covered	T2,T29,T41
addr_hit[31]	Covered	T1,T2,T29
addr_hit[32]	Covered	T2,T29,T41
addr_hit[33]	Covered	T2,T29,T41
addr_hit[34]	Covered	T2,T29,T41
addr_hit[35]	Covered	T1,T2,T3
addr_hit[36]	Covered	T2,T29,T41
addr_hit[37]	Covered	T2,T29,T41
addr_hit[38]	Covered	T2,T29,T41
addr_hit[39]	Covered	T2,T29,T41
addr_hit[40]	Covered	T2,T29,T41
addr_hit[41]	Covered	T2,T29,T41
addr_hit[42]	Covered	T2,T29,T41
default	Covered	T1,T2,T3

9884           unique case (1'b1)
                      -1-  
9885             addr_hit[36]: begin
9886               reg_busy_sel = wake_control_busy;
                   ==>
9887             end
9888             addr_hit[37]: begin
9889               reg_busy_sel = wake_events_busy;
                   ==>
9890             end
9891             default: begin
9892               reg_busy_sel  = '0;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[36]	Covered	T2,T29,T41
addr_hit[37]	Covered	T2,T29,T41
default	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	582225092	19855689	0	0
reAfterRv	582225092	19855689	0	0
rePulse	582225092	19522715	0	0
wePulse	582225092	332974	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	582225092	19855689	0	0
T1	7293	20	0	0
T2	7698	12	0	0
T3	6346	22	0	0
T28	8471	12	0	0
T29	21708	70	0	0
T30	38925	190	0	0
T31	7561	19	0	0
T32	48746	127	0	0
T41	7600	11	0	0
T42	1581	7	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	582225092	19855689	0	0
T1	7293	20	0	0
T2	7698	12	0	0
T3	6346	22	0	0
T28	8471	12	0	0
T29	21708	70	0	0
T30	38925	190	0	0
T31	7561	19	0	0
T32	48746	127	0	0
T41	7600	11	0	0
T42	1581	7	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	582225092	19522715	0	0
T1	7293	10	0	0
T2	7698	3	0	0
T3	6346	7	0	0
T28	8471	5	0	0
T29	21708	9	0	0
T30	38925	64	0	0
T31	7561	3	0	0
T32	48746	50	0	0
T41	7600	2	0	0
T42	1581	5	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	582225092	332974	0	0
T1	7293	10	0	0
T2	7698	9	0	0
T3	6346	15	0	0
T28	8471	7	0	0
T29	21708	61	0	0
T30	38925	126	0	0
T31	7561	16	0	0
T32	48746	77	0	0
T41	7600	9	0	0
T42	1581	2	0	0