Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9707246	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10310970

1

T1

7

T2

6

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19371795	1			T1	7		T2	7		T3	3
values[0x0]	321936	1			T1	6		T2	1		T3	5
values[0x1]	324485	1			T1	5		T2	6		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7718138	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

12300078

1

T1

10

T2

10

T3

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	58673	1			T42	2		T30	1		T31	23
valid_sources[0x01]	58195	1			T30	2		T32	10		T39	3
valid_sources[0x02]	60572	1			T30	1		T32	6		T8	2
valid_sources[0x03]	73673	1			T32	11		T4	114		T9	1
valid_sources[0x04]	122108	1			T43	6		T32	13		T4	78
valid_sources[0x05]	71096	1			T31	1		T32	10		T34	1
valid_sources[0x06]	67818	1			T29	1		T30	12		T32	11
valid_sources[0x07]	79748	1			T32	13		T39	10		T4	19
valid_sources[0x08]	58654	1			T32	20		T39	11		T21	16
valid_sources[0x09]	58696	1			T29	1		T32	7		T39	7
valid_sources[0x0a]	59061	1			T42	4		T30	2		T32	4
valid_sources[0x0b]	133204	1			T32	9		T39	5		T8	1
valid_sources[0x0c]	59915	1			T32	16		T39	11		T4	53
valid_sources[0x0d]	58267	1			T30	1		T32	10		T39	2
valid_sources[0x0e]	59275	1			T32	5		T39	12		T4	18
valid_sources[0x0f]	59833	1			T31	1		T32	7		T21	6
valid_sources[0x10]	124761	1			T30	1		T32	17		T20	1
valid_sources[0x11]	58934	1			T29	1		T31	11		T32	9
valid_sources[0x12]	58868	1			T32	6		T39	2		T4	51
valid_sources[0x13]	58254	1			T2	1		T30	4		T32	8
valid_sources[0x14]	60139	1			T31	4		T32	7		T8	1
valid_sources[0x15]	59849	1			T29	4		T32	9		T39	2
valid_sources[0x16]	59327	1			T32	9		T21	45		T4	3
valid_sources[0x17]	59514	1			T32	16		T39	2		T18	1
valid_sources[0x18]	76016	1			T41	1		T32	11		T21	16
valid_sources[0x19]	58597	1			T32	13		T18	1		T4	4
valid_sources[0x1a]	59719	1			T30	2		T32	8		T39	5
valid_sources[0x1b]	60539	1			T31	7		T32	7		T21	27
valid_sources[0x1c]	58485	1			T30	6		T32	27		T34	1
valid_sources[0x1d]	119549	1			T29	9		T32	11		T8	1
valid_sources[0x1e]	59337	1			T32	24		T39	7		T8	1
valid_sources[0x1f]	164853	1			T29	2		T32	3		T4	58
valid_sources[0x20]	58172	1			T31	1		T32	14		T39	15
valid_sources[0x21]	59161	1			T31	3		T32	10		T39	9
valid_sources[0x22]	58668	1			T32	21		T8	2		T4	71
valid_sources[0x23]	59768	1			T30	6		T31	3		T32	16
valid_sources[0x24]	77991	1			T31	9		T32	22		T8	3
valid_sources[0x25]	63879	1			T30	1		T32	7		T21	5
valid_sources[0x26]	111739	1			T32	11		T39	11		T21	8
valid_sources[0x27]	57457	1			T29	1		T32	6		T9	4
valid_sources[0x28]	59088	1			T32	18		T4	29		T9	3
valid_sources[0x29]	76639	1			T32	12		T4	169		T68	2
valid_sources[0x2a]	60385	1			T32	7		T34	1		T39	3
valid_sources[0x2b]	135293	1			T32	10		T34	1		T39	8
valid_sources[0x2c]	74392	1			T32	10		T21	24		T8	1
valid_sources[0x2d]	74659	1			T41	1		T30	2		T32	11
valid_sources[0x2e]	69657	1			T32	15		T19	1		T20	1
valid_sources[0x2f]	59925	1			T32	19		T8	1		T4	37
valid_sources[0x30]	153776	1			T3	4		T32	2		T8	1
valid_sources[0x31]	218796	1			T30	11		T32	16		T4	10
valid_sources[0x32]	60426	1			T32	9		T21	27		T4	54
valid_sources[0x33]	59022	1			T32	12		T39	3		T8	1
valid_sources[0x34]	59459	1			T32	13		T39	6		T18	1
valid_sources[0x35]	83994	1			T32	18		T39	3		T8	1
valid_sources[0x36]	60020	1			T32	11		T39	7		T4	28
valid_sources[0x37]	123046	1			T27	12		T29	2		T32	13
valid_sources[0x38]	58440	1			T29	3		T31	12		T32	7
valid_sources[0x39]	59460	1			T42	9		T32	7		T18	1
valid_sources[0x3a]	58154	1			T32	10		T19	1		T4	32
valid_sources[0x3b]	59860	1			T31	6		T32	15		T39	1
valid_sources[0x3c]	75944	1			T30	2		T31	1		T32	7
valid_sources[0x3d]	59338	1			T32	17		T39	5		T18	2
valid_sources[0x3e]	58072	1			T29	1		T32	9		T19	1
valid_sources[0x3f]	75443	1			T30	1		T32	11		T19	1
valid_sources[0x40]	59192	1			T29	1		T32	10		T39	10
valid_sources[0x41]	60119	1			T29	4		T30	7		T31	4
valid_sources[0x42]	106635	1			T31	1		T32	9		T19	1
valid_sources[0x43]	136481	1			T27	1		T32	15		T39	6
valid_sources[0x44]	59402	1			T30	3		T31	8		T32	16
valid_sources[0x45]	60389	1			T29	2		T32	6		T4	43
valid_sources[0x46]	102401	1			T29	2		T32	21		T9	2
valid_sources[0x47]	67984	1			T29	1		T32	14		T39	3
valid_sources[0x48]	60319	1			T29	6		T32	18		T39	2
valid_sources[0x49]	83197	1			T32	11		T39	1		T8	1
valid_sources[0x4a]	59657	1			T32	15		T8	2		T4	113
valid_sources[0x4b]	59122	1			T42	4		T32	7		T39	5
valid_sources[0x4c]	90268	1			T41	1		T29	5		T32	5
valid_sources[0x4d]	59824	1			T29	2		T31	5		T32	6
valid_sources[0x4e]	82466	1			T43	3		T31	10		T32	13
valid_sources[0x4f]	59796	1			T32	10		T21	47		T4	28
valid_sources[0x50]	59861	1			T30	3		T32	15		T18	1
valid_sources[0x51]	76469	1			T29	2		T31	12		T32	13
valid_sources[0x52]	58889	1			T31	5		T32	7		T39	2
valid_sources[0x53]	59239	1			T32	8		T39	3		T8	1
valid_sources[0x54]	58844	1			T32	9		T39	7		T8	1
valid_sources[0x55]	58746	1			T30	5		T32	13		T8	2
valid_sources[0x56]	59633	1			T42	1		T29	14		T32	5
valid_sources[0x57]	59162	1			T30	3		T32	5		T8	1
valid_sources[0x58]	69298	1			T29	7		T32	19		T39	1
valid_sources[0x59]	58566	1			T32	14		T4	54		T6	78
valid_sources[0x5a]	59140	1			T31	2		T32	20		T4	81
valid_sources[0x5b]	58327	1			T32	15		T8	2		T4	2
valid_sources[0x5c]	59753	1			T32	11		T39	2		T4	23
valid_sources[0x5d]	69318	1			T30	3		T31	11		T32	12
valid_sources[0x5e]	59819	1			T30	2		T32	9		T39	3
valid_sources[0x5f]	129527	1			T30	1		T32	10		T39	2
valid_sources[0x60]	129923	1			T31	3		T32	12		T39	1
valid_sources[0x61]	270118	1			T32	19		T88	389		T9	2
valid_sources[0x62]	135899	1			T32	10		T34	1		T39	1
valid_sources[0x63]	58609	1			T3	8		T32	19		T39	7
valid_sources[0x64]	58691	1			T32	8		T39	1		T8	3
valid_sources[0x65]	58640	1			T30	14		T32	16		T39	5
valid_sources[0x66]	58520	1			T41	1		T29	2		T32	13
valid_sources[0x67]	60036	1			T43	8		T32	7		T39	6
valid_sources[0x68]	59181	1			T30	2		T31	9		T32	13
valid_sources[0x69]	59568	1			T31	1		T32	8		T21	51
valid_sources[0x6a]	59641	1			T32	13		T18	1		T4	65
valid_sources[0x6b]	59662	1			T29	5		T32	17		T39	5
valid_sources[0x6c]	87002	1			T32	19		T39	12		T4	31
valid_sources[0x6d]	59420	1			T32	22		T39	3		T4	40
valid_sources[0x6e]	58501	1			T32	10		T39	2		T21	6
valid_sources[0x6f]	59319	1			T29	1		T30	15		T32	22
valid_sources[0x70]	58606	1			T29	2		T32	8		T34	1
valid_sources[0x71]	58986	1			T30	3		T32	12		T39	3
valid_sources[0x72]	60029	1			T29	5		T32	15		T21	16
valid_sources[0x73]	82652	1			T32	17		T39	16		T4	21
valid_sources[0x74]	152695	1			T30	1		T32	27		T20	1
valid_sources[0x75]	59409	1			T31	7		T32	13		T21	12
valid_sources[0x76]	59885	1			T31	9		T32	15		T8	1
valid_sources[0x77]	77413	1			T30	1		T31	5		T32	2
valid_sources[0x78]	111900	1			T31	10		T32	13		T34	1
valid_sources[0x79]	70479	1			T29	4		T32	13		T39	15
valid_sources[0x7a]	59022	1			T29	2		T43	10		T32	14
valid_sources[0x7b]	63071	1			T29	10		T32	18		T39	8
valid_sources[0x7c]	59507	1			T32	7		T19	1		T21	43
valid_sources[0x7d]	58868	1			T32	21		T34	1		T21	1
valid_sources[0x7e]	123294	1			T42	1		T29	1		T30	2
valid_sources[0x7f]	59068	1			T43	13		T32	10		T39	1
valid_sources[0x80]	58599	1			T29	1		T32	15		T39	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9793703

1

T1

2

T2

4

T40

1

values[0x0]

all_enables

biggest_size

267196

1

T1

2

T2

1

T3

2

values[0x1]

all_enables

biggest_size

250071

1

T1

3

T2

1

T3

3