Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

9722552

1

T1

11

T2

8

T3

7

full_word

10311995

1

T1

7

T2

6

T3

5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	20034227	1			T1	18		T2	14		T3	12
auto[TlIntgErrCmd]	129	1			T206	5		T237	4		T238	7
auto[TlIntgErrData]	109	1			T206	2		T237	5		T238	9
auto[TlIntgErrBoth]	82	1			T206	3		T237	1		T238	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19373675

1

T1

7

T2

7

T3

3

auto[1]

660872

1

T1

11

T2

7

T3

9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9579651	1			T1	5		T2	3		T3	3
auto[TlIntgErrNone]	partial	auto[1]	142606	1			T1	6		T2	5		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	9793895	1			T1	2		T2	4		T40	1
auto[TlIntgErrNone]	full_word	auto[1]	518075	1			T1	5		T2	2		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T206	3		T237	1		T238	1
auto[TlIntgErrCmd]	partial	auto[1]	78	1			T206	2		T237	2		T238	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T237	1		T238	1		T543	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T238	1		T251	1		T545	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T206	1		T237	3		T238	5
auto[TlIntgErrData]	partial	auto[1]	52	1			T206	1		T237	2		T238	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T543	1		T546	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	9	1			T238	2		T251	1		T547	2
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T206	1		T251	2		T547	1
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T206	2		T237	1		T238	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T547	1		T542	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T546	1		-	-		-	-