Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	580407123	12784	0	0
ep_in_enable_rd_A	580407123	2237	0	0
ep_out_enable_rd_A	580407123	2031	0	0
in_iso_rd_A	580407123	2600	0	0
intr_enable_rd_A	580407123	2882	0	0
out_iso_rd_A	580407123	2280	0	0
phy_config_rd_A	580407123	1585	0	0
phy_pins_drive_rd_A	580407123	1609	0	0
rxenable_setup_rd_A	580407123	2169	0	0
set_nak_out_rd_A	580407123	2136	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580407123	12784	0	0
T204	2877	6	0	0
T205	3158	9	0	0
T206	15619	4	0	0
T230	7501	821	0	0
T231	7208	298	0	0
T237	19297	3	0	0
T238	33588	3	0	0
T239	11397	700	0	0
T240	12202	632	0	0
T250	3967	16	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580407123	2237	0	0
T242	4995	45	0	0
T251	51419	600	0	0
T260	3995	4	0	0
T264	9653	75	0	0
T265	17054	129	0	0
T267	42187	216	0	0
T273	15391	33	0	0
T276	8831	20	0	0
T277	4707	54	0	0
T278	2689	30	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580407123	2031	0	0
T242	4995	59	0	0
T251	51419	559	0	0
T260	3995	1	0	0
T264	9653	60	0	0
T265	17054	91	0	0
T267	42187	216	0	0
T273	15391	54	0	0
T276	8831	1	0	0
T277	4707	8	0	0
T278	2689	8	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580407123	2600	0	0
T242	4995	4	0	0
T247	11348	7	0	0
T251	51419	757	0	0
T264	9653	90	0	0
T265	17054	90	0	0
T267	42187	195	0	0
T273	15391	25	0	0
T276	8831	8	0	0
T277	4707	10	0	0
T278	2689	45	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580407123	2882	0	0
T212	2752	5	0	0
T215	2815	24	0	0
T251	51419	543	0	0
T260	3995	8	0	0
T264	9653	80	0	0
T265	17054	67	0	0
T267	42187	244	0	0
T273	15391	47	0	0
T277	4707	85	0	0
T279	2737	28	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580407123	2280	0	0
T242	4995	8	0	0
T251	51419	566	0	0
T264	9653	94	0	0
T265	17054	110	0	0
T267	42187	223	0	0
T273	15391	47	0	0
T276	8831	15	0	0
T277	4707	8	0	0
T278	2689	5	0	0
T280	15212	19	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580407123	1585	0	0
T242	4995	20	0	0
T251	51419	286	0	0
T260	3995	5	0	0
T264	9653	72	0	0
T265	17054	128	0	0
T267	42187	216	0	0
T273	15391	9	0	0
T276	8831	4	0	0
T277	4707	23	0	0
T278	2689	19	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580407123	1609	0	0
T242	4995	14	0	0
T251	51419	267	0	0
T264	9653	109	0	0
T265	17054	106	0	0
T267	42187	214	0	0
T273	15391	24	0	0
T276	8831	16	0	0
T277	4707	9	0	0
T278	2689	3	0	0
T280	15212	21	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580407123	2169	0	0
T240	12202	1	0	0
T242	4995	64	0	0
T251	51419	620	0	0
T260	3995	6	0	0
T264	9653	81	0	0
T265	17054	103	0	0
T267	42187	247	0	0
T273	15391	41	0	0
T276	8831	9	0	0
T277	4707	7	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	580407123	2136	0	0
T240	12202	3	0	0
T242	4995	5	0	0
T251	51419	357	0	0
T260	3995	13	0	0
T264	9653	83	0	0
T265	17054	109	0	0
T267	42187	227	0	0
T273	15391	38	0	0
T277	4707	65	0	0
T280	15212	65	0	0